[mirror_ubuntu-zesty-kernel.git] / arch / mips / kvm / interrupt.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * KVM/MIPS: Interrupt delivery
 *
 * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
 * Authors: Sanjay Lal <sanjayl@kymasys.com>
 */

#include <linux/errno.h>
#include <linux/err.h>
#include <linux/vmalloc.h>
#include <linux/fs.h>
#include <linux/bootmem.h>
#include <asm/page.h>
#include <asm/cacheflush.h>

#include <linux/kvm_host.h>

#include "interrupt.h"

void kvm_mips_queue_irq(struct kvm_vcpu *vcpu, unsigned int priority)
{
	set_bit(priority, &vcpu->arch.pending_exceptions);
}

void kvm_mips_dequeue_irq(struct kvm_vcpu *vcpu, unsigned int priority)
{
	clear_bit(priority, &vcpu->arch.pending_exceptions);
}

void kvm_mips_queue_timer_int_cb(struct kvm_vcpu *vcpu)
{
	/*
	 * Cause bits to reflect the pending timer interrupt,
	 * the EXC code will be set when we are actually
	 * delivering the interrupt:
	 */
	kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ5 | C_TI));

	/* Queue up an INT exception for the core */
	kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_TIMER);

}

void kvm_mips_dequeue_timer_int_cb(struct kvm_vcpu *vcpu)
{
	kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ5 | C_TI));
	kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_TIMER);
}

void kvm_mips_queue_io_int_cb(struct kvm_vcpu *vcpu,
			      struct kvm_mips_interrupt *irq)
{
	int intr = (int)irq->irq;

	/*
	 * Cause bits to reflect the pending IO interrupt,
	 * the EXC code will be set when we are actually
	 * delivering the interrupt:
	 */
	switch (intr) {
	case 2:
		kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ0));
		/* Queue up an INT exception for the core */
		kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_IO);
		break;

	case 3:
		kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ1));
		kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_IPI_1);
		break;

	case 4:
		kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ2));
		kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_IPI_2);
		break;

	default:
		break;
	}

}

void kvm_mips_dequeue_io_int_cb(struct kvm_vcpu *vcpu,
				struct kvm_mips_interrupt *irq)
{
	int intr = (int)irq->irq;

	switch (intr) {
	case -2:
		kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ0));
		kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_IO);
		break;

	case -3:
		kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ1));
		kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_IPI_1);
		break;

	case -4:
		kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ2));
		kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_IPI_2);
		break;

	default:
		break;
	}

}

/* Deliver the interrupt of the corresponding priority, if possible. */
int kvm_mips_irq_deliver_cb(struct kvm_vcpu *vcpu, unsigned int priority,
			    u32 cause)
{
	int allowed = 0;
	u32 exccode;

	struct kvm_vcpu_arch *arch = &vcpu->arch;
	struct mips_coproc *cop0 = vcpu->arch.cop0;

	switch (priority) {
	case MIPS_EXC_INT_TIMER:
		if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
		    && (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL)))
		    && (kvm_read_c0_guest_status(cop0) & IE_IRQ5)) {
			allowed = 1;
			exccode = EXCCODE_INT;
		}
		break;

	case MIPS_EXC_INT_IO:
		if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
		    && (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL)))
		    && (kvm_read_c0_guest_status(cop0) & IE_IRQ0)) {
			allowed = 1;
			exccode = EXCCODE_INT;
		}
		break;

	case MIPS_EXC_INT_IPI_1:
		if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
		    && (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL)))
		    && (kvm_read_c0_guest_status(cop0) & IE_IRQ1)) {
			allowed = 1;
			exccode = EXCCODE_INT;
		}
		break;

	case MIPS_EXC_INT_IPI_2:
		if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
		    && (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL | ST0_ERL)))
		    && (kvm_read_c0_guest_status(cop0) & IE_IRQ2)) {
			allowed = 1;
			exccode = EXCCODE_INT;
		}
		break;

	default:
		break;
	}

	/* Are we allowed to deliver the interrupt ??? */
	if (allowed) {
		if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
			/* save old pc */
			kvm_write_c0_guest_epc(cop0, arch->pc);
			kvm_set_c0_guest_status(cop0, ST0_EXL);

			if (cause & CAUSEF_BD)
				kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
			else
				kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);

			kvm_debug("Delivering INT @ pc %#lx\n", arch->pc);

		} else
			kvm_err("Trying to deliver interrupt when EXL is already set\n");

		kvm_change_c0_guest_cause(cop0, CAUSEF_EXCCODE,
					  (exccode << CAUSEB_EXCCODE));

		/* XXXSL Set PC to the interrupt exception entry point */
		if (kvm_read_c0_guest_cause(cop0) & CAUSEF_IV)
			arch->pc = KVM_GUEST_KSEG0 + 0x200;
		else
			arch->pc = KVM_GUEST_KSEG0 + 0x180;

		clear_bit(priority, &vcpu->arch.pending_exceptions);
	}

	return allowed;
}

int kvm_mips_irq_clear_cb(struct kvm_vcpu *vcpu, unsigned int priority,
			  u32 cause)
{
	return 1;
}

void kvm_mips_deliver_interrupts(struct kvm_vcpu *vcpu, u32 cause)
{
	unsigned long *pending = &vcpu->arch.pending_exceptions;
	unsigned long *pending_clr = &vcpu->arch.pending_exceptions_clr;
	unsigned int priority;

	if (!(*pending) && !(*pending_clr))
		return;

	priority = __ffs(*pending_clr);
	while (priority <= MIPS_EXC_MAX) {
		if (kvm_mips_callbacks->irq_clear(vcpu, priority, cause)) {
			if (!KVM_MIPS_IRQ_CLEAR_ALL_AT_ONCE)
				break;
		}

		priority = find_next_bit(pending_clr,
					 BITS_PER_BYTE * sizeof(*pending_clr),
					 priority + 1);
	}

	priority = __ffs(*pending);
	while (priority <= MIPS_EXC_MAX) {
		if (kvm_mips_callbacks->irq_deliver(vcpu, priority, cause)) {
			if (!KVM_MIPS_IRQ_DELIVER_ALL_AT_ONCE)
				break;
		}

		priority = find_next_bit(pending,
					 BITS_PER_BYTE * sizeof(*pending),
					 priority + 1);
	}

}

int kvm_mips_pending_timer(struct kvm_vcpu *vcpu)
{
	return test_bit(MIPS_EXC_INT_TIMER, &vcpu->arch.pending_exceptions);
}
Commit	Line	Data
06d1838d	1	/*
d116e812 DCZ	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* KVM/MIPS: Interrupt delivery
	7	*
	8	* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
	9	* Authors: Sanjay Lal <sanjayl@kymasys.com>
	10	*/
06d1838d SL	11
	12	#include <linux/errno.h>
	13	#include <linux/err.h>
06d1838d SL	14	#include <linux/vmalloc.h>
	15	#include <linux/fs.h>
	16	#include <linux/bootmem.h>
	17	#include <asm/page.h>
	18	#include <asm/cacheflush.h>
	19
	20	#include <linux/kvm_host.h>
	21
d7d5b05f	22	#include "interrupt.h"
06d1838d	23
bdb7ed86	24	void kvm_mips_queue_irq(struct kvm_vcpu *vcpu, unsigned int priority)
06d1838d SL	25	{
	26	set_bit(priority, &vcpu->arch.pending_exceptions);
	27	}
	28
bdb7ed86	29	void kvm_mips_dequeue_irq(struct kvm_vcpu *vcpu, unsigned int priority)
06d1838d SL	30	{
	31	clear_bit(priority, &vcpu->arch.pending_exceptions);
	32	}
	33
	34	void kvm_mips_queue_timer_int_cb(struct kvm_vcpu *vcpu)
	35	{
d116e812 DCZ	36	/*
d116e812 DCZ	37	* Cause bits to reflect the pending timer interrupt,
06d1838d SL	38	* the EXC code will be set when we are actually
	39	* delivering the interrupt:
	40	*/
	41	kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ5 \| C_TI));
	42
	43	/* Queue up an INT exception for the core */
	44	kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_TIMER);
	45
	46	}
	47
	48	void kvm_mips_dequeue_timer_int_cb(struct kvm_vcpu *vcpu)
	49	{
	50	kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ5 \| C_TI));
	51	kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_TIMER);
	52	}
	53
d116e812 DCZ	54	void kvm_mips_queue_io_int_cb(struct kvm_vcpu *vcpu,
d116e812 DCZ	55	struct kvm_mips_interrupt *irq)
06d1838d SL	56	{
	57	int intr = (int)irq->irq;
	58
d116e812 DCZ	59	/*
d116e812 DCZ	60	* Cause bits to reflect the pending IO interrupt,
06d1838d SL	61	* the EXC code will be set when we are actually
	62	* delivering the interrupt:
	63	*/
	64	switch (intr) {
	65	case 2:
	66	kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ0));
	67	/* Queue up an INT exception for the core */
	68	kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_IO);
	69	break;
	70
	71	case 3:
	72	kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ1));
	73	kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_IPI_1);
	74	break;
	75
	76	case 4:
	77	kvm_set_c0_guest_cause(vcpu->arch.cop0, (C_IRQ2));
	78	kvm_mips_queue_irq(vcpu, MIPS_EXC_INT_IPI_2);
	79	break;
	80
	81	default:
	82	break;
	83	}
	84
	85	}
	86
d116e812 DCZ	87	void kvm_mips_dequeue_io_int_cb(struct kvm_vcpu *vcpu,
d116e812 DCZ	88	struct kvm_mips_interrupt *irq)
06d1838d SL	89	{
06d1838d SL	90	int intr = (int)irq->irq;
d116e812	91
06d1838d SL	92	switch (intr) {
	93	case -2:
	94	kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ0));
	95	kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_IO);
	96	break;
	97
	98	case -3:
	99	kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ1));
	100	kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_IPI_1);
	101	break;
	102
	103	case -4:
	104	kvm_clear_c0_guest_cause(vcpu->arch.cop0, (C_IRQ2));
	105	kvm_mips_dequeue_irq(vcpu, MIPS_EXC_INT_IPI_2);
	106	break;
	107
	108	default:
	109	break;
	110	}
	111
	112	}
	113
	114	/* Deliver the interrupt of the corresponding priority, if possible. */
d116e812	115	int kvm_mips_irq_deliver_cb(struct kvm_vcpu *vcpu, unsigned int priority,
bdb7ed86	116	u32 cause)
06d1838d SL	117	{
06d1838d SL	118	int allowed = 0;
8cffd197	119	u32 exccode;
06d1838d SL	120
	121	struct kvm_vcpu_arch *arch = &vcpu->arch;
	122	struct mips_coproc *cop0 = vcpu->arch.cop0;
	123
	124	switch (priority) {
	125	case MIPS_EXC_INT_TIMER:
	126	if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
	127	&& (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL \| ST0_ERL)))
	128	&& (kvm_read_c0_guest_status(cop0) & IE_IRQ5)) {
	129	allowed = 1;
16d100db	130	exccode = EXCCODE_INT;
06d1838d SL	131	}
	132	break;
	133
	134	case MIPS_EXC_INT_IO:
	135	if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
	136	&& (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL \| ST0_ERL)))
	137	&& (kvm_read_c0_guest_status(cop0) & IE_IRQ0)) {
	138	allowed = 1;
16d100db	139	exccode = EXCCODE_INT;
06d1838d SL	140	}
	141	break;
	142
	143	case MIPS_EXC_INT_IPI_1:
	144	if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
	145	&& (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL \| ST0_ERL)))
	146	&& (kvm_read_c0_guest_status(cop0) & IE_IRQ1)) {
	147	allowed = 1;
16d100db	148	exccode = EXCCODE_INT;
06d1838d SL	149	}
	150	break;
	151
	152	case MIPS_EXC_INT_IPI_2:
	153	if ((kvm_read_c0_guest_status(cop0) & ST0_IE)
	154	&& (!(kvm_read_c0_guest_status(cop0) & (ST0_EXL \| ST0_ERL)))
	155	&& (kvm_read_c0_guest_status(cop0) & IE_IRQ2)) {
	156	allowed = 1;
16d100db	157	exccode = EXCCODE_INT;
06d1838d SL	158	}
	159	break;
	160
	161	default:
	162	break;
	163	}
	164
	165	/* Are we allowed to deliver the interrupt ??? */
	166	if (allowed) {
06d1838d SL	167	if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
	168	/* save old pc */
	169	kvm_write_c0_guest_epc(cop0, arch->pc);
	170	kvm_set_c0_guest_status(cop0, ST0_EXL);
	171
	172	if (cause & CAUSEF_BD)
	173	kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
	174	else
	175	kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
	176
	177	kvm_debug("Delivering INT @ pc %#lx\n", arch->pc);
	178
	179	} else
	180	kvm_err("Trying to deliver interrupt when EXL is already set\n");
	181
	182	kvm_change_c0_guest_cause(cop0, CAUSEF_EXCCODE,
	183	(exccode << CAUSEB_EXCCODE));
	184
	185	/* XXXSL Set PC to the interrupt exception entry point */
	186	if (kvm_read_c0_guest_cause(cop0) & CAUSEF_IV)
	187	arch->pc = KVM_GUEST_KSEG0 + 0x200;
	188	else
	189	arch->pc = KVM_GUEST_KSEG0 + 0x180;
	190
	191	clear_bit(priority, &vcpu->arch.pending_exceptions);
	192	}
	193
	194	return allowed;
	195	}
	196
d116e812	197	int kvm_mips_irq_clear_cb(struct kvm_vcpu *vcpu, unsigned int priority,
bdb7ed86	198	u32 cause)
06d1838d SL	199	{
	200	return 1;
	201	}
	202
bdb7ed86	203	void kvm_mips_deliver_interrupts(struct kvm_vcpu *vcpu, u32 cause)
06d1838d SL	204	{
	205	unsigned long *pending = &vcpu->arch.pending_exceptions;
	206	unsigned long *pending_clr = &vcpu->arch.pending_exceptions_clr;
	207	unsigned int priority;
	208
	209	if (!(pending) && !(pending_clr))
	210	return;
	211
	212	priority = __ffs(*pending_clr);
	213	while (priority <= MIPS_EXC_MAX) {
	214	if (kvm_mips_callbacks->irq_clear(vcpu, priority, cause)) {
	215	if (!KVM_MIPS_IRQ_CLEAR_ALL_AT_ONCE)
	216	break;
	217	}
	218
	219	priority = find_next_bit(pending_clr,
	220	BITS_PER_BYTE * sizeof(*pending_clr),
	221	priority + 1);
	222	}
	223
	224	priority = __ffs(*pending);
	225	while (priority <= MIPS_EXC_MAX) {
	226	if (kvm_mips_callbacks->irq_deliver(vcpu, priority, cause)) {
	227	if (!KVM_MIPS_IRQ_DELIVER_ALL_AT_ONCE)
	228	break;
	229	}
	230
	231	priority = find_next_bit(pending,
	232	BITS_PER_BYTE * sizeof(*pending),
	233	priority + 1);
	234	}
	235
	236	}
	237
	238	int kvm_mips_pending_timer(struct kvm_vcpu *vcpu)
	239	{
	240	return test_bit(MIPS_EXC_INT_TIMER, &vcpu->arch.pending_exceptions);
	241	}