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Commit | Line | Data |
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669e846e SL |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * KVM/MIPS: MIPS specific KVM APIs | |
7 | * | |
8 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
9 | * Authors: Sanjay Lal <sanjayl@kymasys.com> | |
d116e812 | 10 | */ |
669e846e | 11 | |
05108709 | 12 | #include <linux/bitops.h> |
669e846e SL |
13 | #include <linux/errno.h> |
14 | #include <linux/err.h> | |
98e91b84 | 15 | #include <linux/kdebug.h> |
669e846e | 16 | #include <linux/module.h> |
d852b5f3 | 17 | #include <linux/uaccess.h> |
669e846e | 18 | #include <linux/vmalloc.h> |
174cd4b1 | 19 | #include <linux/sched/signal.h> |
669e846e SL |
20 | #include <linux/fs.h> |
21 | #include <linux/bootmem.h> | |
174cd4b1 | 22 | |
f798217d | 23 | #include <asm/fpu.h> |
669e846e SL |
24 | #include <asm/page.h> |
25 | #include <asm/cacheflush.h> | |
26 | #include <asm/mmu_context.h> | |
06c158c9 | 27 | #include <asm/pgalloc.h> |
c4c6f2ca | 28 | #include <asm/pgtable.h> |
669e846e SL |
29 | |
30 | #include <linux/kvm_host.h> | |
31 | ||
d7d5b05f DCZ |
32 | #include "interrupt.h" |
33 | #include "commpage.h" | |
669e846e SL |
34 | |
35 | #define CREATE_TRACE_POINTS | |
36 | #include "trace.h" | |
37 | ||
38 | #ifndef VECTORSPACING | |
39 | #define VECTORSPACING 0x100 /* for EI/VI mode */ | |
40 | #endif | |
41 | ||
d116e812 | 42 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x) |
669e846e | 43 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
d116e812 DCZ |
44 | { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU }, |
45 | { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU }, | |
46 | { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU }, | |
47 | { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU }, | |
48 | { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU }, | |
49 | { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU }, | |
50 | { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU }, | |
51 | { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU }, | |
52 | { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU }, | |
53 | { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU }, | |
54 | { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU }, | |
55 | { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU }, | |
56 | { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU }, | |
0a560427 | 57 | { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU }, |
c2537ed9 | 58 | { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU }, |
1c0cd66a | 59 | { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU }, |
c2537ed9 | 60 | { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU }, |
d116e812 | 61 | { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU }, |
f7819512 | 62 | { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU }, |
62bea5bf | 63 | { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU }, |
3491caf2 | 64 | { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU }, |
d116e812 | 65 | { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU }, |
669e846e SL |
66 | {NULL} |
67 | }; | |
68 | ||
d116e812 DCZ |
69 | /* |
70 | * XXXKYMA: We are simulatoring a processor that has the WII bit set in | |
71 | * Config7, so we are "runnable" if interrupts are pending | |
669e846e SL |
72 | */ |
73 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) | |
74 | { | |
75 | return !!(vcpu->arch.pending_exceptions); | |
76 | } | |
77 | ||
78 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) | |
79 | { | |
80 | return 1; | |
81 | } | |
82 | ||
13a34e06 | 83 | int kvm_arch_hardware_enable(void) |
669e846e SL |
84 | { |
85 | return 0; | |
86 | } | |
87 | ||
669e846e SL |
88 | int kvm_arch_hardware_setup(void) |
89 | { | |
90 | return 0; | |
91 | } | |
92 | ||
669e846e SL |
93 | void kvm_arch_check_processor_compat(void *rtn) |
94 | { | |
d98403a5 | 95 | *(int *)rtn = 0; |
669e846e SL |
96 | } |
97 | ||
669e846e SL |
98 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
99 | { | |
06c158c9 JH |
100 | /* Allocate page table to map GPA -> RPA */ |
101 | kvm->arch.gpa_mm.pgd = kvm_pgd_alloc(); | |
102 | if (!kvm->arch.gpa_mm.pgd) | |
103 | return -ENOMEM; | |
104 | ||
669e846e SL |
105 | return 0; |
106 | } | |
107 | ||
235539b4 LC |
108 | bool kvm_arch_has_vcpu_debugfs(void) |
109 | { | |
110 | return false; | |
111 | } | |
112 | ||
113 | int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu) | |
114 | { | |
115 | return 0; | |
116 | } | |
117 | ||
669e846e SL |
118 | void kvm_mips_free_vcpus(struct kvm *kvm) |
119 | { | |
120 | unsigned int i; | |
121 | struct kvm_vcpu *vcpu; | |
122 | ||
669e846e SL |
123 | kvm_for_each_vcpu(i, vcpu, kvm) { |
124 | kvm_arch_vcpu_free(vcpu); | |
125 | } | |
126 | ||
127 | mutex_lock(&kvm->lock); | |
128 | ||
129 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
130 | kvm->vcpus[i] = NULL; | |
131 | ||
132 | atomic_set(&kvm->online_vcpus, 0); | |
133 | ||
134 | mutex_unlock(&kvm->lock); | |
135 | } | |
136 | ||
06c158c9 JH |
137 | static void kvm_mips_free_gpa_pt(struct kvm *kvm) |
138 | { | |
139 | /* It should always be safe to remove after flushing the whole range */ | |
140 | WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0)); | |
141 | pgd_free(NULL, kvm->arch.gpa_mm.pgd); | |
142 | } | |
143 | ||
669e846e SL |
144 | void kvm_arch_destroy_vm(struct kvm *kvm) |
145 | { | |
146 | kvm_mips_free_vcpus(kvm); | |
06c158c9 | 147 | kvm_mips_free_gpa_pt(kvm); |
669e846e SL |
148 | } |
149 | ||
d116e812 DCZ |
150 | long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, |
151 | unsigned long arg) | |
669e846e | 152 | { |
ed829857 | 153 | return -ENOIOCTLCMD; |
669e846e SL |
154 | } |
155 | ||
5587027c AK |
156 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
157 | unsigned long npages) | |
669e846e SL |
158 | { |
159 | return 0; | |
160 | } | |
161 | ||
b6209110 JH |
162 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
163 | { | |
164 | /* Flush whole GPA */ | |
165 | kvm_mips_flush_gpa_pt(kvm, 0, ~0); | |
166 | ||
167 | /* Let implementation do the rest */ | |
168 | kvm_mips_callbacks->flush_shadow_all(kvm); | |
169 | } | |
170 | ||
171 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, | |
172 | struct kvm_memory_slot *slot) | |
173 | { | |
174 | /* | |
175 | * The slot has been made invalid (ready for moving or deletion), so we | |
176 | * need to ensure that it can no longer be accessed by any guest VCPUs. | |
177 | */ | |
178 | ||
179 | spin_lock(&kvm->mmu_lock); | |
180 | /* Flush slot from GPA */ | |
181 | kvm_mips_flush_gpa_pt(kvm, slot->base_gfn, | |
182 | slot->base_gfn + slot->npages - 1); | |
183 | /* Let implementation do the rest */ | |
184 | kvm_mips_callbacks->flush_shadow_memslot(kvm, slot); | |
185 | spin_unlock(&kvm->mmu_lock); | |
186 | } | |
187 | ||
669e846e | 188 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
d116e812 | 189 | struct kvm_memory_slot *memslot, |
09170a49 | 190 | const struct kvm_userspace_memory_region *mem, |
d116e812 | 191 | enum kvm_mr_change change) |
669e846e SL |
192 | { |
193 | return 0; | |
194 | } | |
195 | ||
196 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
09170a49 | 197 | const struct kvm_userspace_memory_region *mem, |
d116e812 | 198 | const struct kvm_memory_slot *old, |
f36f3f28 | 199 | const struct kvm_memory_slot *new, |
d116e812 | 200 | enum kvm_mr_change change) |
669e846e | 201 | { |
a1ac9e17 JH |
202 | int needs_flush; |
203 | ||
669e846e SL |
204 | kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n", |
205 | __func__, kvm, mem->slot, mem->guest_phys_addr, | |
206 | mem->memory_size, mem->userspace_addr); | |
a1ac9e17 JH |
207 | |
208 | /* | |
209 | * If dirty page logging is enabled, write protect all pages in the slot | |
210 | * ready for dirty logging. | |
211 | * | |
212 | * There is no need to do this in any of the following cases: | |
213 | * CREATE: No dirty mappings will already exist. | |
214 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
215 | * kvm_arch_flush_shadow_memslot() | |
216 | */ | |
217 | if (change == KVM_MR_FLAGS_ONLY && | |
218 | (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) && | |
219 | new->flags & KVM_MEM_LOG_DIRTY_PAGES)) { | |
220 | spin_lock(&kvm->mmu_lock); | |
221 | /* Write protect GPA page table entries */ | |
222 | needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn, | |
223 | new->base_gfn + new->npages - 1); | |
224 | /* Let implementation do the rest */ | |
225 | if (needs_flush) | |
226 | kvm_mips_callbacks->flush_shadow_memslot(kvm, new); | |
227 | spin_unlock(&kvm->mmu_lock); | |
228 | } | |
669e846e SL |
229 | } |
230 | ||
d7b8f890 JH |
231 | static inline void dump_handler(const char *symbol, void *start, void *end) |
232 | { | |
233 | u32 *p; | |
234 | ||
235 | pr_debug("LEAF(%s)\n", symbol); | |
236 | ||
237 | pr_debug("\t.set push\n"); | |
238 | pr_debug("\t.set noreorder\n"); | |
239 | ||
240 | for (p = start; p < (u32 *)end; ++p) | |
241 | pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p); | |
242 | ||
243 | pr_debug("\t.set\tpop\n"); | |
244 | ||
245 | pr_debug("\tEND(%s)\n", symbol); | |
246 | } | |
247 | ||
669e846e SL |
248 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id) |
249 | { | |
90e9311a | 250 | int err, size; |
a7cfa7ac | 251 | void *gebase, *p, *handler, *refill_start, *refill_end; |
669e846e SL |
252 | int i; |
253 | ||
254 | struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL); | |
255 | ||
256 | if (!vcpu) { | |
257 | err = -ENOMEM; | |
258 | goto out; | |
259 | } | |
260 | ||
261 | err = kvm_vcpu_init(vcpu, kvm, id); | |
262 | ||
263 | if (err) | |
264 | goto out_free_cpu; | |
265 | ||
6e95bfd2 | 266 | kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu); |
669e846e | 267 | |
d116e812 DCZ |
268 | /* |
269 | * Allocate space for host mode exception handlers that handle | |
669e846e SL |
270 | * guest mode exits |
271 | */ | |
d116e812 | 272 | if (cpu_has_veic || cpu_has_vint) |
669e846e | 273 | size = 0x200 + VECTORSPACING * 64; |
d116e812 | 274 | else |
7006e2df | 275 | size = 0x4000; |
669e846e | 276 | |
669e846e SL |
277 | gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL); |
278 | ||
279 | if (!gebase) { | |
280 | err = -ENOMEM; | |
585bb8f9 | 281 | goto out_uninit_cpu; |
669e846e | 282 | } |
6e95bfd2 JH |
283 | kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n", |
284 | ALIGN(size, PAGE_SIZE), gebase); | |
669e846e | 285 | |
2a06dab8 JH |
286 | /* |
287 | * Check new ebase actually fits in CP0_EBase. The lack of a write gate | |
288 | * limits us to the low 512MB of physical address space. If the memory | |
289 | * we allocate is out of range, just give up now. | |
290 | */ | |
291 | if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) { | |
292 | kvm_err("CP0_EBase.WG required for guest exception base %pK\n", | |
293 | gebase); | |
294 | err = -ENOMEM; | |
295 | goto out_free_gebase; | |
296 | } | |
297 | ||
669e846e SL |
298 | /* Save new ebase */ |
299 | vcpu->arch.guest_ebase = gebase; | |
300 | ||
90e9311a | 301 | /* Build guest exception vectors dynamically in unmapped memory */ |
1f9ca62c | 302 | handler = gebase + 0x2000; |
669e846e | 303 | |
a7cfa7ac JH |
304 | /* TLB refill */ |
305 | refill_start = gebase; | |
306 | refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler); | |
669e846e SL |
307 | |
308 | /* General Exception Entry point */ | |
1f9ca62c | 309 | kvm_mips_build_exception(gebase + 0x180, handler); |
669e846e SL |
310 | |
311 | /* For vectored interrupts poke the exception code @ all offsets 0-7 */ | |
312 | for (i = 0; i < 8; i++) { | |
313 | kvm_debug("L1 Vectored handler @ %p\n", | |
314 | gebase + 0x200 + (i * VECTORSPACING)); | |
1f9ca62c JH |
315 | kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING, |
316 | handler); | |
669e846e SL |
317 | } |
318 | ||
90e9311a | 319 | /* General exit handler */ |
1f9ca62c | 320 | p = handler; |
90e9311a JH |
321 | p = kvm_mips_build_exit(p); |
322 | ||
323 | /* Guest entry routine */ | |
324 | vcpu->arch.vcpu_run = p; | |
325 | p = kvm_mips_build_vcpu_run(p); | |
797179bc | 326 | |
d7b8f890 JH |
327 | /* Dump the generated code */ |
328 | pr_debug("#include <asm/asm.h>\n"); | |
329 | pr_debug("#include <asm/regdef.h>\n"); | |
330 | pr_debug("\n"); | |
331 | dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p); | |
a7cfa7ac | 332 | dump_handler("kvm_tlb_refill", refill_start, refill_end); |
d7b8f890 JH |
333 | dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200); |
334 | dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run); | |
335 | ||
669e846e | 336 | /* Invalidate the icache for these ranges */ |
32eb12a6 JH |
337 | flush_icache_range((unsigned long)gebase, |
338 | (unsigned long)gebase + ALIGN(size, PAGE_SIZE)); | |
669e846e | 339 | |
d116e812 DCZ |
340 | /* |
341 | * Allocate comm page for guest kernel, a TLB will be reserved for | |
342 | * mapping GVA @ 0xFFFF8000 to this page | |
343 | */ | |
669e846e SL |
344 | vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL); |
345 | ||
346 | if (!vcpu->arch.kseg0_commpage) { | |
347 | err = -ENOMEM; | |
348 | goto out_free_gebase; | |
349 | } | |
350 | ||
6e95bfd2 | 351 | kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage); |
669e846e SL |
352 | kvm_mips_commpage_init(vcpu); |
353 | ||
354 | /* Init */ | |
355 | vcpu->arch.last_sched_cpu = -1; | |
356 | ||
357 | /* Start off the timer */ | |
e30492bb | 358 | kvm_mips_init_count(vcpu); |
669e846e SL |
359 | |
360 | return vcpu; | |
361 | ||
362 | out_free_gebase: | |
363 | kfree(gebase); | |
364 | ||
585bb8f9 JH |
365 | out_uninit_cpu: |
366 | kvm_vcpu_uninit(vcpu); | |
367 | ||
669e846e SL |
368 | out_free_cpu: |
369 | kfree(vcpu); | |
370 | ||
371 | out: | |
372 | return ERR_PTR(err); | |
373 | } | |
374 | ||
375 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
376 | { | |
377 | hrtimer_cancel(&vcpu->arch.comparecount_timer); | |
378 | ||
379 | kvm_vcpu_uninit(vcpu); | |
380 | ||
381 | kvm_mips_dump_stats(vcpu); | |
382 | ||
aba85929 | 383 | kvm_mmu_free_memory_caches(vcpu); |
c6c0a663 JH |
384 | kfree(vcpu->arch.guest_ebase); |
385 | kfree(vcpu->arch.kseg0_commpage); | |
8c9eb041 | 386 | kfree(vcpu); |
669e846e SL |
387 | } |
388 | ||
389 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) | |
390 | { | |
391 | kvm_arch_vcpu_free(vcpu); | |
392 | } | |
393 | ||
d116e812 DCZ |
394 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
395 | struct kvm_guest_debug *dbg) | |
669e846e | 396 | { |
ed829857 | 397 | return -ENOIOCTLCMD; |
669e846e SL |
398 | } |
399 | ||
400 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) | |
401 | { | |
460df4c1 | 402 | int r = -EINTR; |
669e846e SL |
403 | sigset_t sigsaved; |
404 | ||
405 | if (vcpu->sigset_active) | |
406 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
407 | ||
408 | if (vcpu->mmio_needed) { | |
409 | if (!vcpu->mmio_is_write) | |
410 | kvm_mips_complete_mmio_load(vcpu, run); | |
411 | vcpu->mmio_needed = 0; | |
412 | } | |
413 | ||
460df4c1 PB |
414 | if (run->immediate_exit) |
415 | goto out; | |
416 | ||
f798217d JH |
417 | lose_fpu(1); |
418 | ||
044f0f03 | 419 | local_irq_disable(); |
6edaa530 | 420 | guest_enter_irqoff(); |
93258604 | 421 | trace_kvm_enter(vcpu); |
25b08c7f | 422 | |
4841e0dd JH |
423 | /* |
424 | * Make sure the read of VCPU requests in vcpu_run() callback is not | |
425 | * reordered ahead of the write to vcpu->mode, or we could miss a TLB | |
426 | * flush request while the requester sees the VCPU as outside of guest | |
427 | * mode and not needing an IPI. | |
428 | */ | |
429 | smp_store_mb(vcpu->mode, IN_GUEST_MODE); | |
430 | ||
a2c046e4 | 431 | r = kvm_mips_callbacks->vcpu_run(run, vcpu); |
25b08c7f | 432 | |
93258604 | 433 | trace_kvm_out(vcpu); |
6edaa530 | 434 | guest_exit_irqoff(); |
669e846e SL |
435 | local_irq_enable(); |
436 | ||
460df4c1 | 437 | out: |
669e846e SL |
438 | if (vcpu->sigset_active) |
439 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
440 | ||
441 | return r; | |
442 | } | |
443 | ||
d116e812 DCZ |
444 | int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
445 | struct kvm_mips_interrupt *irq) | |
669e846e SL |
446 | { |
447 | int intr = (int)irq->irq; | |
448 | struct kvm_vcpu *dvcpu = NULL; | |
449 | ||
450 | if (intr == 3 || intr == -3 || intr == 4 || intr == -4) | |
451 | kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu, | |
452 | (int)intr); | |
453 | ||
454 | if (irq->cpu == -1) | |
455 | dvcpu = vcpu; | |
456 | else | |
457 | dvcpu = vcpu->kvm->vcpus[irq->cpu]; | |
458 | ||
459 | if (intr == 2 || intr == 3 || intr == 4) { | |
460 | kvm_mips_callbacks->queue_io_int(dvcpu, irq); | |
461 | ||
462 | } else if (intr == -2 || intr == -3 || intr == -4) { | |
463 | kvm_mips_callbacks->dequeue_io_int(dvcpu, irq); | |
464 | } else { | |
465 | kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__, | |
466 | irq->cpu, irq->irq); | |
467 | return -EINVAL; | |
468 | } | |
469 | ||
470 | dvcpu->arch.wait = 0; | |
471 | ||
8577370f MT |
472 | if (swait_active(&dvcpu->wq)) |
473 | swake_up(&dvcpu->wq); | |
669e846e SL |
474 | |
475 | return 0; | |
476 | } | |
477 | ||
d116e812 DCZ |
478 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
479 | struct kvm_mp_state *mp_state) | |
669e846e | 480 | { |
ed829857 | 481 | return -ENOIOCTLCMD; |
669e846e SL |
482 | } |
483 | ||
d116e812 DCZ |
484 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, |
485 | struct kvm_mp_state *mp_state) | |
669e846e | 486 | { |
ed829857 | 487 | return -ENOIOCTLCMD; |
669e846e SL |
488 | } |
489 | ||
4c73fb2b DD |
490 | static u64 kvm_mips_get_one_regs[] = { |
491 | KVM_REG_MIPS_R0, | |
492 | KVM_REG_MIPS_R1, | |
493 | KVM_REG_MIPS_R2, | |
494 | KVM_REG_MIPS_R3, | |
495 | KVM_REG_MIPS_R4, | |
496 | KVM_REG_MIPS_R5, | |
497 | KVM_REG_MIPS_R6, | |
498 | KVM_REG_MIPS_R7, | |
499 | KVM_REG_MIPS_R8, | |
500 | KVM_REG_MIPS_R9, | |
501 | KVM_REG_MIPS_R10, | |
502 | KVM_REG_MIPS_R11, | |
503 | KVM_REG_MIPS_R12, | |
504 | KVM_REG_MIPS_R13, | |
505 | KVM_REG_MIPS_R14, | |
506 | KVM_REG_MIPS_R15, | |
507 | KVM_REG_MIPS_R16, | |
508 | KVM_REG_MIPS_R17, | |
509 | KVM_REG_MIPS_R18, | |
510 | KVM_REG_MIPS_R19, | |
511 | KVM_REG_MIPS_R20, | |
512 | KVM_REG_MIPS_R21, | |
513 | KVM_REG_MIPS_R22, | |
514 | KVM_REG_MIPS_R23, | |
515 | KVM_REG_MIPS_R24, | |
516 | KVM_REG_MIPS_R25, | |
517 | KVM_REG_MIPS_R26, | |
518 | KVM_REG_MIPS_R27, | |
519 | KVM_REG_MIPS_R28, | |
520 | KVM_REG_MIPS_R29, | |
521 | KVM_REG_MIPS_R30, | |
522 | KVM_REG_MIPS_R31, | |
523 | ||
70e92c7e | 524 | #ifndef CONFIG_CPU_MIPSR6 |
4c73fb2b DD |
525 | KVM_REG_MIPS_HI, |
526 | KVM_REG_MIPS_LO, | |
70e92c7e | 527 | #endif |
4c73fb2b | 528 | KVM_REG_MIPS_PC, |
4c73fb2b DD |
529 | }; |
530 | ||
e5775930 JH |
531 | static u64 kvm_mips_get_one_regs_fpu[] = { |
532 | KVM_REG_MIPS_FCR_IR, | |
533 | KVM_REG_MIPS_FCR_CSR, | |
534 | }; | |
535 | ||
536 | static u64 kvm_mips_get_one_regs_msa[] = { | |
537 | KVM_REG_MIPS_MSA_IR, | |
538 | KVM_REG_MIPS_MSA_CSR, | |
539 | }; | |
540 | ||
f5c43bd4 JH |
541 | static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu) |
542 | { | |
543 | unsigned long ret; | |
544 | ||
545 | ret = ARRAY_SIZE(kvm_mips_get_one_regs); | |
e5775930 JH |
546 | if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { |
547 | ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48; | |
548 | /* odd doubles */ | |
549 | if (boot_cpu_data.fpu_id & MIPS_FPIR_F64) | |
550 | ret += 16; | |
551 | } | |
552 | if (kvm_mips_guest_can_have_msa(&vcpu->arch)) | |
553 | ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32; | |
f5c43bd4 JH |
554 | ret += kvm_mips_callbacks->num_regs(vcpu); |
555 | ||
556 | return ret; | |
557 | } | |
558 | ||
559 | static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) | |
560 | { | |
e5775930 JH |
561 | u64 index; |
562 | unsigned int i; | |
563 | ||
f5c43bd4 JH |
564 | if (copy_to_user(indices, kvm_mips_get_one_regs, |
565 | sizeof(kvm_mips_get_one_regs))) | |
566 | return -EFAULT; | |
567 | indices += ARRAY_SIZE(kvm_mips_get_one_regs); | |
568 | ||
e5775930 JH |
569 | if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { |
570 | if (copy_to_user(indices, kvm_mips_get_one_regs_fpu, | |
571 | sizeof(kvm_mips_get_one_regs_fpu))) | |
572 | return -EFAULT; | |
573 | indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu); | |
574 | ||
575 | for (i = 0; i < 32; ++i) { | |
576 | index = KVM_REG_MIPS_FPR_32(i); | |
577 | if (copy_to_user(indices, &index, sizeof(index))) | |
578 | return -EFAULT; | |
579 | ++indices; | |
580 | ||
581 | /* skip odd doubles if no F64 */ | |
582 | if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64)) | |
583 | continue; | |
584 | ||
585 | index = KVM_REG_MIPS_FPR_64(i); | |
586 | if (copy_to_user(indices, &index, sizeof(index))) | |
587 | return -EFAULT; | |
588 | ++indices; | |
589 | } | |
590 | } | |
591 | ||
592 | if (kvm_mips_guest_can_have_msa(&vcpu->arch)) { | |
593 | if (copy_to_user(indices, kvm_mips_get_one_regs_msa, | |
594 | sizeof(kvm_mips_get_one_regs_msa))) | |
595 | return -EFAULT; | |
596 | indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa); | |
597 | ||
598 | for (i = 0; i < 32; ++i) { | |
599 | index = KVM_REG_MIPS_VEC_128(i); | |
600 | if (copy_to_user(indices, &index, sizeof(index))) | |
601 | return -EFAULT; | |
602 | ++indices; | |
603 | } | |
604 | } | |
605 | ||
f5c43bd4 JH |
606 | return kvm_mips_callbacks->copy_reg_indices(vcpu, indices); |
607 | } | |
608 | ||
4c73fb2b DD |
609 | static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, |
610 | const struct kvm_one_reg *reg) | |
611 | { | |
4c73fb2b | 612 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
379245cd | 613 | struct mips_fpu_struct *fpu = &vcpu->arch.fpu; |
f8be02da | 614 | int ret; |
4c73fb2b | 615 | s64 v; |
ab86bd60 | 616 | s64 vs[2]; |
379245cd | 617 | unsigned int idx; |
4c73fb2b DD |
618 | |
619 | switch (reg->id) { | |
379245cd | 620 | /* General purpose registers */ |
4c73fb2b DD |
621 | case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31: |
622 | v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0]; | |
623 | break; | |
70e92c7e | 624 | #ifndef CONFIG_CPU_MIPSR6 |
4c73fb2b DD |
625 | case KVM_REG_MIPS_HI: |
626 | v = (long)vcpu->arch.hi; | |
627 | break; | |
628 | case KVM_REG_MIPS_LO: | |
629 | v = (long)vcpu->arch.lo; | |
630 | break; | |
70e92c7e | 631 | #endif |
4c73fb2b DD |
632 | case KVM_REG_MIPS_PC: |
633 | v = (long)vcpu->arch.pc; | |
634 | break; | |
635 | ||
379245cd JH |
636 | /* Floating point registers */ |
637 | case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): | |
638 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
639 | return -EINVAL; | |
640 | idx = reg->id - KVM_REG_MIPS_FPR_32(0); | |
641 | /* Odd singles in top of even double when FR=0 */ | |
642 | if (kvm_read_c0_guest_status(cop0) & ST0_FR) | |
643 | v = get_fpr32(&fpu->fpr[idx], 0); | |
644 | else | |
645 | v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1); | |
646 | break; | |
647 | case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): | |
648 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
649 | return -EINVAL; | |
650 | idx = reg->id - KVM_REG_MIPS_FPR_64(0); | |
651 | /* Can't access odd doubles in FR=0 mode */ | |
652 | if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) | |
653 | return -EINVAL; | |
654 | v = get_fpr64(&fpu->fpr[idx], 0); | |
655 | break; | |
656 | case KVM_REG_MIPS_FCR_IR: | |
657 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
658 | return -EINVAL; | |
659 | v = boot_cpu_data.fpu_id; | |
660 | break; | |
661 | case KVM_REG_MIPS_FCR_CSR: | |
662 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
663 | return -EINVAL; | |
664 | v = fpu->fcr31; | |
665 | break; | |
666 | ||
ab86bd60 JH |
667 | /* MIPS SIMD Architecture (MSA) registers */ |
668 | case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): | |
669 | if (!kvm_mips_guest_has_msa(&vcpu->arch)) | |
670 | return -EINVAL; | |
671 | /* Can't access MSA registers in FR=0 mode */ | |
672 | if (!(kvm_read_c0_guest_status(cop0) & ST0_FR)) | |
673 | return -EINVAL; | |
674 | idx = reg->id - KVM_REG_MIPS_VEC_128(0); | |
675 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
676 | /* least significant byte first */ | |
677 | vs[0] = get_fpr64(&fpu->fpr[idx], 0); | |
678 | vs[1] = get_fpr64(&fpu->fpr[idx], 1); | |
679 | #else | |
680 | /* most significant byte first */ | |
681 | vs[0] = get_fpr64(&fpu->fpr[idx], 1); | |
682 | vs[1] = get_fpr64(&fpu->fpr[idx], 0); | |
683 | #endif | |
684 | break; | |
685 | case KVM_REG_MIPS_MSA_IR: | |
686 | if (!kvm_mips_guest_has_msa(&vcpu->arch)) | |
687 | return -EINVAL; | |
688 | v = boot_cpu_data.msa_id; | |
689 | break; | |
690 | case KVM_REG_MIPS_MSA_CSR: | |
691 | if (!kvm_mips_guest_has_msa(&vcpu->arch)) | |
692 | return -EINVAL; | |
693 | v = fpu->msacsr; | |
694 | break; | |
695 | ||
f8be02da | 696 | /* registers to be handled specially */ |
cc68d22f | 697 | default: |
f8be02da JH |
698 | ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v); |
699 | if (ret) | |
700 | return ret; | |
701 | break; | |
4c73fb2b | 702 | } |
681865d4 DD |
703 | if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { |
704 | u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; | |
d116e812 | 705 | |
681865d4 DD |
706 | return put_user(v, uaddr64); |
707 | } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { | |
708 | u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; | |
709 | u32 v32 = (u32)v; | |
d116e812 | 710 | |
681865d4 | 711 | return put_user(v32, uaddr32); |
ab86bd60 JH |
712 | } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { |
713 | void __user *uaddr = (void __user *)(long)reg->addr; | |
714 | ||
0178fd7d | 715 | return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0; |
681865d4 DD |
716 | } else { |
717 | return -EINVAL; | |
718 | } | |
4c73fb2b DD |
719 | } |
720 | ||
721 | static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, | |
722 | const struct kvm_one_reg *reg) | |
723 | { | |
4c73fb2b | 724 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
379245cd JH |
725 | struct mips_fpu_struct *fpu = &vcpu->arch.fpu; |
726 | s64 v; | |
ab86bd60 | 727 | s64 vs[2]; |
379245cd | 728 | unsigned int idx; |
4c73fb2b | 729 | |
681865d4 DD |
730 | if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { |
731 | u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; | |
732 | ||
733 | if (get_user(v, uaddr64) != 0) | |
734 | return -EFAULT; | |
735 | } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { | |
736 | u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; | |
737 | s32 v32; | |
738 | ||
739 | if (get_user(v32, uaddr32) != 0) | |
740 | return -EFAULT; | |
741 | v = (s64)v32; | |
ab86bd60 JH |
742 | } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { |
743 | void __user *uaddr = (void __user *)(long)reg->addr; | |
744 | ||
0178fd7d | 745 | return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0; |
681865d4 DD |
746 | } else { |
747 | return -EINVAL; | |
748 | } | |
4c73fb2b DD |
749 | |
750 | switch (reg->id) { | |
379245cd | 751 | /* General purpose registers */ |
4c73fb2b DD |
752 | case KVM_REG_MIPS_R0: |
753 | /* Silently ignore requests to set $0 */ | |
754 | break; | |
755 | case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31: | |
756 | vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v; | |
757 | break; | |
70e92c7e | 758 | #ifndef CONFIG_CPU_MIPSR6 |
4c73fb2b DD |
759 | case KVM_REG_MIPS_HI: |
760 | vcpu->arch.hi = v; | |
761 | break; | |
762 | case KVM_REG_MIPS_LO: | |
763 | vcpu->arch.lo = v; | |
764 | break; | |
70e92c7e | 765 | #endif |
4c73fb2b DD |
766 | case KVM_REG_MIPS_PC: |
767 | vcpu->arch.pc = v; | |
768 | break; | |
769 | ||
379245cd JH |
770 | /* Floating point registers */ |
771 | case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): | |
772 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
773 | return -EINVAL; | |
774 | idx = reg->id - KVM_REG_MIPS_FPR_32(0); | |
775 | /* Odd singles in top of even double when FR=0 */ | |
776 | if (kvm_read_c0_guest_status(cop0) & ST0_FR) | |
777 | set_fpr32(&fpu->fpr[idx], 0, v); | |
778 | else | |
779 | set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v); | |
780 | break; | |
781 | case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): | |
782 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
783 | return -EINVAL; | |
784 | idx = reg->id - KVM_REG_MIPS_FPR_64(0); | |
785 | /* Can't access odd doubles in FR=0 mode */ | |
786 | if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) | |
787 | return -EINVAL; | |
788 | set_fpr64(&fpu->fpr[idx], 0, v); | |
789 | break; | |
790 | case KVM_REG_MIPS_FCR_IR: | |
791 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
792 | return -EINVAL; | |
793 | /* Read-only */ | |
794 | break; | |
795 | case KVM_REG_MIPS_FCR_CSR: | |
796 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
797 | return -EINVAL; | |
798 | fpu->fcr31 = v; | |
799 | break; | |
800 | ||
ab86bd60 JH |
801 | /* MIPS SIMD Architecture (MSA) registers */ |
802 | case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): | |
803 | if (!kvm_mips_guest_has_msa(&vcpu->arch)) | |
804 | return -EINVAL; | |
805 | idx = reg->id - KVM_REG_MIPS_VEC_128(0); | |
806 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
807 | /* least significant byte first */ | |
808 | set_fpr64(&fpu->fpr[idx], 0, vs[0]); | |
809 | set_fpr64(&fpu->fpr[idx], 1, vs[1]); | |
810 | #else | |
811 | /* most significant byte first */ | |
812 | set_fpr64(&fpu->fpr[idx], 1, vs[0]); | |
813 | set_fpr64(&fpu->fpr[idx], 0, vs[1]); | |
814 | #endif | |
815 | break; | |
816 | case KVM_REG_MIPS_MSA_IR: | |
817 | if (!kvm_mips_guest_has_msa(&vcpu->arch)) | |
818 | return -EINVAL; | |
819 | /* Read-only */ | |
820 | break; | |
821 | case KVM_REG_MIPS_MSA_CSR: | |
822 | if (!kvm_mips_guest_has_msa(&vcpu->arch)) | |
823 | return -EINVAL; | |
824 | fpu->msacsr = v; | |
825 | break; | |
826 | ||
f8be02da | 827 | /* registers to be handled specially */ |
4c73fb2b | 828 | default: |
cc68d22f | 829 | return kvm_mips_callbacks->set_one_reg(vcpu, reg, v); |
4c73fb2b DD |
830 | } |
831 | return 0; | |
832 | } | |
833 | ||
5fafd874 JH |
834 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
835 | struct kvm_enable_cap *cap) | |
836 | { | |
837 | int r = 0; | |
838 | ||
839 | if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap)) | |
840 | return -EINVAL; | |
841 | if (cap->flags) | |
842 | return -EINVAL; | |
843 | if (cap->args[0]) | |
844 | return -EINVAL; | |
845 | ||
846 | switch (cap->cap) { | |
847 | case KVM_CAP_MIPS_FPU: | |
848 | vcpu->arch.fpu_enabled = true; | |
849 | break; | |
d952bd07 JH |
850 | case KVM_CAP_MIPS_MSA: |
851 | vcpu->arch.msa_enabled = true; | |
852 | break; | |
5fafd874 JH |
853 | default: |
854 | r = -EINVAL; | |
855 | break; | |
856 | } | |
857 | ||
858 | return r; | |
859 | } | |
860 | ||
d116e812 DCZ |
861 | long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, |
862 | unsigned long arg) | |
669e846e SL |
863 | { |
864 | struct kvm_vcpu *vcpu = filp->private_data; | |
865 | void __user *argp = (void __user *)arg; | |
866 | long r; | |
669e846e SL |
867 | |
868 | switch (ioctl) { | |
4c73fb2b DD |
869 | case KVM_SET_ONE_REG: |
870 | case KVM_GET_ONE_REG: { | |
871 | struct kvm_one_reg reg; | |
d116e812 | 872 | |
4c73fb2b DD |
873 | if (copy_from_user(®, argp, sizeof(reg))) |
874 | return -EFAULT; | |
875 | if (ioctl == KVM_SET_ONE_REG) | |
876 | return kvm_mips_set_reg(vcpu, ®); | |
877 | else | |
878 | return kvm_mips_get_reg(vcpu, ®); | |
879 | } | |
880 | case KVM_GET_REG_LIST: { | |
881 | struct kvm_reg_list __user *user_list = argp; | |
4c73fb2b DD |
882 | struct kvm_reg_list reg_list; |
883 | unsigned n; | |
884 | ||
885 | if (copy_from_user(®_list, user_list, sizeof(reg_list))) | |
886 | return -EFAULT; | |
887 | n = reg_list.n; | |
f5c43bd4 | 888 | reg_list.n = kvm_mips_num_regs(vcpu); |
4c73fb2b DD |
889 | if (copy_to_user(user_list, ®_list, sizeof(reg_list))) |
890 | return -EFAULT; | |
891 | if (n < reg_list.n) | |
892 | return -E2BIG; | |
f5c43bd4 | 893 | return kvm_mips_copy_reg_indices(vcpu, user_list->reg); |
4c73fb2b | 894 | } |
669e846e SL |
895 | case KVM_INTERRUPT: |
896 | { | |
897 | struct kvm_mips_interrupt irq; | |
d116e812 | 898 | |
669e846e | 899 | if (copy_from_user(&irq, argp, sizeof(irq))) |
5a6da5f7 | 900 | return -EFAULT; |
669e846e SL |
901 | kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, |
902 | irq.irq); | |
903 | ||
904 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
905 | break; | |
906 | } | |
5fafd874 JH |
907 | case KVM_ENABLE_CAP: { |
908 | struct kvm_enable_cap cap; | |
909 | ||
5fafd874 | 910 | if (copy_from_user(&cap, argp, sizeof(cap))) |
5a6da5f7 | 911 | return -EFAULT; |
5fafd874 JH |
912 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); |
913 | break; | |
914 | } | |
669e846e | 915 | default: |
4c73fb2b | 916 | r = -ENOIOCTLCMD; |
669e846e | 917 | } |
669e846e SL |
918 | return r; |
919 | } | |
920 | ||
e88643ba JH |
921 | /** |
922 | * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot | |
923 | * @kvm: kvm instance | |
924 | * @log: slot id and address to which we copy the log | |
925 | * | |
926 | * Steps 1-4 below provide general overview of dirty page logging. See | |
927 | * kvm_get_dirty_log_protect() function description for additional details. | |
928 | * | |
929 | * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we | |
930 | * always flush the TLB (step 4) even if previous step failed and the dirty | |
931 | * bitmap may be corrupt. Regardless of previous outcome the KVM logging API | |
932 | * does not preclude user space subsequent dirty log read. Flushing TLB ensures | |
933 | * writes will be marked dirty for next log read. | |
934 | * | |
935 | * 1. Take a snapshot of the bit and clear it if needed. | |
936 | * 2. Write protect the corresponding page. | |
937 | * 3. Copy the snapshot to the userspace. | |
938 | * 4. Flush TLB's if needed. | |
939 | */ | |
669e846e SL |
940 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
941 | { | |
9f6b8029 | 942 | struct kvm_memslots *slots; |
669e846e | 943 | struct kvm_memory_slot *memslot; |
e88643ba | 944 | bool is_dirty = false; |
669e846e | 945 | int r; |
669e846e SL |
946 | |
947 | mutex_lock(&kvm->slots_lock); | |
948 | ||
e88643ba | 949 | r = kvm_get_dirty_log_protect(kvm, log, &is_dirty); |
669e846e | 950 | |
669e846e | 951 | if (is_dirty) { |
9f6b8029 PB |
952 | slots = kvm_memslots(kvm); |
953 | memslot = id_to_memslot(slots, log->slot); | |
669e846e | 954 | |
e88643ba JH |
955 | /* Let implementation handle TLB/GVA invalidation */ |
956 | kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot); | |
669e846e SL |
957 | } |
958 | ||
669e846e SL |
959 | mutex_unlock(&kvm->slots_lock); |
960 | return r; | |
669e846e SL |
961 | } |
962 | ||
963 | long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) | |
964 | { | |
965 | long r; | |
966 | ||
967 | switch (ioctl) { | |
968 | default: | |
ed829857 | 969 | r = -ENOIOCTLCMD; |
669e846e SL |
970 | } |
971 | ||
972 | return r; | |
973 | } | |
974 | ||
975 | int kvm_arch_init(void *opaque) | |
976 | { | |
669e846e SL |
977 | if (kvm_mips_callbacks) { |
978 | kvm_err("kvm: module already exists\n"); | |
979 | return -EEXIST; | |
980 | } | |
981 | ||
d98403a5 | 982 | return kvm_mips_emulation_init(&kvm_mips_callbacks); |
669e846e SL |
983 | } |
984 | ||
985 | void kvm_arch_exit(void) | |
986 | { | |
987 | kvm_mips_callbacks = NULL; | |
988 | } | |
989 | ||
d116e812 DCZ |
990 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
991 | struct kvm_sregs *sregs) | |
669e846e | 992 | { |
ed829857 | 993 | return -ENOIOCTLCMD; |
669e846e SL |
994 | } |
995 | ||
d116e812 DCZ |
996 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
997 | struct kvm_sregs *sregs) | |
669e846e | 998 | { |
ed829857 | 999 | return -ENOIOCTLCMD; |
669e846e SL |
1000 | } |
1001 | ||
31928aa5 | 1002 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
669e846e | 1003 | { |
669e846e SL |
1004 | } |
1005 | ||
1006 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
1007 | { | |
ed829857 | 1008 | return -ENOIOCTLCMD; |
669e846e SL |
1009 | } |
1010 | ||
1011 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
1012 | { | |
ed829857 | 1013 | return -ENOIOCTLCMD; |
669e846e SL |
1014 | } |
1015 | ||
1016 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) | |
1017 | { | |
1018 | return VM_FAULT_SIGBUS; | |
1019 | } | |
1020 | ||
784aa3d7 | 1021 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
669e846e SL |
1022 | { |
1023 | int r; | |
1024 | ||
1025 | switch (ext) { | |
4c73fb2b | 1026 | case KVM_CAP_ONE_REG: |
5fafd874 | 1027 | case KVM_CAP_ENABLE_CAP: |
230c5724 | 1028 | case KVM_CAP_READONLY_MEM: |
411740f5 | 1029 | case KVM_CAP_SYNC_MMU: |
460df4c1 | 1030 | case KVM_CAP_IMMEDIATE_EXIT: |
4c73fb2b DD |
1031 | r = 1; |
1032 | break; | |
669e846e SL |
1033 | case KVM_CAP_COALESCED_MMIO: |
1034 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
1035 | break; | |
12ed1fae JH |
1036 | case KVM_CAP_NR_VCPUS: |
1037 | r = num_online_cpus(); | |
1038 | break; | |
1039 | case KVM_CAP_MAX_VCPUS: | |
1040 | r = KVM_MAX_VCPUS; | |
1041 | break; | |
5fafd874 | 1042 | case KVM_CAP_MIPS_FPU: |
556f2a52 JH |
1043 | /* We don't handle systems with inconsistent cpu_has_fpu */ |
1044 | r = !!raw_cpu_has_fpu; | |
5fafd874 | 1045 | break; |
d952bd07 JH |
1046 | case KVM_CAP_MIPS_MSA: |
1047 | /* | |
1048 | * We don't support MSA vector partitioning yet: | |
1049 | * 1) It would require explicit support which can't be tested | |
1050 | * yet due to lack of support in current hardware. | |
1051 | * 2) It extends the state that would need to be saved/restored | |
1052 | * by e.g. QEMU for migration. | |
1053 | * | |
1054 | * When vector partitioning hardware becomes available, support | |
1055 | * could be added by requiring a flag when enabling | |
1056 | * KVM_CAP_MIPS_MSA capability to indicate that userland knows | |
1057 | * to save/restore the appropriate extra state. | |
1058 | */ | |
1059 | r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF); | |
1060 | break; | |
669e846e SL |
1061 | default: |
1062 | r = 0; | |
1063 | break; | |
1064 | } | |
1065 | return r; | |
669e846e SL |
1066 | } |
1067 | ||
1068 | int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) | |
1069 | { | |
1070 | return kvm_mips_pending_timer(vcpu); | |
1071 | } | |
1072 | ||
1073 | int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu) | |
1074 | { | |
1075 | int i; | |
1076 | struct mips_coproc *cop0; | |
1077 | ||
1078 | if (!vcpu) | |
1079 | return -1; | |
1080 | ||
6ad78a5c DCZ |
1081 | kvm_debug("VCPU Register Dump:\n"); |
1082 | kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc); | |
1083 | kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions); | |
669e846e SL |
1084 | |
1085 | for (i = 0; i < 32; i += 4) { | |
6ad78a5c | 1086 | kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i, |
669e846e SL |
1087 | vcpu->arch.gprs[i], |
1088 | vcpu->arch.gprs[i + 1], | |
1089 | vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]); | |
1090 | } | |
6ad78a5c DCZ |
1091 | kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi); |
1092 | kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo); | |
669e846e SL |
1093 | |
1094 | cop0 = vcpu->arch.cop0; | |
6ad78a5c DCZ |
1095 | kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n", |
1096 | kvm_read_c0_guest_status(cop0), | |
1097 | kvm_read_c0_guest_cause(cop0)); | |
669e846e | 1098 | |
6ad78a5c | 1099 | kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0)); |
669e846e SL |
1100 | |
1101 | return 0; | |
1102 | } | |
1103 | ||
1104 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
1105 | { | |
1106 | int i; | |
1107 | ||
8d17dd04 | 1108 | for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) |
bf32ebf6 | 1109 | vcpu->arch.gprs[i] = regs->gpr[i]; |
8d17dd04 | 1110 | vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ |
669e846e SL |
1111 | vcpu->arch.hi = regs->hi; |
1112 | vcpu->arch.lo = regs->lo; | |
1113 | vcpu->arch.pc = regs->pc; | |
1114 | ||
4c73fb2b | 1115 | return 0; |
669e846e SL |
1116 | } |
1117 | ||
1118 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
1119 | { | |
1120 | int i; | |
1121 | ||
8d17dd04 | 1122 | for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) |
bf32ebf6 | 1123 | regs->gpr[i] = vcpu->arch.gprs[i]; |
669e846e SL |
1124 | |
1125 | regs->hi = vcpu->arch.hi; | |
1126 | regs->lo = vcpu->arch.lo; | |
1127 | regs->pc = vcpu->arch.pc; | |
1128 | ||
4c73fb2b | 1129 | return 0; |
669e846e SL |
1130 | } |
1131 | ||
0fae34f4 | 1132 | static void kvm_mips_comparecount_func(unsigned long data) |
669e846e SL |
1133 | { |
1134 | struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data; | |
1135 | ||
1136 | kvm_mips_callbacks->queue_timer_int(vcpu); | |
1137 | ||
1138 | vcpu->arch.wait = 0; | |
8577370f MT |
1139 | if (swait_active(&vcpu->wq)) |
1140 | swake_up(&vcpu->wq); | |
669e846e SL |
1141 | } |
1142 | ||
d116e812 | 1143 | /* low level hrtimer wake routine */ |
0fae34f4 | 1144 | static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer) |
669e846e SL |
1145 | { |
1146 | struct kvm_vcpu *vcpu; | |
1147 | ||
1148 | vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer); | |
1149 | kvm_mips_comparecount_func((unsigned long) vcpu); | |
e30492bb | 1150 | return kvm_mips_count_timeout(vcpu); |
669e846e SL |
1151 | } |
1152 | ||
1153 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) | |
1154 | { | |
f7f1427d JH |
1155 | int err; |
1156 | ||
1157 | err = kvm_mips_callbacks->vcpu_init(vcpu); | |
1158 | if (err) | |
1159 | return err; | |
1160 | ||
669e846e SL |
1161 | hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, |
1162 | HRTIMER_MODE_REL); | |
1163 | vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; | |
669e846e SL |
1164 | return 0; |
1165 | } | |
1166 | ||
630766b3 JH |
1167 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) |
1168 | { | |
1169 | kvm_mips_callbacks->vcpu_uninit(vcpu); | |
1170 | } | |
1171 | ||
d116e812 DCZ |
1172 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, |
1173 | struct kvm_translation *tr) | |
669e846e SL |
1174 | { |
1175 | return 0; | |
1176 | } | |
1177 | ||
1178 | /* Initial guest state */ | |
1179 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) | |
1180 | { | |
1181 | return kvm_mips_callbacks->vcpu_setup(vcpu); | |
1182 | } | |
1183 | ||
d116e812 | 1184 | static void kvm_mips_set_c0_status(void) |
669e846e | 1185 | { |
8cffd197 | 1186 | u32 status = read_c0_status(); |
669e846e | 1187 | |
669e846e SL |
1188 | if (cpu_has_dsp) |
1189 | status |= (ST0_MX); | |
1190 | ||
1191 | write_c0_status(status); | |
1192 | ehb(); | |
1193 | } | |
1194 | ||
1195 | /* | |
1196 | * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) | |
1197 | */ | |
1198 | int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu) | |
1199 | { | |
8cffd197 JH |
1200 | u32 cause = vcpu->arch.host_cp0_cause; |
1201 | u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; | |
1202 | u32 __user *opc = (u32 __user *) vcpu->arch.pc; | |
669e846e SL |
1203 | unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; |
1204 | enum emulation_result er = EMULATE_DONE; | |
122e51d4 | 1205 | u32 inst; |
669e846e SL |
1206 | int ret = RESUME_GUEST; |
1207 | ||
4841e0dd JH |
1208 | vcpu->mode = OUTSIDE_GUEST_MODE; |
1209 | ||
c4c6f2ca JH |
1210 | /* re-enable HTW before enabling interrupts */ |
1211 | htw_start(); | |
1212 | ||
669e846e SL |
1213 | /* Set a default exit reason */ |
1214 | run->exit_reason = KVM_EXIT_UNKNOWN; | |
1215 | run->ready_for_interrupt_injection = 1; | |
1216 | ||
d116e812 DCZ |
1217 | /* |
1218 | * Set the appropriate status bits based on host CPU features, | |
1219 | * before we hit the scheduler | |
1220 | */ | |
669e846e SL |
1221 | kvm_mips_set_c0_status(); |
1222 | ||
1223 | local_irq_enable(); | |
1224 | ||
1225 | kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n", | |
1226 | cause, opc, run, vcpu); | |
1e09e86a | 1227 | trace_kvm_exit(vcpu, exccode); |
669e846e | 1228 | |
d116e812 DCZ |
1229 | /* |
1230 | * Do a privilege check, if in UM most of these exit conditions end up | |
669e846e SL |
1231 | * causing an exception to be delivered to the Guest Kernel |
1232 | */ | |
1233 | er = kvm_mips_check_privilege(cause, opc, run, vcpu); | |
1234 | if (er == EMULATE_PRIV_FAIL) { | |
1235 | goto skip_emul; | |
1236 | } else if (er == EMULATE_FAIL) { | |
1237 | run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
1238 | ret = RESUME_HOST; | |
1239 | goto skip_emul; | |
1240 | } | |
1241 | ||
1242 | switch (exccode) { | |
16d100db JH |
1243 | case EXCCODE_INT: |
1244 | kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc); | |
669e846e SL |
1245 | |
1246 | ++vcpu->stat.int_exits; | |
669e846e | 1247 | |
d116e812 | 1248 | if (need_resched()) |
669e846e | 1249 | cond_resched(); |
669e846e SL |
1250 | |
1251 | ret = RESUME_GUEST; | |
1252 | break; | |
1253 | ||
16d100db JH |
1254 | case EXCCODE_CPU: |
1255 | kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc); | |
669e846e SL |
1256 | |
1257 | ++vcpu->stat.cop_unusable_exits; | |
669e846e SL |
1258 | ret = kvm_mips_callbacks->handle_cop_unusable(vcpu); |
1259 | /* XXXKYMA: Might need to return to user space */ | |
d116e812 | 1260 | if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN) |
669e846e | 1261 | ret = RESUME_HOST; |
669e846e SL |
1262 | break; |
1263 | ||
16d100db | 1264 | case EXCCODE_MOD: |
669e846e | 1265 | ++vcpu->stat.tlbmod_exits; |
669e846e SL |
1266 | ret = kvm_mips_callbacks->handle_tlb_mod(vcpu); |
1267 | break; | |
1268 | ||
16d100db | 1269 | case EXCCODE_TLBS: |
d116e812 DCZ |
1270 | kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n", |
1271 | cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc, | |
1272 | badvaddr); | |
669e846e SL |
1273 | |
1274 | ++vcpu->stat.tlbmiss_st_exits; | |
669e846e SL |
1275 | ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu); |
1276 | break; | |
1277 | ||
16d100db | 1278 | case EXCCODE_TLBL: |
669e846e SL |
1279 | kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n", |
1280 | cause, opc, badvaddr); | |
1281 | ||
1282 | ++vcpu->stat.tlbmiss_ld_exits; | |
669e846e SL |
1283 | ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu); |
1284 | break; | |
1285 | ||
16d100db | 1286 | case EXCCODE_ADES: |
669e846e | 1287 | ++vcpu->stat.addrerr_st_exits; |
669e846e SL |
1288 | ret = kvm_mips_callbacks->handle_addr_err_st(vcpu); |
1289 | break; | |
1290 | ||
16d100db | 1291 | case EXCCODE_ADEL: |
669e846e | 1292 | ++vcpu->stat.addrerr_ld_exits; |
669e846e SL |
1293 | ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu); |
1294 | break; | |
1295 | ||
16d100db | 1296 | case EXCCODE_SYS: |
669e846e | 1297 | ++vcpu->stat.syscall_exits; |
669e846e SL |
1298 | ret = kvm_mips_callbacks->handle_syscall(vcpu); |
1299 | break; | |
1300 | ||
16d100db | 1301 | case EXCCODE_RI: |
669e846e | 1302 | ++vcpu->stat.resvd_inst_exits; |
669e846e SL |
1303 | ret = kvm_mips_callbacks->handle_res_inst(vcpu); |
1304 | break; | |
1305 | ||
16d100db | 1306 | case EXCCODE_BP: |
669e846e | 1307 | ++vcpu->stat.break_inst_exits; |
669e846e SL |
1308 | ret = kvm_mips_callbacks->handle_break(vcpu); |
1309 | break; | |
1310 | ||
16d100db | 1311 | case EXCCODE_TR: |
0a560427 | 1312 | ++vcpu->stat.trap_inst_exits; |
0a560427 JH |
1313 | ret = kvm_mips_callbacks->handle_trap(vcpu); |
1314 | break; | |
1315 | ||
16d100db | 1316 | case EXCCODE_MSAFPE: |
c2537ed9 | 1317 | ++vcpu->stat.msa_fpe_exits; |
c2537ed9 JH |
1318 | ret = kvm_mips_callbacks->handle_msa_fpe(vcpu); |
1319 | break; | |
1320 | ||
16d100db | 1321 | case EXCCODE_FPE: |
1c0cd66a | 1322 | ++vcpu->stat.fpe_exits; |
1c0cd66a JH |
1323 | ret = kvm_mips_callbacks->handle_fpe(vcpu); |
1324 | break; | |
1325 | ||
16d100db | 1326 | case EXCCODE_MSADIS: |
c2537ed9 | 1327 | ++vcpu->stat.msa_disabled_exits; |
98119ad5 JH |
1328 | ret = kvm_mips_callbacks->handle_msa_disabled(vcpu); |
1329 | break; | |
1330 | ||
669e846e | 1331 | default: |
122e51d4 JH |
1332 | if (cause & CAUSEF_BD) |
1333 | opc += 1; | |
1334 | inst = 0; | |
6a97c775 | 1335 | kvm_get_badinstr(opc, vcpu, &inst); |
d116e812 | 1336 | kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n", |
122e51d4 | 1337 | exccode, opc, inst, badvaddr, |
d116e812 | 1338 | kvm_read_c0_guest_status(vcpu->arch.cop0)); |
669e846e SL |
1339 | kvm_arch_vcpu_dump_regs(vcpu); |
1340 | run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
1341 | ret = RESUME_HOST; | |
1342 | break; | |
1343 | ||
1344 | } | |
1345 | ||
1346 | skip_emul: | |
1347 | local_irq_disable(); | |
1348 | ||
1349 | if (er == EMULATE_DONE && !(ret & RESUME_HOST)) | |
1350 | kvm_mips_deliver_interrupts(vcpu, cause); | |
1351 | ||
1352 | if (!(ret & RESUME_HOST)) { | |
d116e812 | 1353 | /* Only check for signals if not already exiting to userspace */ |
669e846e SL |
1354 | if (signal_pending(current)) { |
1355 | run->exit_reason = KVM_EXIT_INTR; | |
1356 | ret = (-EINTR << 2) | RESUME_HOST; | |
1357 | ++vcpu->stat.signal_exits; | |
1e09e86a | 1358 | trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL); |
669e846e SL |
1359 | } |
1360 | } | |
1361 | ||
98e91b84 | 1362 | if (ret == RESUME_GUEST) { |
93258604 JH |
1363 | trace_kvm_reenter(vcpu); |
1364 | ||
4841e0dd JH |
1365 | /* |
1366 | * Make sure the read of VCPU requests in vcpu_reenter() | |
1367 | * callback is not reordered ahead of the write to vcpu->mode, | |
1368 | * or we could miss a TLB flush request while the requester sees | |
1369 | * the VCPU as outside of guest mode and not needing an IPI. | |
1370 | */ | |
1371 | smp_store_mb(vcpu->mode, IN_GUEST_MODE); | |
1372 | ||
a2c046e4 | 1373 | kvm_mips_callbacks->vcpu_reenter(run, vcpu); |
25b08c7f | 1374 | |
98e91b84 | 1375 | /* |
539cb89f JH |
1376 | * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context |
1377 | * is live), restore FCR31 / MSACSR. | |
98e91b84 JH |
1378 | * |
1379 | * This should be before returning to the guest exception | |
539cb89f JH |
1380 | * vector, as it may well cause an [MSA] FP exception if there |
1381 | * are pending exception bits unmasked. (see | |
98e91b84 JH |
1382 | * kvm_mips_csr_die_notifier() for how that is handled). |
1383 | */ | |
1384 | if (kvm_mips_guest_has_fpu(&vcpu->arch) && | |
1385 | read_c0_status() & ST0_CU1) | |
1386 | __kvm_restore_fcsr(&vcpu->arch); | |
539cb89f JH |
1387 | |
1388 | if (kvm_mips_guest_has_msa(&vcpu->arch) && | |
1389 | read_c0_config5() & MIPS_CONF5_MSAEN) | |
1390 | __kvm_restore_msacsr(&vcpu->arch); | |
98e91b84 JH |
1391 | } |
1392 | ||
c4c6f2ca JH |
1393 | /* Disable HTW before returning to guest or host */ |
1394 | htw_stop(); | |
1395 | ||
669e846e SL |
1396 | return ret; |
1397 | } | |
1398 | ||
98e91b84 JH |
1399 | /* Enable FPU for guest and restore context */ |
1400 | void kvm_own_fpu(struct kvm_vcpu *vcpu) | |
1401 | { | |
1402 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1403 | unsigned int sr, cfg5; | |
1404 | ||
1405 | preempt_disable(); | |
1406 | ||
539cb89f JH |
1407 | sr = kvm_read_c0_guest_status(cop0); |
1408 | ||
1409 | /* | |
1410 | * If MSA state is already live, it is undefined how it interacts with | |
1411 | * FR=0 FPU state, and we don't want to hit reserved instruction | |
1412 | * exceptions trying to save the MSA state later when CU=1 && FR=1, so | |
1413 | * play it safe and save it first. | |
1414 | * | |
1415 | * In theory we shouldn't ever hit this case since kvm_lose_fpu() should | |
1416 | * get called when guest CU1 is set, however we can't trust the guest | |
1417 | * not to clobber the status register directly via the commpage. | |
1418 | */ | |
1419 | if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) && | |
f943176a | 1420 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) |
539cb89f JH |
1421 | kvm_lose_fpu(vcpu); |
1422 | ||
98e91b84 JH |
1423 | /* |
1424 | * Enable FPU for guest | |
1425 | * We set FR and FRE according to guest context | |
1426 | */ | |
98e91b84 JH |
1427 | change_c0_status(ST0_CU1 | ST0_FR, sr); |
1428 | if (cpu_has_fre) { | |
1429 | cfg5 = kvm_read_c0_guest_config5(cop0); | |
1430 | change_c0_config5(MIPS_CONF5_FRE, cfg5); | |
1431 | } | |
1432 | enable_fpu_hazard(); | |
1433 | ||
1434 | /* If guest FPU state not active, restore it now */ | |
f943176a | 1435 | if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) { |
98e91b84 | 1436 | __kvm_restore_fpu(&vcpu->arch); |
f943176a | 1437 | vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; |
04ebebf4 JH |
1438 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU); |
1439 | } else { | |
1440 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU); | |
98e91b84 JH |
1441 | } |
1442 | ||
1443 | preempt_enable(); | |
1444 | } | |
1445 | ||
539cb89f JH |
1446 | #ifdef CONFIG_CPU_HAS_MSA |
1447 | /* Enable MSA for guest and restore context */ | |
1448 | void kvm_own_msa(struct kvm_vcpu *vcpu) | |
1449 | { | |
1450 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1451 | unsigned int sr, cfg5; | |
1452 | ||
1453 | preempt_disable(); | |
1454 | ||
1455 | /* | |
1456 | * Enable FPU if enabled in guest, since we're restoring FPU context | |
1457 | * anyway. We set FR and FRE according to guest context. | |
1458 | */ | |
1459 | if (kvm_mips_guest_has_fpu(&vcpu->arch)) { | |
1460 | sr = kvm_read_c0_guest_status(cop0); | |
1461 | ||
1462 | /* | |
1463 | * If FR=0 FPU state is already live, it is undefined how it | |
1464 | * interacts with MSA state, so play it safe and save it first. | |
1465 | */ | |
1466 | if (!(sr & ST0_FR) && | |
f943176a JH |
1467 | (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | |
1468 | KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU) | |
539cb89f JH |
1469 | kvm_lose_fpu(vcpu); |
1470 | ||
1471 | change_c0_status(ST0_CU1 | ST0_FR, sr); | |
1472 | if (sr & ST0_CU1 && cpu_has_fre) { | |
1473 | cfg5 = kvm_read_c0_guest_config5(cop0); | |
1474 | change_c0_config5(MIPS_CONF5_FRE, cfg5); | |
1475 | } | |
1476 | } | |
1477 | ||
1478 | /* Enable MSA for guest */ | |
1479 | set_c0_config5(MIPS_CONF5_MSAEN); | |
1480 | enable_fpu_hazard(); | |
1481 | ||
f943176a JH |
1482 | switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) { |
1483 | case KVM_MIPS_AUX_FPU: | |
539cb89f JH |
1484 | /* |
1485 | * Guest FPU state already loaded, only restore upper MSA state | |
1486 | */ | |
1487 | __kvm_restore_msa_upper(&vcpu->arch); | |
f943176a | 1488 | vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; |
04ebebf4 | 1489 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA); |
539cb89f JH |
1490 | break; |
1491 | case 0: | |
1492 | /* Neither FPU or MSA already active, restore full MSA state */ | |
1493 | __kvm_restore_msa(&vcpu->arch); | |
f943176a | 1494 | vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; |
539cb89f | 1495 | if (kvm_mips_guest_has_fpu(&vcpu->arch)) |
f943176a | 1496 | vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; |
04ebebf4 JH |
1497 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, |
1498 | KVM_TRACE_AUX_FPU_MSA); | |
539cb89f JH |
1499 | break; |
1500 | default: | |
04ebebf4 | 1501 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA); |
539cb89f JH |
1502 | break; |
1503 | } | |
1504 | ||
1505 | preempt_enable(); | |
1506 | } | |
1507 | #endif | |
1508 | ||
1509 | /* Drop FPU & MSA without saving it */ | |
98e91b84 JH |
1510 | void kvm_drop_fpu(struct kvm_vcpu *vcpu) |
1511 | { | |
1512 | preempt_disable(); | |
f943176a | 1513 | if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { |
539cb89f | 1514 | disable_msa(); |
04ebebf4 | 1515 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA); |
f943176a | 1516 | vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA; |
539cb89f | 1517 | } |
f943176a | 1518 | if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { |
98e91b84 | 1519 | clear_c0_status(ST0_CU1 | ST0_FR); |
04ebebf4 | 1520 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU); |
f943176a | 1521 | vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; |
98e91b84 JH |
1522 | } |
1523 | preempt_enable(); | |
1524 | } | |
1525 | ||
539cb89f | 1526 | /* Save and disable FPU & MSA */ |
98e91b84 JH |
1527 | void kvm_lose_fpu(struct kvm_vcpu *vcpu) |
1528 | { | |
1529 | /* | |
539cb89f JH |
1530 | * FPU & MSA get disabled in root context (hardware) when it is disabled |
1531 | * in guest context (software), but the register state in the hardware | |
1532 | * may still be in use. This is why we explicitly re-enable the hardware | |
98e91b84 JH |
1533 | * before saving. |
1534 | */ | |
1535 | ||
1536 | preempt_disable(); | |
f943176a | 1537 | if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { |
539cb89f JH |
1538 | set_c0_config5(MIPS_CONF5_MSAEN); |
1539 | enable_fpu_hazard(); | |
1540 | ||
1541 | __kvm_save_msa(&vcpu->arch); | |
04ebebf4 | 1542 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA); |
539cb89f JH |
1543 | |
1544 | /* Disable MSA & FPU */ | |
1545 | disable_msa(); | |
f943176a | 1546 | if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { |
539cb89f | 1547 | clear_c0_status(ST0_CU1 | ST0_FR); |
4ac33429 JH |
1548 | disable_fpu_hazard(); |
1549 | } | |
f943176a JH |
1550 | vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA); |
1551 | } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { | |
98e91b84 JH |
1552 | set_c0_status(ST0_CU1); |
1553 | enable_fpu_hazard(); | |
1554 | ||
1555 | __kvm_save_fpu(&vcpu->arch); | |
f943176a | 1556 | vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; |
04ebebf4 | 1557 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU); |
98e91b84 JH |
1558 | |
1559 | /* Disable FPU */ | |
1560 | clear_c0_status(ST0_CU1 | ST0_FR); | |
4ac33429 | 1561 | disable_fpu_hazard(); |
98e91b84 JH |
1562 | } |
1563 | preempt_enable(); | |
1564 | } | |
1565 | ||
1566 | /* | |
539cb89f JH |
1567 | * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are |
1568 | * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP | |
1569 | * exception if cause bits are set in the value being written. | |
98e91b84 JH |
1570 | */ |
1571 | static int kvm_mips_csr_die_notify(struct notifier_block *self, | |
1572 | unsigned long cmd, void *ptr) | |
1573 | { | |
1574 | struct die_args *args = (struct die_args *)ptr; | |
1575 | struct pt_regs *regs = args->regs; | |
1576 | unsigned long pc; | |
1577 | ||
539cb89f JH |
1578 | /* Only interested in FPE and MSAFPE */ |
1579 | if (cmd != DIE_FP && cmd != DIE_MSAFP) | |
98e91b84 JH |
1580 | return NOTIFY_DONE; |
1581 | ||
1582 | /* Return immediately if guest context isn't active */ | |
1583 | if (!(current->flags & PF_VCPU)) | |
1584 | return NOTIFY_DONE; | |
1585 | ||
1586 | /* Should never get here from user mode */ | |
1587 | BUG_ON(user_mode(regs)); | |
1588 | ||
1589 | pc = instruction_pointer(regs); | |
1590 | switch (cmd) { | |
1591 | case DIE_FP: | |
1592 | /* match 2nd instruction in __kvm_restore_fcsr */ | |
1593 | if (pc != (unsigned long)&__kvm_restore_fcsr + 4) | |
1594 | return NOTIFY_DONE; | |
1595 | break; | |
539cb89f JH |
1596 | case DIE_MSAFP: |
1597 | /* match 2nd/3rd instruction in __kvm_restore_msacsr */ | |
1598 | if (!cpu_has_msa || | |
1599 | pc < (unsigned long)&__kvm_restore_msacsr + 4 || | |
1600 | pc > (unsigned long)&__kvm_restore_msacsr + 8) | |
1601 | return NOTIFY_DONE; | |
1602 | break; | |
98e91b84 JH |
1603 | } |
1604 | ||
1605 | /* Move PC forward a little and continue executing */ | |
1606 | instruction_pointer(regs) += 4; | |
1607 | ||
1608 | return NOTIFY_STOP; | |
1609 | } | |
1610 | ||
1611 | static struct notifier_block kvm_mips_csr_die_notifier = { | |
1612 | .notifier_call = kvm_mips_csr_die_notify, | |
1613 | }; | |
1614 | ||
2db9d233 | 1615 | static int __init kvm_mips_init(void) |
669e846e SL |
1616 | { |
1617 | int ret; | |
1618 | ||
1e5217f5 JH |
1619 | ret = kvm_mips_entry_setup(); |
1620 | if (ret) | |
1621 | return ret; | |
1622 | ||
669e846e SL |
1623 | ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); |
1624 | ||
1625 | if (ret) | |
1626 | return ret; | |
1627 | ||
98e91b84 JH |
1628 | register_die_notifier(&kvm_mips_csr_die_notifier); |
1629 | ||
669e846e SL |
1630 | return 0; |
1631 | } | |
1632 | ||
2db9d233 | 1633 | static void __exit kvm_mips_exit(void) |
669e846e SL |
1634 | { |
1635 | kvm_exit(); | |
1636 | ||
98e91b84 | 1637 | unregister_die_notifier(&kvm_mips_csr_die_notifier); |
669e846e SL |
1638 | } |
1639 | ||
1640 | module_init(kvm_mips_init); | |
1641 | module_exit(kvm_mips_exit); | |
1642 | ||
1643 | EXPORT_TRACEPOINT_SYMBOL(kvm_exit); |