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d41ced01 JC |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify it | |
3 | * under the terms of the GNU General Public License version 2 as published | |
4 | * by the Free Software Foundation. | |
5 | * | |
6 | * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> | |
97b92108 | 7 | * Copyright (C) 2011 John Crispin <john@phrozen.org> |
d41ced01 JC |
8 | */ |
9 | ||
10 | #include <linux/ioport.h> | |
11 | #include <linux/export.h> | |
12 | #include <linux/clkdev.h> | |
13 | #include <linux/of_address.h> | |
14 | #include <asm/delay.h> | |
15 | ||
16 | #include <lantiq_soc.h> | |
17 | ||
18 | #include "../clk.h" | |
19 | ||
20 | /* infrastructure control register */ | |
21 | #define SYS1_INFRAC 0x00bc | |
22 | /* Configuration fuses for drivers and pll */ | |
23 | #define STATUS_CONFIG 0x0040 | |
24 | ||
25 | /* GPE frequency selection */ | |
26 | #define GPPC_OFFSET 24 | |
ba735155 | 27 | #define GPEFREQ_MASK 0x0000C00 |
d41ced01 JC |
28 | #define GPEFREQ_OFFSET 10 |
29 | /* Clock status register */ | |
30 | #define SYSCTL_CLKS 0x0000 | |
31 | /* Clock enable register */ | |
32 | #define SYSCTL_CLKEN 0x0004 | |
33 | /* Clock clear register */ | |
34 | #define SYSCTL_CLKCLR 0x0008 | |
35 | /* Activation Status Register */ | |
36 | #define SYSCTL_ACTS 0x0020 | |
37 | /* Activation Register */ | |
38 | #define SYSCTL_ACT 0x0024 | |
39 | /* Deactivation Register */ | |
40 | #define SYSCTL_DEACT 0x0028 | |
41 | /* reboot Register */ | |
42 | #define SYSCTL_RBT 0x002c | |
43 | /* CPU0 Clock Control Register */ | |
44 | #define SYS1_CPU0CC 0x0040 | |
45 | /* HRST_OUT_N Control Register */ | |
46 | #define SYS1_HRSTOUTC 0x00c0 | |
47 | /* clock divider bit */ | |
48 | #define CPU0CC_CPUDIV 0x0001 | |
49 | ||
50 | /* Activation Status Register */ | |
df8b5bed | 51 | #define ACTS_ASC0_ACT 0x00001000 |
9bc7ebcb | 52 | #define ACTS_SSC0 0x00002000 |
d41ced01 JC |
53 | #define ACTS_ASC1_ACT 0x00000800 |
54 | #define ACTS_I2C_ACT 0x00004000 | |
55 | #define ACTS_P0 0x00010000 | |
56 | #define ACTS_P1 0x00010000 | |
57 | #define ACTS_P2 0x00020000 | |
58 | #define ACTS_P3 0x00020000 | |
59 | #define ACTS_P4 0x00040000 | |
60 | #define ACTS_PADCTRL0 0x00100000 | |
61 | #define ACTS_PADCTRL1 0x00100000 | |
62 | #define ACTS_PADCTRL2 0x00200000 | |
63 | #define ACTS_PADCTRL3 0x00200000 | |
64 | #define ACTS_PADCTRL4 0x00400000 | |
65 | ||
66 | #define sysctl_w32(m, x, y) ltq_w32((x), sysctl_membase[m] + (y)) | |
67 | #define sysctl_r32(m, x) ltq_r32(sysctl_membase[m] + (x)) | |
68 | #define sysctl_w32_mask(m, clear, set, reg) \ | |
69 | sysctl_w32(m, (sysctl_r32(m, reg) & ~(clear)) | (set), reg) | |
70 | ||
71 | #define status_w32(x, y) ltq_w32((x), status_membase + (y)) | |
72 | #define status_r32(x) ltq_r32(status_membase + (x)) | |
73 | ||
74 | static void __iomem *sysctl_membase[3], *status_membase; | |
75 | void __iomem *ltq_sys1_membase, *ltq_ebu_membase; | |
76 | ||
77 | void falcon_trigger_hrst(int level) | |
78 | { | |
79 | sysctl_w32(SYSCTL_SYS1, level & 1, SYS1_HRSTOUTC); | |
80 | } | |
81 | ||
82 | static inline void sysctl_wait(struct clk *clk, | |
83 | unsigned int test, unsigned int reg) | |
84 | { | |
85 | int err = 1000000; | |
86 | ||
87 | do {} while (--err && ((sysctl_r32(clk->module, reg) | |
88 | & clk->bits) != test)); | |
89 | if (!err) | |
90 | pr_err("module de/activation failed %d %08X %08X %08X\n", | |
91 | clk->module, clk->bits, test, | |
92 | sysctl_r32(clk->module, reg) & clk->bits); | |
93 | } | |
94 | ||
95 | static int sysctl_activate(struct clk *clk) | |
96 | { | |
97 | sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); | |
98 | sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); | |
99 | sysctl_wait(clk, clk->bits, SYSCTL_ACTS); | |
100 | return 0; | |
101 | } | |
102 | ||
103 | static void sysctl_deactivate(struct clk *clk) | |
104 | { | |
105 | sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR); | |
106 | sysctl_w32(clk->module, clk->bits, SYSCTL_DEACT); | |
107 | sysctl_wait(clk, 0, SYSCTL_ACTS); | |
108 | } | |
109 | ||
110 | static int sysctl_clken(struct clk *clk) | |
111 | { | |
112 | sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); | |
df8b5bed | 113 | sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); |
d41ced01 JC |
114 | sysctl_wait(clk, clk->bits, SYSCTL_CLKS); |
115 | return 0; | |
116 | } | |
117 | ||
118 | static void sysctl_clkdis(struct clk *clk) | |
119 | { | |
120 | sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR); | |
121 | sysctl_wait(clk, 0, SYSCTL_CLKS); | |
122 | } | |
123 | ||
124 | static void sysctl_reboot(struct clk *clk) | |
125 | { | |
126 | unsigned int act; | |
127 | unsigned int bits; | |
128 | ||
129 | act = sysctl_r32(clk->module, SYSCTL_ACT); | |
130 | bits = ~act & clk->bits; | |
131 | if (bits != 0) { | |
132 | sysctl_w32(clk->module, bits, SYSCTL_CLKEN); | |
133 | sysctl_w32(clk->module, bits, SYSCTL_ACT); | |
134 | sysctl_wait(clk, bits, SYSCTL_ACTS); | |
135 | } | |
136 | sysctl_w32(clk->module, act & clk->bits, SYSCTL_RBT); | |
137 | sysctl_wait(clk, clk->bits, SYSCTL_ACTS); | |
138 | } | |
139 | ||
140 | /* enable the ONU core */ | |
141 | static void falcon_gpe_enable(void) | |
142 | { | |
143 | unsigned int freq; | |
144 | unsigned int status; | |
145 | ||
146 | /* if if the clock is already enabled */ | |
147 | status = sysctl_r32(SYSCTL_SYS1, SYS1_INFRAC); | |
148 | if (status & (1 << (GPPC_OFFSET + 1))) | |
149 | return; | |
150 | ||
eb5dbd22 JC |
151 | freq = (status_r32(STATUS_CONFIG) & |
152 | GPEFREQ_MASK) >> | |
153 | GPEFREQ_OFFSET; | |
154 | if (freq == 0) | |
d41ced01 | 155 | freq = 1; /* use 625MHz on unfused chip */ |
d41ced01 JC |
156 | |
157 | /* apply new frequency */ | |
158 | sysctl_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1), | |
159 | freq << (GPPC_OFFSET + 2) , SYS1_INFRAC); | |
160 | udelay(1); | |
161 | ||
162 | /* enable new frequency */ | |
163 | sysctl_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC); | |
164 | udelay(1); | |
165 | } | |
166 | ||
167 | static inline void clkdev_add_sys(const char *dev, unsigned int module, | |
168 | unsigned int bits) | |
169 | { | |
170 | struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); | |
171 | ||
172 | clk->cl.dev_id = dev; | |
173 | clk->cl.con_id = NULL; | |
174 | clk->cl.clk = clk; | |
175 | clk->module = module; | |
3a6ac500 | 176 | clk->bits = bits; |
d41ced01 JC |
177 | clk->activate = sysctl_activate; |
178 | clk->deactivate = sysctl_deactivate; | |
179 | clk->enable = sysctl_clken; | |
180 | clk->disable = sysctl_clkdis; | |
181 | clk->reboot = sysctl_reboot; | |
182 | clkdev_add(&clk->cl); | |
183 | } | |
184 | ||
185 | void __init ltq_soc_init(void) | |
186 | { | |
187 | struct device_node *np_status = | |
188 | of_find_compatible_node(NULL, NULL, "lantiq,status-falcon"); | |
189 | struct device_node *np_ebu = | |
190 | of_find_compatible_node(NULL, NULL, "lantiq,ebu-falcon"); | |
191 | struct device_node *np_sys1 = | |
192 | of_find_compatible_node(NULL, NULL, "lantiq,sys1-falcon"); | |
193 | struct device_node *np_syseth = | |
194 | of_find_compatible_node(NULL, NULL, "lantiq,syseth-falcon"); | |
195 | struct device_node *np_sysgpe = | |
196 | of_find_compatible_node(NULL, NULL, "lantiq,sysgpe-falcon"); | |
197 | struct resource res_status, res_ebu, res_sys[3]; | |
198 | int i; | |
199 | ||
200 | /* check if all the core register ranges are available */ | |
201 | if (!np_status || !np_ebu || !np_sys1 || !np_syseth || !np_sysgpe) | |
202 | panic("Failed to load core nodes from devicetree"); | |
203 | ||
204 | if (of_address_to_resource(np_status, 0, &res_status) || | |
205 | of_address_to_resource(np_ebu, 0, &res_ebu) || | |
206 | of_address_to_resource(np_sys1, 0, &res_sys[0]) || | |
207 | of_address_to_resource(np_syseth, 0, &res_sys[1]) || | |
208 | of_address_to_resource(np_sysgpe, 0, &res_sys[2])) | |
209 | panic("Failed to get core resources"); | |
210 | ||
211 | if ((request_mem_region(res_status.start, resource_size(&res_status), | |
212 | res_status.name) < 0) || | |
213 | (request_mem_region(res_ebu.start, resource_size(&res_ebu), | |
214 | res_ebu.name) < 0) || | |
215 | (request_mem_region(res_sys[0].start, | |
216 | resource_size(&res_sys[0]), | |
217 | res_sys[0].name) < 0) || | |
218 | (request_mem_region(res_sys[1].start, | |
219 | resource_size(&res_sys[1]), | |
220 | res_sys[1].name) < 0) || | |
221 | (request_mem_region(res_sys[2].start, | |
222 | resource_size(&res_sys[2]), | |
223 | res_sys[2].name) < 0)) | |
1a84db56 | 224 | pr_err("Failed to request core resources"); |
d41ced01 JC |
225 | |
226 | status_membase = ioremap_nocache(res_status.start, | |
227 | resource_size(&res_status)); | |
228 | ltq_ebu_membase = ioremap_nocache(res_ebu.start, | |
229 | resource_size(&res_ebu)); | |
230 | ||
231 | if (!status_membase || !ltq_ebu_membase) | |
232 | panic("Failed to remap core resources"); | |
233 | ||
234 | for (i = 0; i < 3; i++) { | |
235 | sysctl_membase[i] = ioremap_nocache(res_sys[i].start, | |
236 | resource_size(&res_sys[i])); | |
237 | if (!sysctl_membase[i]) | |
238 | panic("Failed to remap sysctrl resources"); | |
239 | } | |
240 | ltq_sys1_membase = sysctl_membase[0]; | |
241 | ||
242 | falcon_gpe_enable(); | |
243 | ||
244 | /* get our 3 static rates for cpu, fpi and io clocks */ | |
245 | if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV) | |
740c606e | 246 | clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0); |
d41ced01 | 247 | else |
740c606e | 248 | clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0); |
d41ced01 JC |
249 | |
250 | /* add our clock domains */ | |
251 | clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0); | |
252 | clkdev_add_sys("1d810100.gpio", SYSCTL_SYSETH, ACTS_P2); | |
253 | clkdev_add_sys("1e800100.gpio", SYSCTL_SYS1, ACTS_P1); | |
254 | clkdev_add_sys("1e800200.gpio", SYSCTL_SYS1, ACTS_P3); | |
255 | clkdev_add_sys("1e800300.gpio", SYSCTL_SYS1, ACTS_P4); | |
256 | clkdev_add_sys("1db01000.pad", SYSCTL_SYSETH, ACTS_PADCTRL0); | |
257 | clkdev_add_sys("1db02000.pad", SYSCTL_SYSETH, ACTS_PADCTRL2); | |
258 | clkdev_add_sys("1e800400.pad", SYSCTL_SYS1, ACTS_PADCTRL1); | |
259 | clkdev_add_sys("1e800500.pad", SYSCTL_SYS1, ACTS_PADCTRL3); | |
260 | clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4); | |
df8b5bed TL |
261 | clkdev_add_sys("1e100b00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT); |
262 | clkdev_add_sys("1e100c00.serial", SYSCTL_SYS1, ACTS_ASC0_ACT); | |
9bc7ebcb | 263 | clkdev_add_sys("1e100d00.spi", SYSCTL_SYS1, ACTS_SSC0); |
d41ced01 JC |
264 | clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT); |
265 | } |