[mirror_ubuntu-artful-kernel.git] / arch / mips / lantiq / irq.c

/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
 */

#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/irqdomain.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <asm/bootinfo.h>
#include <asm/irq_cpu.h>

#include <lantiq_soc.h>
#include <irq.h>

/* register definitions - internal irqs */
#define LTQ_ICU_IM0_ISR		0x0000
#define LTQ_ICU_IM0_IER		0x0008
#define LTQ_ICU_IM0_IOSR	0x0010
#define LTQ_ICU_IM0_IRSR	0x0018
#define LTQ_ICU_IM0_IMR		0x0020
#define LTQ_ICU_IM1_ISR		0x0028
#define LTQ_ICU_OFFSET		(LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)

/* register definitions - external irqs */
#define LTQ_EIU_EXIN_C		0x0000
#define LTQ_EIU_EXIN_INIC	0x0004
#define LTQ_EIU_EXIN_INEN	0x000C

/* irq numbers used by the external interrupt unit (EIU) */
#define LTQ_EIU_IR0		(INT_NUM_IM4_IRL0 + 30)
#define LTQ_EIU_IR1		(INT_NUM_IM3_IRL0 + 31)
#define LTQ_EIU_IR2		(INT_NUM_IM1_IRL0 + 26)
#define LTQ_EIU_IR3		INT_NUM_IM1_IRL0
#define LTQ_EIU_IR4		(INT_NUM_IM1_IRL0 + 1)
#define LTQ_EIU_IR5		(INT_NUM_IM1_IRL0 + 2)
#define LTQ_EIU_IR6		(INT_NUM_IM2_IRL0 + 30)
#define XWAY_EXIN_COUNT		3
#define MAX_EIU			6

/* the performance counter */
#define LTQ_PERF_IRQ		(INT_NUM_IM4_IRL0 + 31)

/*
 * irqs generated by devices attached to the EBU need to be acked in
 * a special manner
 */
#define LTQ_ICU_EBU_IRQ		22

#define ltq_icu_w32(m, x, y)	ltq_w32((x), ltq_icu_membase[m] + (y))
#define ltq_icu_r32(m, x)	ltq_r32(ltq_icu_membase[m] + (x))

#define ltq_eiu_w32(x, y)	ltq_w32((x), ltq_eiu_membase + (y))
#define ltq_eiu_r32(x)		ltq_r32(ltq_eiu_membase + (x))

/* our 2 ipi interrupts for VSMP */
#define MIPS_CPU_IPI_RESCHED_IRQ	0
#define MIPS_CPU_IPI_CALL_IRQ		1

/* we have a cascade of 8 irqs */
#define MIPS_CPU_IRQ_CASCADE		8

#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
int gic_present;
#endif

static unsigned short ltq_eiu_irq[MAX_EIU] = {
	LTQ_EIU_IR0,
	LTQ_EIU_IR1,
	LTQ_EIU_IR2,
	LTQ_EIU_IR3,
	LTQ_EIU_IR4,
	LTQ_EIU_IR5,
};

static int exin_avail;
static void __iomem *ltq_icu_membase[MAX_IM];
static void __iomem *ltq_eiu_membase;

void ltq_disable_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
}

void ltq_mask_and_ack_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	u32 isr = LTQ_ICU_IM0_ISR;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
	ltq_icu_w32(im, BIT(offset), isr);
}

static void ltq_ack_irq(struct irq_data *d)
{
	u32 isr = LTQ_ICU_IM0_ISR;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, BIT(offset), isr);
}

void ltq_enable_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
	int im = offset / INT_NUM_IM_OFFSET;

	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
}

static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
{
	int i;

	ltq_enable_irq(d);
	for (i = 0; i < MAX_EIU; i++) {
		if (d->hwirq == ltq_eiu_irq[i]) {
			/* low level - we should really handle set_type */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
				(0x6 << (i * 4)), LTQ_EIU_EXIN_C);
			/* clear all pending */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i),
				LTQ_EIU_EXIN_INIC);
			/* enable */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
				LTQ_EIU_EXIN_INEN);
			break;
		}
	}

	return 0;
}

static void ltq_shutdown_eiu_irq(struct irq_data *d)
{
	int i;

	ltq_disable_irq(d);
	for (i = 0; i < MAX_EIU; i++) {
		if (d->hwirq == ltq_eiu_irq[i]) {
			/* disable */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
				LTQ_EIU_EXIN_INEN);
			break;
		}
	}
}

static struct irq_chip ltq_irq_type = {
	"icu",
	.irq_enable = ltq_enable_irq,
	.irq_disable = ltq_disable_irq,
	.irq_unmask = ltq_enable_irq,
	.irq_ack = ltq_ack_irq,
	.irq_mask = ltq_disable_irq,
	.irq_mask_ack = ltq_mask_and_ack_irq,
};

static struct irq_chip ltq_eiu_type = {
	"eiu",
	.irq_startup = ltq_startup_eiu_irq,
	.irq_shutdown = ltq_shutdown_eiu_irq,
	.irq_enable = ltq_enable_irq,
	.irq_disable = ltq_disable_irq,
	.irq_unmask = ltq_enable_irq,
	.irq_ack = ltq_ack_irq,
	.irq_mask = ltq_disable_irq,
	.irq_mask_ack = ltq_mask_and_ack_irq,
};

static void ltq_hw_irqdispatch(int module)
{
	u32 irq;

	irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
	if (irq == 0)
		return;

	/*
	 * silicon bug causes only the msb set to 1 to be valid. all
	 * other bits might be bogus
	 */
	irq = __fls(irq);
	do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));

	/* if this is a EBU irq, we need to ack it or get a deadlock */
	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
		ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
			LTQ_EBU_PCC_ISTAT);
}

#define DEFINE_HWx_IRQDISPATCH(x)					\
	static void ltq_hw ## x ## _irqdispatch(void)			\
	{								\
		ltq_hw_irqdispatch(x);					\
	}
DEFINE_HWx_IRQDISPATCH(0)
DEFINE_HWx_IRQDISPATCH(1)
DEFINE_HWx_IRQDISPATCH(2)
DEFINE_HWx_IRQDISPATCH(3)
DEFINE_HWx_IRQDISPATCH(4)

static void ltq_hw5_irqdispatch(void)
{
	do_IRQ(MIPS_CPU_TIMER_IRQ);
}

#ifdef CONFIG_MIPS_MT_SMP
void __init arch_init_ipiirq(int irq, struct irqaction *action)
{
	setup_irq(irq, action);
	irq_set_handler(irq, handle_percpu_irq);
}

static void ltq_sw0_irqdispatch(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
}

static void ltq_sw1_irqdispatch(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
}
static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
{
	scheduler_ipi();
	return IRQ_HANDLED;
}

static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
{
	smp_call_function_interrupt();
	return IRQ_HANDLED;
}

static struct irqaction irq_resched = {
	.handler	= ipi_resched_interrupt,
	.flags		= IRQF_PERCPU,
	.name		= "IPI_resched"
};

static struct irqaction irq_call = {
	.handler	= ipi_call_interrupt,
	.flags		= IRQF_PERCPU,
	.name		= "IPI_call"
};
#endif

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
	unsigned int i;

	if (pending & CAUSEF_IP7) {
		do_IRQ(MIPS_CPU_TIMER_IRQ);
		goto out;
	} else {
		for (i = 0; i < MAX_IM; i++) {
			if (pending & (CAUSEF_IP2 << i)) {
				ltq_hw_irqdispatch(i);
				goto out;
			}
		}
	}
	pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());

out:
	return;
}

static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
{
	struct irq_chip *chip = &ltq_irq_type;
	int i;

	for (i = 0; i < exin_avail; i++)
		if (hw == ltq_eiu_irq[i])
			chip = &ltq_eiu_type;

	irq_set_chip_and_handler(hw, chip, handle_level_irq);

	return 0;
}

static const struct irq_domain_ops irq_domain_ops = {
	.xlate = irq_domain_xlate_onetwocell,
	.map = icu_map,
};

static struct irqaction cascade = {
	.handler = no_action,
	.name = "cascade",
};

int __init icu_of_init(struct device_node *node, struct device_node *parent)
{
	struct device_node *eiu_node;
	struct resource res;
	int i;

	for (i = 0; i < MAX_IM; i++) {
		if (of_address_to_resource(node, i, &res))
			panic("Failed to get icu memory range");

		if (request_mem_region(res.start, resource_size(&res),
					res.name) < 0)
			pr_err("Failed to request icu memory");

		ltq_icu_membase[i] = ioremap_nocache(res.start,
					resource_size(&res));
		if (!ltq_icu_membase[i])
			panic("Failed to remap icu memory");
	}

	/* the external interrupts are optional and xway only */
	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
	if (eiu_node && of_address_to_resource(eiu_node, 0, &res)) {
		/* find out how many external irq sources we have */
		const __be32 *count = of_get_property(node,
							"lantiq,count",	NULL);

		if (count)
			exin_avail = *count;
		if (exin_avail > MAX_EIU)
			exin_avail = MAX_EIU;

		if (request_mem_region(res.start, resource_size(&res),
							res.name) < 0)
			pr_err("Failed to request eiu memory");

		ltq_eiu_membase = ioremap_nocache(res.start,
							resource_size(&res));
		if (!ltq_eiu_membase)
			panic("Failed to remap eiu memory");
	}

	/* turn off all irqs by default */
	for (i = 0; i < MAX_IM; i++) {
		/* make sure all irqs are turned off by default */
		ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
		/* clear all possibly pending interrupts */
		ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
	}

	mips_cpu_irq_init();

	for (i = 0; i < MAX_IM; i++)
		setup_irq(i + 2, &cascade);

	if (cpu_has_vint) {
		pr_info("Setting up vectored interrupts\n");
		set_vi_handler(2, ltq_hw0_irqdispatch);
		set_vi_handler(3, ltq_hw1_irqdispatch);
		set_vi_handler(4, ltq_hw2_irqdispatch);
		set_vi_handler(5, ltq_hw3_irqdispatch);
		set_vi_handler(6, ltq_hw4_irqdispatch);
		set_vi_handler(7, ltq_hw5_irqdispatch);
	}

	irq_domain_add_linear(node,
		(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
		&irq_domain_ops, 0);

#if defined(CONFIG_MIPS_MT_SMP)
	if (cpu_has_vint) {
		pr_info("Setting up IPI vectored interrupts\n");
		set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
		set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
	}
	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
		&irq_resched);
	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
#endif

#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
		IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#else
	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
		IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#endif

	/* tell oprofile which irq to use */
	cp0_perfcount_irq = LTQ_PERF_IRQ;
	return 0;
}

unsigned int __cpuinit get_c0_compare_int(void)
{
	return CP0_LEGACY_COMPARE_IRQ;
}

static struct of_device_id __initdata of_irq_ids[] = {
	{ .compatible = "lantiq,icu", .data = icu_of_init },
	{},
};

void __init arch_init_irq(void)
{
	of_irq_init(of_irq_ids);
}
Commit	Line	Data
171bb2f1 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
	6	* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
	7	* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
	8	*/
	9
	10	#include <linux/interrupt.h>
	11	#include <linux/ioport.h>
3645da02 JC	12	#include <linux/sched.h>
	13	#include <linux/irqdomain.h>
	14	#include <linux/of_platform.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of_irq.h>
171bb2f1 JC	17
	18	#include <asm/bootinfo.h>
	19	#include <asm/irq_cpu.h>
	20
	21	#include <lantiq_soc.h>
	22	#include <irq.h>
	23
3645da02	24	/* register definitions - internal irqs */
171bb2f1 JC	25	#define LTQ_ICU_IM0_ISR 0x0000
	26	#define LTQ_ICU_IM0_IER 0x0008
	27	#define LTQ_ICU_IM0_IOSR 0x0010
	28	#define LTQ_ICU_IM0_IRSR 0x0018
	29	#define LTQ_ICU_IM0_IMR 0x0020
	30	#define LTQ_ICU_IM1_ISR 0x0028
	31	#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
	32
3645da02	33	/* register definitions - external irqs */
171bb2f1 JC	34	#define LTQ_EIU_EXIN_C 0x0000
	35	#define LTQ_EIU_EXIN_INIC 0x0004
	36	#define LTQ_EIU_EXIN_INEN 0x000C
	37
	38	/* irq numbers used by the external interrupt unit (EIU) */
	39	#define LTQ_EIU_IR0 (INT_NUM_IM4_IRL0 + 30)
	40	#define LTQ_EIU_IR1 (INT_NUM_IM3_IRL0 + 31)
	41	#define LTQ_EIU_IR2 (INT_NUM_IM1_IRL0 + 26)
	42	#define LTQ_EIU_IR3 INT_NUM_IM1_IRL0
	43	#define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1)
	44	#define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2)
	45	#define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30)
3645da02	46	#define XWAY_EXIN_COUNT 3
171bb2f1 JC	47	#define MAX_EIU 6
171bb2f1 JC	48
59c11579 JC	49	/* the performance counter */
	50	#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
	51
3645da02 JC	52	/*
3645da02 JC	53	* irqs generated by devices attached to the EBU need to be acked in
171bb2f1 JC	54	* a special manner
	55	*/
	56	#define LTQ_ICU_EBU_IRQ 22
	57
61fa969f JC	58	#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
61fa969f JC	59	#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
171bb2f1 JC	60
	61	#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
	62	#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
	63
a8d096ef JC	64	/* our 2 ipi interrupts for VSMP */
	65	#define MIPS_CPU_IPI_RESCHED_IRQ 0
	66	#define MIPS_CPU_IPI_CALL_IRQ 1
	67
3645da02 JC	68	/* we have a cascade of 8 irqs */
	69	#define MIPS_CPU_IRQ_CASCADE 8
	70
a8d096ef JC	71	#if defined(CONFIG_MIPS_MT_SMP) \|\| defined(CONFIG_MIPS_MT_SMTC)
	72	int gic_present;
	73	#endif
	74
171bb2f1 JC	75	static unsigned short ltq_eiu_irq[MAX_EIU] = {
	76	LTQ_EIU_IR0,
	77	LTQ_EIU_IR1,
	78	LTQ_EIU_IR2,
	79	LTQ_EIU_IR3,
	80	LTQ_EIU_IR4,
	81	LTQ_EIU_IR5,
	82	};
	83
3645da02	84	static int exin_avail;
61fa969f	85	static void __iomem *ltq_icu_membase[MAX_IM];
171bb2f1 JC	86	static void __iomem *ltq_eiu_membase;
	87
	88	void ltq_disable_irq(struct irq_data *d)
	89	{
	90	u32 ier = LTQ_ICU_IM0_IER;
3645da02	91	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	92	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	93
3645da02	94	offset %= INT_NUM_IM_OFFSET;
61fa969f	95	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
171bb2f1 JC	96	}
	97
	98	void ltq_mask_and_ack_irq(struct irq_data *d)
	99	{
	100	u32 ier = LTQ_ICU_IM0_IER;
	101	u32 isr = LTQ_ICU_IM0_ISR;
3645da02	102	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	103	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	104
3645da02	105	offset %= INT_NUM_IM_OFFSET;
61fa969f JC	106	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
61fa969f JC	107	ltq_icu_w32(im, BIT(offset), isr);
171bb2f1 JC	108	}
	109
	110	static void ltq_ack_irq(struct irq_data *d)
	111	{
	112	u32 isr = LTQ_ICU_IM0_ISR;
3645da02	113	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	114	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	115
3645da02	116	offset %= INT_NUM_IM_OFFSET;
61fa969f	117	ltq_icu_w32(im, BIT(offset), isr);
171bb2f1 JC	118	}
	119
	120	void ltq_enable_irq(struct irq_data *d)
	121	{
	122	u32 ier = LTQ_ICU_IM0_IER;
3645da02	123	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
61fa969f	124	int im = offset / INT_NUM_IM_OFFSET;
171bb2f1	125
3645da02	126	offset %= INT_NUM_IM_OFFSET;
61fa969f	127	ltq_icu_w32(im, ltq_icu_r32(im, ier) \| BIT(offset), ier);
171bb2f1 JC	128	}
	129
	130	static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
	131	{
	132	int i;
171bb2f1 JC	133
	134	ltq_enable_irq(d);
	135	for (i = 0; i < MAX_EIU; i++) {
3645da02	136	if (d->hwirq == ltq_eiu_irq[i]) {
171bb2f1 JC	137	/* low level - we should really handle set_type */
	138	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) \|
	139	(0x6 << (i * 4)), LTQ_EIU_EXIN_C);
	140	/* clear all pending */
3645da02	141	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i),
171bb2f1 JC	142	LTQ_EIU_EXIN_INIC);
171bb2f1 JC	143	/* enable */
3645da02	144	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) \| BIT(i),
171bb2f1 JC	145	LTQ_EIU_EXIN_INEN);
	146	break;
	147	}
	148	}
	149
	150	return 0;
	151	}
	152
	153	static void ltq_shutdown_eiu_irq(struct irq_data *d)
	154	{
	155	int i;
171bb2f1 JC	156
	157	ltq_disable_irq(d);
	158	for (i = 0; i < MAX_EIU; i++) {
3645da02	159	if (d->hwirq == ltq_eiu_irq[i]) {
171bb2f1	160	/* disable */
3645da02	161	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
171bb2f1 JC	162	LTQ_EIU_EXIN_INEN);
	163	break;
	164	}
	165	}
	166	}
	167
	168	static struct irq_chip ltq_irq_type = {
	169	"icu",
	170	.irq_enable = ltq_enable_irq,
	171	.irq_disable = ltq_disable_irq,
	172	.irq_unmask = ltq_enable_irq,
	173	.irq_ack = ltq_ack_irq,
	174	.irq_mask = ltq_disable_irq,
	175	.irq_mask_ack = ltq_mask_and_ack_irq,
	176	};
	177
	178	static struct irq_chip ltq_eiu_type = {
	179	"eiu",
	180	.irq_startup = ltq_startup_eiu_irq,
	181	.irq_shutdown = ltq_shutdown_eiu_irq,
	182	.irq_enable = ltq_enable_irq,
	183	.irq_disable = ltq_disable_irq,
	184	.irq_unmask = ltq_enable_irq,
	185	.irq_ack = ltq_ack_irq,
	186	.irq_mask = ltq_disable_irq,
	187	.irq_mask_ack = ltq_mask_and_ack_irq,
	188	};
	189
	190	static void ltq_hw_irqdispatch(int module)
	191	{
	192	u32 irq;
	193
61fa969f	194	irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
171bb2f1 JC	195	if (irq == 0)
	196	return;
	197
3645da02 JC	198	/*
3645da02 JC	199	* silicon bug causes only the msb set to 1 to be valid. all
171bb2f1 JC	200	* other bits might be bogus
	201	*/
	202	irq = __fls(irq);
3645da02	203	do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
171bb2f1 JC	204
171bb2f1 JC	205	/* if this is a EBU irq, we need to ack it or get a deadlock */
3645da02	206	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
171bb2f1 JC	207	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) \| 0x10,
	208	LTQ_EBU_PCC_ISTAT);
	209	}
	210
	211	#define DEFINE_HWx_IRQDISPATCH(x) \
	212	static void ltq_hw ## x ## _irqdispatch(void) \
	213	{ \
	214	ltq_hw_irqdispatch(x); \
	215	}
	216	DEFINE_HWx_IRQDISPATCH(0)
	217	DEFINE_HWx_IRQDISPATCH(1)
	218	DEFINE_HWx_IRQDISPATCH(2)
	219	DEFINE_HWx_IRQDISPATCH(3)
	220	DEFINE_HWx_IRQDISPATCH(4)
	221
	222	static void ltq_hw5_irqdispatch(void)
	223	{
	224	do_IRQ(MIPS_CPU_TIMER_IRQ);
	225	}
	226
a8d096ef JC	227	#ifdef CONFIG_MIPS_MT_SMP
	228	void __init arch_init_ipiirq(int irq, struct irqaction *action)
	229	{
	230	setup_irq(irq, action);
	231	irq_set_handler(irq, handle_percpu_irq);
	232	}
	233
	234	static void ltq_sw0_irqdispatch(void)
	235	{
	236	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
	237	}
	238
	239	static void ltq_sw1_irqdispatch(void)
	240	{
	241	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
	242	}
	243	static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
	244	{
	245	scheduler_ipi();
	246	return IRQ_HANDLED;
	247	}
	248
	249	static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
	250	{
	251	smp_call_function_interrupt();
	252	return IRQ_HANDLED;
	253	}
	254
	255	static struct irqaction irq_resched = {
	256	.handler = ipi_resched_interrupt,
	257	.flags = IRQF_PERCPU,
	258	.name = "IPI_resched"
	259	};
	260
	261	static struct irqaction irq_call = {
	262	.handler = ipi_call_interrupt,
	263	.flags = IRQF_PERCPU,
	264	.name = "IPI_call"
	265	};
	266	#endif
	267
171bb2f1 JC	268	asmlinkage void plat_irq_dispatch(void)
	269	{
	270	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
	271	unsigned int i;
	272
	273	if (pending & CAUSEF_IP7) {
	274	do_IRQ(MIPS_CPU_TIMER_IRQ);
	275	goto out;
	276	} else {
61fa969f	277	for (i = 0; i < MAX_IM; i++) {
171bb2f1 JC	278	if (pending & (CAUSEF_IP2 << i)) {
	279	ltq_hw_irqdispatch(i);
	280	goto out;
	281	}
	282	}
	283	}
	284	pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
	285
	286	out:
	287	return;
	288	}
	289
3645da02 JC	290	static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
	291	{
	292	struct irq_chip *chip = &ltq_irq_type;
	293	int i;
	294
	295	for (i = 0; i < exin_avail; i++)
	296	if (hw == ltq_eiu_irq[i])
	297	chip = &ltq_eiu_type;
	298
	299	irq_set_chip_and_handler(hw, chip, handle_level_irq);
	300
	301	return 0;
	302	}
	303
	304	static const struct irq_domain_ops irq_domain_ops = {
	305	.xlate = irq_domain_xlate_onetwocell,
	306	.map = icu_map,
	307	};
	308
171bb2f1 JC	309	static struct irqaction cascade = {
171bb2f1 JC	310	.handler = no_action,
171bb2f1 JC	311	.name = "cascade",
	312	};
	313
3645da02	314	int __init icu_of_init(struct device_node node, struct device_node parent)
171bb2f1	315	{
3645da02 JC	316	struct device_node *eiu_node;
3645da02 JC	317	struct resource res;
171bb2f1 JC	318	int i;
171bb2f1 JC	319
61fa969f JC	320	for (i = 0; i < MAX_IM; i++) {
	321	if (of_address_to_resource(node, i, &res))
	322	panic("Failed to get icu memory range");
171bb2f1	323
61fa969f JC	324	if (request_mem_region(res.start, resource_size(&res),
	325	res.name) < 0)
	326	pr_err("Failed to request icu memory");
171bb2f1	327
61fa969f JC	328	ltq_icu_membase[i] = ioremap_nocache(res.start,
	329	resource_size(&res));
	330	if (!ltq_icu_membase[i])
	331	panic("Failed to remap icu memory");
	332	}
171bb2f1	333
3645da02 JC	334	/* the external interrupts are optional and xway only */
	335	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
	336	if (eiu_node && of_address_to_resource(eiu_node, 0, &res)) {
	337	/* find out how many external irq sources we have */
	338	const __be32 *count = of_get_property(node,
	339	"lantiq,count", NULL);
	340
	341	if (count)
	342	exin_avail = *count;
	343	if (exin_avail > MAX_EIU)
	344	exin_avail = MAX_EIU;
	345
	346	if (request_mem_region(res.start, resource_size(&res),
	347	res.name) < 0)
	348	pr_err("Failed to request eiu memory");
	349
	350	ltq_eiu_membase = ioremap_nocache(res.start,
	351	resource_size(&res));
	352	if (!ltq_eiu_membase)
	353	panic("Failed to remap eiu memory");
	354	}
171bb2f1	355
16f70b56	356	/* turn off all irqs by default */
61fa969f	357	for (i = 0; i < MAX_IM; i++) {
16f70b56	358	/* make sure all irqs are turned off by default */
61fa969f	359	ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
16f70b56	360	/* clear all possibly pending interrupts */
61fa969f	361	ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
16f70b56	362	}
171bb2f1 JC	363
	364	mips_cpu_irq_init();
	365
61fa969f JC	366	for (i = 0; i < MAX_IM; i++)
61fa969f JC	367	setup_irq(i + 2, &cascade);
171bb2f1 JC	368
	369	if (cpu_has_vint) {
	370	pr_info("Setting up vectored interrupts\n");
	371	set_vi_handler(2, ltq_hw0_irqdispatch);
	372	set_vi_handler(3, ltq_hw1_irqdispatch);
	373	set_vi_handler(4, ltq_hw2_irqdispatch);
	374	set_vi_handler(5, ltq_hw3_irqdispatch);
	375	set_vi_handler(6, ltq_hw4_irqdispatch);
	376	set_vi_handler(7, ltq_hw5_irqdispatch);
	377	}
	378
61fa969f JC	379	irq_domain_add_linear(node,
61fa969f JC	380	(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
3645da02	381	&irq_domain_ops, 0);
171bb2f1	382
a8d096ef JC	383	#if defined(CONFIG_MIPS_MT_SMP)
	384	if (cpu_has_vint) {
	385	pr_info("Setting up IPI vectored interrupts\n");
	386	set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
	387	set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
	388	}
	389	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
	390	&irq_resched);
	391	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
	392	#endif
	393
171bb2f1 JC	394	#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
	395	set_c0_status(IE_IRQ0 \| IE_IRQ1 \| IE_IRQ2 \|
	396	IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5);
	397	#else
	398	set_c0_status(IE_SW0 \| IE_SW1 \| IE_IRQ0 \| IE_IRQ1 \|
	399	IE_IRQ2 \| IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5);
	400	#endif
59c11579 JC	401
	402	/* tell oprofile which irq to use */
	403	cp0_perfcount_irq = LTQ_PERF_IRQ;
3645da02	404	return 0;
171bb2f1 JC	405	}
	406
	407	unsigned int __cpuinit get_c0_compare_int(void)
	408	{
	409	return CP0_LEGACY_COMPARE_IRQ;
	410	}
3645da02 JC	411
	412	static struct of_device_id __initdata of_irq_ids[] = {
	413	{ .compatible = "lantiq,icu", .data = icu_of_init },
	414	{},
	415	};
	416
	417	void __init arch_init_irq(void)
	418	{
	419	of_irq_init(of_irq_ids);
	420	}