[mirror_ubuntu-artful-kernel.git] / arch / mips / lantiq / irq.c

/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
 */

#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/irqdomain.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <asm/bootinfo.h>
#include <asm/irq_cpu.h>

#include <lantiq_soc.h>
#include <irq.h>

/* register definitions - internal irqs */
#define LTQ_ICU_IM0_ISR		0x0000
#define LTQ_ICU_IM0_IER		0x0008
#define LTQ_ICU_IM0_IOSR	0x0010
#define LTQ_ICU_IM0_IRSR	0x0018
#define LTQ_ICU_IM0_IMR		0x0020
#define LTQ_ICU_IM1_ISR		0x0028
#define LTQ_ICU_OFFSET		(LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)

/* register definitions - external irqs */
#define LTQ_EIU_EXIN_C		0x0000
#define LTQ_EIU_EXIN_INIC	0x0004
#define LTQ_EIU_EXIN_INEN	0x000C

/* irq numbers used by the external interrupt unit (EIU) */
#define LTQ_EIU_IR0		(INT_NUM_IM4_IRL0 + 30)
#define LTQ_EIU_IR1		(INT_NUM_IM3_IRL0 + 31)
#define LTQ_EIU_IR2		(INT_NUM_IM1_IRL0 + 26)
#define LTQ_EIU_IR3		INT_NUM_IM1_IRL0
#define LTQ_EIU_IR4		(INT_NUM_IM1_IRL0 + 1)
#define LTQ_EIU_IR5		(INT_NUM_IM1_IRL0 + 2)
#define LTQ_EIU_IR6		(INT_NUM_IM2_IRL0 + 30)
#define XWAY_EXIN_COUNT		3
#define MAX_EIU			6

/* the performance counter */
#define LTQ_PERF_IRQ		(INT_NUM_IM4_IRL0 + 31)

/*
 * irqs generated by devices attached to the EBU need to be acked in
 * a special manner
 */
#define LTQ_ICU_EBU_IRQ		22

#define ltq_icu_w32(x, y)	ltq_w32((x), ltq_icu_membase + (y))
#define ltq_icu_r32(x)		ltq_r32(ltq_icu_membase + (x))

#define ltq_eiu_w32(x, y)	ltq_w32((x), ltq_eiu_membase + (y))
#define ltq_eiu_r32(x)		ltq_r32(ltq_eiu_membase + (x))

/* our 2 ipi interrupts for VSMP */
#define MIPS_CPU_IPI_RESCHED_IRQ	0
#define MIPS_CPU_IPI_CALL_IRQ		1

/* we have a cascade of 8 irqs */
#define MIPS_CPU_IRQ_CASCADE		8

#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
int gic_present;
#endif

static unsigned short ltq_eiu_irq[MAX_EIU] = {
	LTQ_EIU_IR0,
	LTQ_EIU_IR1,
	LTQ_EIU_IR2,
	LTQ_EIU_IR3,
	LTQ_EIU_IR4,
	LTQ_EIU_IR5,
};

static int exin_avail;
static void __iomem *ltq_icu_membase;
static void __iomem *ltq_eiu_membase;

void ltq_disable_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;

	ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier);
}

void ltq_mask_and_ack_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	u32 isr = LTQ_ICU_IM0_ISR;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;

	ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
	isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier);
	ltq_icu_w32(BIT(offset), isr);
}

static void ltq_ack_irq(struct irq_data *d)
{
	u32 isr = LTQ_ICU_IM0_ISR;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;

	isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(BIT(offset), isr);
}

void ltq_enable_irq(struct irq_data *d)
{
	u32 ier = LTQ_ICU_IM0_IER;
	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;

	ier += LTQ_ICU_OFFSET  * (offset / INT_NUM_IM_OFFSET);
	offset %= INT_NUM_IM_OFFSET;
	ltq_icu_w32(ltq_icu_r32(ier) | BIT(offset), ier);
}

static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
{
	int i;

	ltq_enable_irq(d);
	for (i = 0; i < MAX_EIU; i++) {
		if (d->hwirq == ltq_eiu_irq[i]) {
			/* low level - we should really handle set_type */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
				(0x6 << (i * 4)), LTQ_EIU_EXIN_C);
			/* clear all pending */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i),
				LTQ_EIU_EXIN_INIC);
			/* enable */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
				LTQ_EIU_EXIN_INEN);
			break;
		}
	}

	return 0;
}

static void ltq_shutdown_eiu_irq(struct irq_data *d)
{
	int i;

	ltq_disable_irq(d);
	for (i = 0; i < MAX_EIU; i++) {
		if (d->hwirq == ltq_eiu_irq[i]) {
			/* disable */
			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
				LTQ_EIU_EXIN_INEN);
			break;
		}
	}
}

static struct irq_chip ltq_irq_type = {
	"icu",
	.irq_enable = ltq_enable_irq,
	.irq_disable = ltq_disable_irq,
	.irq_unmask = ltq_enable_irq,
	.irq_ack = ltq_ack_irq,
	.irq_mask = ltq_disable_irq,
	.irq_mask_ack = ltq_mask_and_ack_irq,
};

static struct irq_chip ltq_eiu_type = {
	"eiu",
	.irq_startup = ltq_startup_eiu_irq,
	.irq_shutdown = ltq_shutdown_eiu_irq,
	.irq_enable = ltq_enable_irq,
	.irq_disable = ltq_disable_irq,
	.irq_unmask = ltq_enable_irq,
	.irq_ack = ltq_ack_irq,
	.irq_mask = ltq_disable_irq,
	.irq_mask_ack = ltq_mask_and_ack_irq,
};

static void ltq_hw_irqdispatch(int module)
{
	u32 irq;

	irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET));
	if (irq == 0)
		return;

	/*
	 * silicon bug causes only the msb set to 1 to be valid. all
	 * other bits might be bogus
	 */
	irq = __fls(irq);
	do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));

	/* if this is a EBU irq, we need to ack it or get a deadlock */
	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
		ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
			LTQ_EBU_PCC_ISTAT);
}

#define DEFINE_HWx_IRQDISPATCH(x)					\
	static void ltq_hw ## x ## _irqdispatch(void)			\
	{								\
		ltq_hw_irqdispatch(x);					\
	}
DEFINE_HWx_IRQDISPATCH(0)
DEFINE_HWx_IRQDISPATCH(1)
DEFINE_HWx_IRQDISPATCH(2)
DEFINE_HWx_IRQDISPATCH(3)
DEFINE_HWx_IRQDISPATCH(4)

static void ltq_hw5_irqdispatch(void)
{
	do_IRQ(MIPS_CPU_TIMER_IRQ);
}

#ifdef CONFIG_MIPS_MT_SMP
void __init arch_init_ipiirq(int irq, struct irqaction *action)
{
	setup_irq(irq, action);
	irq_set_handler(irq, handle_percpu_irq);
}

static void ltq_sw0_irqdispatch(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
}

static void ltq_sw1_irqdispatch(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
}
static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
{
	scheduler_ipi();
	return IRQ_HANDLED;
}

static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
{
	smp_call_function_interrupt();
	return IRQ_HANDLED;
}

static struct irqaction irq_resched = {
	.handler	= ipi_resched_interrupt,
	.flags		= IRQF_PERCPU,
	.name		= "IPI_resched"
};

static struct irqaction irq_call = {
	.handler	= ipi_call_interrupt,
	.flags		= IRQF_PERCPU,
	.name		= "IPI_call"
};
#endif

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
	unsigned int i;

	if (pending & CAUSEF_IP7) {
		do_IRQ(MIPS_CPU_TIMER_IRQ);
		goto out;
	} else {
		for (i = 0; i < 5; i++) {
			if (pending & (CAUSEF_IP2 << i)) {
				ltq_hw_irqdispatch(i);
				goto out;
			}
		}
	}
	pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());

out:
	return;
}

static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
{
	struct irq_chip *chip = &ltq_irq_type;
	int i;

	for (i = 0; i < exin_avail; i++)
		if (hw == ltq_eiu_irq[i])
			chip = &ltq_eiu_type;

	irq_set_chip_and_handler(hw, chip, handle_level_irq);

	return 0;
}

static const struct irq_domain_ops irq_domain_ops = {
	.xlate = irq_domain_xlate_onetwocell,
	.map = icu_map,
};

static struct irqaction cascade = {
	.handler = no_action,
	.name = "cascade",
};

int __init icu_of_init(struct device_node *node, struct device_node *parent)
{
	struct device_node *eiu_node;
	struct resource res;
	int i;

	if (of_address_to_resource(node, 0, &res))
		panic("Failed to get icu memory range");

	if (request_mem_region(res.start, resource_size(&res), res.name) < 0)
		pr_err("Failed to request icu memory");

	ltq_icu_membase = ioremap_nocache(res.start, resource_size(&res));
	if (!ltq_icu_membase)
		panic("Failed to remap icu memory");

	/* the external interrupts are optional and xway only */
	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
	if (eiu_node && of_address_to_resource(eiu_node, 0, &res)) {
		/* find out how many external irq sources we have */
		const __be32 *count = of_get_property(node,
							"lantiq,count",	NULL);

		if (count)
			exin_avail = *count;
		if (exin_avail > MAX_EIU)
			exin_avail = MAX_EIU;

		if (request_mem_region(res.start, resource_size(&res),
							res.name) < 0)
			pr_err("Failed to request eiu memory");

		ltq_eiu_membase = ioremap_nocache(res.start,
							resource_size(&res));
		if (!ltq_eiu_membase)
			panic("Failed to remap eiu memory");
	}

	/* turn off all irqs by default */
	for (i = 0; i < 5; i++) {
		/* make sure all irqs are turned off by default */
		ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
		/* clear all possibly pending interrupts */
		ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
	}

	mips_cpu_irq_init();

	for (i = 2; i <= 6; i++)
		setup_irq(i, &cascade);

	if (cpu_has_vint) {
		pr_info("Setting up vectored interrupts\n");
		set_vi_handler(2, ltq_hw0_irqdispatch);
		set_vi_handler(3, ltq_hw1_irqdispatch);
		set_vi_handler(4, ltq_hw2_irqdispatch);
		set_vi_handler(5, ltq_hw3_irqdispatch);
		set_vi_handler(6, ltq_hw4_irqdispatch);
		set_vi_handler(7, ltq_hw5_irqdispatch);
	}

	irq_domain_add_linear(node, 6 * INT_NUM_IM_OFFSET,
		&irq_domain_ops, 0);

#if defined(CONFIG_MIPS_MT_SMP)
	if (cpu_has_vint) {
		pr_info("Setting up IPI vectored interrupts\n");
		set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
		set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
	}
	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
		&irq_resched);
	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
#endif

#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
		IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#else
	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
		IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
#endif

	/* tell oprofile which irq to use */
	cp0_perfcount_irq = LTQ_PERF_IRQ;
	return 0;
}

unsigned int __cpuinit get_c0_compare_int(void)
{
	return CP0_LEGACY_COMPARE_IRQ;
}

static struct of_device_id __initdata of_irq_ids[] = {
	{ .compatible = "lantiq,icu", .data = icu_of_init },
	{},
};

void __init arch_init_irq(void)
{
	of_irq_init(of_irq_ids);
}
Commit	Line	Data
171bb2f1 JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
	6	* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
	7	* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
	8	*/
	9
	10	#include <linux/interrupt.h>
	11	#include <linux/ioport.h>
3645da02 JC	12	#include <linux/sched.h>
	13	#include <linux/irqdomain.h>
	14	#include <linux/of_platform.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of_irq.h>
171bb2f1 JC	17
	18	#include <asm/bootinfo.h>
	19	#include <asm/irq_cpu.h>
	20
	21	#include <lantiq_soc.h>
	22	#include <irq.h>
	23
3645da02	24	/* register definitions - internal irqs */
171bb2f1 JC	25	#define LTQ_ICU_IM0_ISR 0x0000
	26	#define LTQ_ICU_IM0_IER 0x0008
	27	#define LTQ_ICU_IM0_IOSR 0x0010
	28	#define LTQ_ICU_IM0_IRSR 0x0018
	29	#define LTQ_ICU_IM0_IMR 0x0020
	30	#define LTQ_ICU_IM1_ISR 0x0028
	31	#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
	32
3645da02	33	/* register definitions - external irqs */
171bb2f1 JC	34	#define LTQ_EIU_EXIN_C 0x0000
	35	#define LTQ_EIU_EXIN_INIC 0x0004
	36	#define LTQ_EIU_EXIN_INEN 0x000C
	37
	38	/* irq numbers used by the external interrupt unit (EIU) */
	39	#define LTQ_EIU_IR0 (INT_NUM_IM4_IRL0 + 30)
	40	#define LTQ_EIU_IR1 (INT_NUM_IM3_IRL0 + 31)
	41	#define LTQ_EIU_IR2 (INT_NUM_IM1_IRL0 + 26)
	42	#define LTQ_EIU_IR3 INT_NUM_IM1_IRL0
	43	#define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1)
	44	#define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2)
	45	#define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30)
3645da02	46	#define XWAY_EXIN_COUNT 3
171bb2f1 JC	47	#define MAX_EIU 6
171bb2f1 JC	48
59c11579 JC	49	/* the performance counter */
	50	#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
	51
3645da02 JC	52	/*
3645da02 JC	53	* irqs generated by devices attached to the EBU need to be acked in
171bb2f1 JC	54	* a special manner
	55	*/
	56	#define LTQ_ICU_EBU_IRQ 22
	57
	58	#define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y))
	59	#define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x))
	60
	61	#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
	62	#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
	63
a8d096ef JC	64	/* our 2 ipi interrupts for VSMP */
	65	#define MIPS_CPU_IPI_RESCHED_IRQ 0
	66	#define MIPS_CPU_IPI_CALL_IRQ 1
	67
3645da02 JC	68	/* we have a cascade of 8 irqs */
	69	#define MIPS_CPU_IRQ_CASCADE 8
	70
a8d096ef JC	71	#if defined(CONFIG_MIPS_MT_SMP) \|\| defined(CONFIG_MIPS_MT_SMTC)
	72	int gic_present;
	73	#endif
	74
171bb2f1 JC	75	static unsigned short ltq_eiu_irq[MAX_EIU] = {
	76	LTQ_EIU_IR0,
	77	LTQ_EIU_IR1,
	78	LTQ_EIU_IR2,
	79	LTQ_EIU_IR3,
	80	LTQ_EIU_IR4,
	81	LTQ_EIU_IR5,
	82	};
	83
3645da02	84	static int exin_avail;
171bb2f1 JC	85	static void __iomem *ltq_icu_membase;
	86	static void __iomem *ltq_eiu_membase;
	87
	88	void ltq_disable_irq(struct irq_data *d)
	89	{
	90	u32 ier = LTQ_ICU_IM0_IER;
3645da02	91	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
171bb2f1	92
3645da02 JC	93	ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
	94	offset %= INT_NUM_IM_OFFSET;
	95	ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier);
171bb2f1 JC	96	}
	97
	98	void ltq_mask_and_ack_irq(struct irq_data *d)
	99	{
	100	u32 ier = LTQ_ICU_IM0_IER;
	101	u32 isr = LTQ_ICU_IM0_ISR;
3645da02	102	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
171bb2f1	103
3645da02 JC	104	ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
	105	isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
	106	offset %= INT_NUM_IM_OFFSET;
	107	ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier);
	108	ltq_icu_w32(BIT(offset), isr);
171bb2f1 JC	109	}
	110
	111	static void ltq_ack_irq(struct irq_data *d)
	112	{
	113	u32 isr = LTQ_ICU_IM0_ISR;
3645da02	114	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
171bb2f1	115
3645da02 JC	116	isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
	117	offset %= INT_NUM_IM_OFFSET;
	118	ltq_icu_w32(BIT(offset), isr);
171bb2f1 JC	119	}
	120
	121	void ltq_enable_irq(struct irq_data *d)
	122	{
	123	u32 ier = LTQ_ICU_IM0_IER;
3645da02	124	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
171bb2f1	125
3645da02 JC	126	ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
	127	offset %= INT_NUM_IM_OFFSET;
	128	ltq_icu_w32(ltq_icu_r32(ier) \| BIT(offset), ier);
171bb2f1 JC	129	}
	130
	131	static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
	132	{
	133	int i;
171bb2f1 JC	134
	135	ltq_enable_irq(d);
	136	for (i = 0; i < MAX_EIU; i++) {
3645da02	137	if (d->hwirq == ltq_eiu_irq[i]) {
171bb2f1 JC	138	/* low level - we should really handle set_type */
	139	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) \|
	140	(0x6 << (i * 4)), LTQ_EIU_EXIN_C);
	141	/* clear all pending */
3645da02	142	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i),
171bb2f1 JC	143	LTQ_EIU_EXIN_INIC);
171bb2f1 JC	144	/* enable */
3645da02	145	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) \| BIT(i),
171bb2f1 JC	146	LTQ_EIU_EXIN_INEN);
	147	break;
	148	}
	149	}
	150
	151	return 0;
	152	}
	153
	154	static void ltq_shutdown_eiu_irq(struct irq_data *d)
	155	{
	156	int i;
171bb2f1 JC	157
	158	ltq_disable_irq(d);
	159	for (i = 0; i < MAX_EIU; i++) {
3645da02	160	if (d->hwirq == ltq_eiu_irq[i]) {
171bb2f1	161	/* disable */
3645da02	162	ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
171bb2f1 JC	163	LTQ_EIU_EXIN_INEN);
	164	break;
	165	}
	166	}
	167	}
	168
	169	static struct irq_chip ltq_irq_type = {
	170	"icu",
	171	.irq_enable = ltq_enable_irq,
	172	.irq_disable = ltq_disable_irq,
	173	.irq_unmask = ltq_enable_irq,
	174	.irq_ack = ltq_ack_irq,
	175	.irq_mask = ltq_disable_irq,
	176	.irq_mask_ack = ltq_mask_and_ack_irq,
	177	};
	178
	179	static struct irq_chip ltq_eiu_type = {
	180	"eiu",
	181	.irq_startup = ltq_startup_eiu_irq,
	182	.irq_shutdown = ltq_shutdown_eiu_irq,
	183	.irq_enable = ltq_enable_irq,
	184	.irq_disable = ltq_disable_irq,
	185	.irq_unmask = ltq_enable_irq,
	186	.irq_ack = ltq_ack_irq,
	187	.irq_mask = ltq_disable_irq,
	188	.irq_mask_ack = ltq_mask_and_ack_irq,
	189	};
	190
	191	static void ltq_hw_irqdispatch(int module)
	192	{
	193	u32 irq;
	194
	195	irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET));
	196	if (irq == 0)
	197	return;
	198
3645da02 JC	199	/*
3645da02 JC	200	* silicon bug causes only the msb set to 1 to be valid. all
171bb2f1 JC	201	* other bits might be bogus
	202	*/
	203	irq = __fls(irq);
3645da02	204	do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
171bb2f1 JC	205
171bb2f1 JC	206	/* if this is a EBU irq, we need to ack it or get a deadlock */
3645da02	207	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
171bb2f1 JC	208	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) \| 0x10,
	209	LTQ_EBU_PCC_ISTAT);
	210	}
	211
	212	#define DEFINE_HWx_IRQDISPATCH(x) \
	213	static void ltq_hw ## x ## _irqdispatch(void) \
	214	{ \
	215	ltq_hw_irqdispatch(x); \
	216	}
	217	DEFINE_HWx_IRQDISPATCH(0)
	218	DEFINE_HWx_IRQDISPATCH(1)
	219	DEFINE_HWx_IRQDISPATCH(2)
	220	DEFINE_HWx_IRQDISPATCH(3)
	221	DEFINE_HWx_IRQDISPATCH(4)
	222
	223	static void ltq_hw5_irqdispatch(void)
	224	{
	225	do_IRQ(MIPS_CPU_TIMER_IRQ);
	226	}
	227
a8d096ef JC	228	#ifdef CONFIG_MIPS_MT_SMP
	229	void __init arch_init_ipiirq(int irq, struct irqaction *action)
	230	{
	231	setup_irq(irq, action);
	232	irq_set_handler(irq, handle_percpu_irq);
	233	}
	234
	235	static void ltq_sw0_irqdispatch(void)
	236	{
	237	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
	238	}
	239
	240	static void ltq_sw1_irqdispatch(void)
	241	{
	242	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
	243	}
	244	static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
	245	{
	246	scheduler_ipi();
	247	return IRQ_HANDLED;
	248	}
	249
	250	static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
	251	{
	252	smp_call_function_interrupt();
	253	return IRQ_HANDLED;
	254	}
	255
	256	static struct irqaction irq_resched = {
	257	.handler = ipi_resched_interrupt,
	258	.flags = IRQF_PERCPU,
	259	.name = "IPI_resched"
	260	};
	261
	262	static struct irqaction irq_call = {
	263	.handler = ipi_call_interrupt,
	264	.flags = IRQF_PERCPU,
	265	.name = "IPI_call"
	266	};
	267	#endif
	268
171bb2f1 JC	269	asmlinkage void plat_irq_dispatch(void)
	270	{
	271	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
	272	unsigned int i;
	273
	274	if (pending & CAUSEF_IP7) {
	275	do_IRQ(MIPS_CPU_TIMER_IRQ);
	276	goto out;
	277	} else {
	278	for (i = 0; i < 5; i++) {
	279	if (pending & (CAUSEF_IP2 << i)) {
	280	ltq_hw_irqdispatch(i);
	281	goto out;
	282	}
	283	}
	284	}
	285	pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
	286
	287	out:
	288	return;
	289	}
	290
3645da02 JC	291	static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
	292	{
	293	struct irq_chip *chip = &ltq_irq_type;
	294	int i;
	295
	296	for (i = 0; i < exin_avail; i++)
	297	if (hw == ltq_eiu_irq[i])
	298	chip = &ltq_eiu_type;
	299
	300	irq_set_chip_and_handler(hw, chip, handle_level_irq);
	301
	302	return 0;
	303	}
	304
	305	static const struct irq_domain_ops irq_domain_ops = {
	306	.xlate = irq_domain_xlate_onetwocell,
	307	.map = icu_map,
	308	};
	309
171bb2f1 JC	310	static struct irqaction cascade = {
171bb2f1 JC	311	.handler = no_action,
171bb2f1 JC	312	.name = "cascade",
	313	};
	314
3645da02	315	int __init icu_of_init(struct device_node node, struct device_node parent)
171bb2f1	316	{
3645da02 JC	317	struct device_node *eiu_node;
3645da02 JC	318	struct resource res;
171bb2f1 JC	319	int i;
171bb2f1 JC	320
3645da02 JC	321	if (of_address_to_resource(node, 0, &res))
3645da02 JC	322	panic("Failed to get icu memory range");
171bb2f1	323
3645da02 JC	324	if (request_mem_region(res.start, resource_size(&res), res.name) < 0)
3645da02 JC	325	pr_err("Failed to request icu memory");
171bb2f1	326
3645da02	327	ltq_icu_membase = ioremap_nocache(res.start, resource_size(&res));
171bb2f1	328	if (!ltq_icu_membase)
ab75dc02	329	panic("Failed to remap icu memory");
171bb2f1	330
3645da02 JC	331	/* the external interrupts are optional and xway only */
	332	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
	333	if (eiu_node && of_address_to_resource(eiu_node, 0, &res)) {
	334	/* find out how many external irq sources we have */
	335	const __be32 *count = of_get_property(node,
	336	"lantiq,count", NULL);
	337
	338	if (count)
	339	exin_avail = *count;
	340	if (exin_avail > MAX_EIU)
	341	exin_avail = MAX_EIU;
	342
	343	if (request_mem_region(res.start, resource_size(&res),
	344	res.name) < 0)
	345	pr_err("Failed to request eiu memory");
	346
	347	ltq_eiu_membase = ioremap_nocache(res.start,
	348	resource_size(&res));
	349	if (!ltq_eiu_membase)
	350	panic("Failed to remap eiu memory");
	351	}
171bb2f1	352
16f70b56 JC	353	/* turn off all irqs by default */
	354	for (i = 0; i < 5; i++) {
	355	/* make sure all irqs are turned off by default */
171bb2f1	356	ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
16f70b56 JC	357	/* clear all possibly pending interrupts */
	358	ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
	359	}
171bb2f1 JC	360
	361	mips_cpu_irq_init();
	362
	363	for (i = 2; i <= 6; i++)
	364	setup_irq(i, &cascade);
	365
	366	if (cpu_has_vint) {
	367	pr_info("Setting up vectored interrupts\n");
	368	set_vi_handler(2, ltq_hw0_irqdispatch);
	369	set_vi_handler(3, ltq_hw1_irqdispatch);
	370	set_vi_handler(4, ltq_hw2_irqdispatch);
	371	set_vi_handler(5, ltq_hw3_irqdispatch);
	372	set_vi_handler(6, ltq_hw4_irqdispatch);
	373	set_vi_handler(7, ltq_hw5_irqdispatch);
	374	}
	375
3645da02 JC	376	irq_domain_add_linear(node, 6 * INT_NUM_IM_OFFSET,
3645da02 JC	377	&irq_domain_ops, 0);
171bb2f1	378
a8d096ef JC	379	#if defined(CONFIG_MIPS_MT_SMP)
	380	if (cpu_has_vint) {
	381	pr_info("Setting up IPI vectored interrupts\n");
	382	set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
	383	set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
	384	}
	385	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
	386	&irq_resched);
	387	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
	388	#endif
	389
171bb2f1 JC	390	#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
	391	set_c0_status(IE_IRQ0 \| IE_IRQ1 \| IE_IRQ2 \|
	392	IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5);
	393	#else
	394	set_c0_status(IE_SW0 \| IE_SW1 \| IE_IRQ0 \| IE_IRQ1 \|
	395	IE_IRQ2 \| IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5);
	396	#endif
59c11579 JC	397
	398	/* tell oprofile which irq to use */
	399	cp0_perfcount_irq = LTQ_PERF_IRQ;
3645da02	400	return 0;
171bb2f1 JC	401	}
	402
	403	unsigned int __cpuinit get_c0_compare_int(void)
	404	{
	405	return CP0_LEGACY_COMPARE_IRQ;
	406	}
3645da02 JC	407
	408	static struct of_device_id __initdata of_irq_ids[] = {
	409	{ .compatible = "lantiq,icu", .data = icu_of_init },
	410	{},
	411	};
	412
	413	void __init arch_init_irq(void)
	414	{
	415	of_irq_init(of_irq_ids);
	416	}