[mirror_ubuntu-focal-kernel.git] / arch / mips / lib / dump_tlb.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Dump R4x00 TLB for debugging purposes.
 *
 * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
 * Copyright (C) 1999 by Silicon Graphics, Inc.
 */
#include <linux/kernel.h>
#include <linux/mm.h>

#include <asm/hazards.h>
#include <asm/mipsregs.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/tlbdebug.h>

void dump_tlb_regs(void)
{
	const int field = 2 * sizeof(unsigned long);

	pr_info("Index    : %0x\n", read_c0_index());
	pr_info("PageMask : %0x\n", read_c0_pagemask());
	if (cpu_has_guestid)
		pr_info("GuestCtl1: %0x\n", read_c0_guestctl1());
	pr_info("EntryHi  : %0*lx\n", field, read_c0_entryhi());
	pr_info("EntryLo0 : %0*lx\n", field, read_c0_entrylo0());
	pr_info("EntryLo1 : %0*lx\n", field, read_c0_entrylo1());
	pr_info("Wired    : %0x\n", read_c0_wired());
	switch (current_cpu_type()) {
	case CPU_R10000:
	case CPU_R12000:
	case CPU_R14000:
	case CPU_R16000:
		pr_info("FrameMask: %0x\n", read_c0_framemask());
		break;
	}
	if (cpu_has_small_pages || cpu_has_rixi || cpu_has_xpa)
		pr_info("PageGrain: %0x\n", read_c0_pagegrain());
	if (cpu_has_htw) {
		pr_info("PWField  : %0*lx\n", field, read_c0_pwfield());
		pr_info("PWSize   : %0*lx\n", field, read_c0_pwsize());
		pr_info("PWCtl    : %0x\n", read_c0_pwctl());
	}
}

static inline const char *msk2str(unsigned int mask)
{
	switch (mask) {
	case PM_4K:	return "4kb";
	case PM_16K:	return "16kb";
	case PM_64K:	return "64kb";
	case PM_256K:	return "256kb";
#ifdef CONFIG_CPU_CAVIUM_OCTEON
	case PM_8K:	return "8kb";
	case PM_32K:	return "32kb";
	case PM_128K:	return "128kb";
	case PM_512K:	return "512kb";
	case PM_2M:	return "2Mb";
	case PM_8M:	return "8Mb";
	case PM_32M:	return "32Mb";
#endif
#ifndef CONFIG_CPU_VR41XX
	case PM_1M:	return "1Mb";
	case PM_4M:	return "4Mb";
	case PM_16M:	return "16Mb";
	case PM_64M:	return "64Mb";
	case PM_256M:	return "256Mb";
	case PM_1G:	return "1Gb";
#endif
	}
	return "";
}

static void dump_tlb(int first, int last)
{
	unsigned long s_entryhi, entryhi, asid;
	unsigned long long entrylo0, entrylo1, pa;
	unsigned int s_index, s_pagemask, s_guestctl1 = 0;
	unsigned int pagemask, guestctl1 = 0, c0, c1, i;
	unsigned long asidmask = cpu_asid_mask(&current_cpu_data);
	int asidwidth = DIV_ROUND_UP(ilog2(asidmask) + 1, 4);
#ifdef CONFIG_32BIT
	bool xpa = cpu_has_xpa && (read_c0_pagegrain() & PG_ELPA);
	int pwidth = xpa ? 11 : 8;
	int vwidth = 8;
#else
	bool xpa = false;
	int pwidth = 11;
	int vwidth = 11;
#endif

	s_pagemask = read_c0_pagemask();
	s_entryhi = read_c0_entryhi();
	s_index = read_c0_index();
	asid = s_entryhi & asidmask;
	if (cpu_has_guestid)
		s_guestctl1 = read_c0_guestctl1();

	for (i = first; i <= last; i++) {
		write_c0_index(i);
		mtc0_tlbr_hazard();
		tlb_read();
		tlb_read_hazard();
		pagemask = read_c0_pagemask();
		entryhi	 = read_c0_entryhi();
		entrylo0 = read_c0_entrylo0();
		entrylo1 = read_c0_entrylo1();
		if (cpu_has_guestid)
			guestctl1 = read_c0_guestctl1();

		/* EHINV bit marks entire entry as invalid */
		if (cpu_has_tlbinv && entryhi & MIPS_ENTRYHI_EHINV)
			continue;
		/*
		 * Prior to tlbinv, unused entries have a virtual address of
		 * CKSEG0.
		 */
		if ((entryhi & ~0x1ffffUL) == CKSEG0)
			continue;
		/*
		 * ASID takes effect in absence of G (global) bit.
		 * We check both G bits, even though architecturally they should
		 * match one another, because some revisions of the SB1 core may
		 * leave only a single G bit set after a machine check exception
		 * due to duplicate TLB entry.
		 */
		if (!((entrylo0 | entrylo1) & ENTRYLO_G) &&
		    (entryhi & asidmask) != asid)
			continue;

		/*
		 * Only print entries in use
		 */
		printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));

		c0 = (entrylo0 & ENTRYLO_C) >> ENTRYLO_C_SHIFT;
		c1 = (entrylo1 & ENTRYLO_C) >> ENTRYLO_C_SHIFT;

		pr_cont("va=%0*lx asid=%0*lx",
			vwidth, (entryhi & ~0x1fffUL),
			asidwidth, entryhi & asidmask);
		if (cpu_has_guestid)
			pr_cont(" gid=%02lx",
				(guestctl1 & MIPS_GCTL1_RID)
					>> MIPS_GCTL1_RID_SHIFT);
		/* RI/XI are in awkward places, so mask them off separately */
		pa = entrylo0 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
		if (xpa)
			pa |= (unsigned long long)readx_c0_entrylo0() << 30;
		pa = (pa << 6) & PAGE_MASK;
		pr_cont("\n\t[");
		if (cpu_has_rixi)
			pr_cont("ri=%d xi=%d ",
				(entrylo0 & MIPS_ENTRYLO_RI) ? 1 : 0,
				(entrylo0 & MIPS_ENTRYLO_XI) ? 1 : 0);
		pr_cont("pa=%0*llx c=%d d=%d v=%d g=%d] [",
			pwidth, pa, c0,
			(entrylo0 & ENTRYLO_D) ? 1 : 0,
			(entrylo0 & ENTRYLO_V) ? 1 : 0,
			(entrylo0 & ENTRYLO_G) ? 1 : 0);
		/* RI/XI are in awkward places, so mask them off separately */
		pa = entrylo1 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
		if (xpa)
			pa |= (unsigned long long)readx_c0_entrylo1() << 30;
		pa = (pa << 6) & PAGE_MASK;
		if (cpu_has_rixi)
			pr_cont("ri=%d xi=%d ",
				(entrylo1 & MIPS_ENTRYLO_RI) ? 1 : 0,
				(entrylo1 & MIPS_ENTRYLO_XI) ? 1 : 0);
		pr_cont("pa=%0*llx c=%d d=%d v=%d g=%d]\n",
			pwidth, pa, c1,
			(entrylo1 & ENTRYLO_D) ? 1 : 0,
			(entrylo1 & ENTRYLO_V) ? 1 : 0,
			(entrylo1 & ENTRYLO_G) ? 1 : 0);
	}
	printk("\n");

	write_c0_entryhi(s_entryhi);
	write_c0_index(s_index);
	write_c0_pagemask(s_pagemask);
	if (cpu_has_guestid)
		write_c0_guestctl1(s_guestctl1);
}

void dump_tlb_all(void)
{
	dump_tlb(0, current_cpu_data.tlbsize - 1);
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
	3	* Dump R4x00 TLB for debugging purposes.
	4	*
	5	* Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
	6	* Copyright (C) 1999 by Silicon Graphics, Inc.
	7	*/
1da177e4 LT	8	#include <linux/kernel.h>
1da177e4 LT	9	#include <linux/mm.h>
1da177e4	10
137877e4	11	#include <asm/hazards.h>
1da177e4 LT	12	#include <asm/mipsregs.h>
	13	#include <asm/page.h>
	14	#include <asm/pgtable.h>
40df3831	15	#include <asm/tlbdebug.h>
1da177e4	16
3c865dd9 JH	17	void dump_tlb_regs(void)
	18	{
	19	const int field = 2 * sizeof(unsigned long);
	20
	21	pr_info("Index : %0x\n", read_c0_index());
	22	pr_info("PageMask : %0x\n", read_c0_pagemask());
4b62fad5 JH	23	if (cpu_has_guestid)
4b62fad5 JH	24	pr_info("GuestCtl1: %0x\n", read_c0_guestctl1());
3c865dd9 JH	25	pr_info("EntryHi : %0*lx\n", field, read_c0_entryhi());
	26	pr_info("EntryLo0 : %0*lx\n", field, read_c0_entrylo0());
	27	pr_info("EntryLo1 : %0*lx\n", field, read_c0_entrylo1());
	28	pr_info("Wired : %0x\n", read_c0_wired());
9bd860ca JH	29	switch (current_cpu_type()) {
	30	case CPU_R10000:
	31	case CPU_R12000:
	32	case CPU_R14000:
	33	case CPU_R16000:
	34	pr_info("FrameMask: %0x\n", read_c0_framemask());
	35	break;
	36	}
5d3c3c7d JH	37	if (cpu_has_small_pages \|\| cpu_has_rixi \|\| cpu_has_xpa)
5d3c3c7d JH	38	pr_info("PageGrain: %0x\n", read_c0_pagegrain());
3c865dd9 JH	39	if (cpu_has_htw) {
	40	pr_info("PWField : %0*lx\n", field, read_c0_pwfield());
	41	pr_info("PWSize : %0*lx\n", field, read_c0_pwsize());
	42	pr_info("PWCtl : %0x\n", read_c0_pwctl());
	43	}
	44	}
	45
1da177e4 LT	46	static inline const char *msk2str(unsigned int mask)
	47	{
	48	switch (mask) {
	49	case PM_4K: return "4kb";
	50	case PM_16K: return "16kb";
	51	case PM_64K: return "64kb";
	52	case PM_256K: return "256kb";
c52399be RB	53	#ifdef CONFIG_CPU_CAVIUM_OCTEON
	54	case PM_8K: return "8kb";
	55	case PM_32K: return "32kb";
	56	case PM_128K: return "128kb";
	57	case PM_512K: return "512kb";
	58	case PM_2M: return "2Mb";
	59	case PM_8M: return "8Mb";
	60	case PM_32M: return "32Mb";
	61	#endif
1da177e4 LT	62	#ifndef CONFIG_CPU_VR41XX
	63	case PM_1M: return "1Mb";
	64	case PM_4M: return "4Mb";
	65	case PM_16M: return "16Mb";
	66	case PM_64M: return "64Mb";
	67	case PM_256M: return "256Mb";
542c1020	68	case PM_1G: return "1Gb";
1da177e4 LT	69	#endif
1da177e4 LT	70	}
4becef1d	71	return "";
1da177e4 LT	72	}
1da177e4 LT	73
69ed25b8	74	static void dump_tlb(int first, int last)
1da177e4	75	{
4becef1d	76	unsigned long s_entryhi, entryhi, asid;
c2bc435e	77	unsigned long long entrylo0, entrylo1, pa;
382208dc JH	78	unsigned int s_index, s_pagemask, s_guestctl1 = 0;
382208dc JH	79	unsigned int pagemask, guestctl1 = 0, c0, c1, i;
4edf00a4 PB	80	unsigned long asidmask = cpu_asid_mask(&current_cpu_data);
4edf00a4 PB	81	int asidwidth = DIV_ROUND_UP(ilog2(asidmask) + 1, 4);
d1ce483e	82	#ifdef CONFIG_32BIT
24ca1d98 JH	83	bool xpa = cpu_has_xpa && (read_c0_pagegrain() & PG_ELPA);
	84	int pwidth = xpa ? 11 : 8;
	85	int vwidth = 8;
d1ce483e	86	#else
24ca1d98 JH	87	bool xpa = false;
	88	int pwidth = 11;
	89	int vwidth = 11;
d1ce483e	90	#endif
1da177e4	91
01422ff4	92	s_pagemask = read_c0_pagemask();
1da177e4 LT	93	s_entryhi = read_c0_entryhi();
1da177e4 LT	94	s_index = read_c0_index();
4edf00a4	95	asid = s_entryhi & asidmask;
382208dc JH	96	if (cpu_has_guestid)
382208dc JH	97	s_guestctl1 = read_c0_guestctl1();
1da177e4 LT	98
	99	for (i = first; i <= last; i++) {
	100	write_c0_index(i);
137877e4	101	mtc0_tlbr_hazard();
1da177e4	102	tlb_read();
137877e4	103	tlb_read_hazard();
1da177e4	104	pagemask = read_c0_pagemask();
70342287	105	entryhi = read_c0_entryhi();
1da177e4 LT	106	entrylo0 = read_c0_entrylo0();
1da177e4 LT	107	entrylo1 = read_c0_entrylo1();
382208dc JH	108	if (cpu_has_guestid)
382208dc JH	109	guestctl1 = read_c0_guestctl1();
1da177e4	110
decebccd JH	111	/* EHINV bit marks entire entry as invalid */
	112	if (cpu_has_tlbinv && entryhi & MIPS_ENTRYHI_EHINV)
	113	continue;
d1ce483e JH	114	/*
	115	* Prior to tlbinv, unused entries have a virtual address of
	116	* CKSEG0.
	117	*/
	118	if ((entryhi & ~0x1ffffUL) == CKSEG0)
	119	continue;
48269c78 JH	120	/*
	121	* ASID takes effect in absence of G (global) bit.
	122	* We check both G bits, even though architecturally they should
	123	* match one another, because some revisions of the SB1 core may
	124	* leave only a single G bit set after a machine check exception
	125	* due to duplicate TLB entry.
	126	*/
bae637a2	127	if (!((entrylo0 \| entrylo1) & ENTRYLO_G) &&
4edf00a4	128	(entryhi & asidmask) != asid)
d1ce483e JH	129	continue;
	130
	131	/*
	132	* Only print entries in use
	133	*/
	134	printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
1da177e4	135
bae637a2 JH	136	c0 = (entrylo0 & ENTRYLO_C) >> ENTRYLO_C_SHIFT;
bae637a2 JH	137	c1 = (entrylo1 & ENTRYLO_C) >> ENTRYLO_C_SHIFT;
1da177e4	138
8a98495c JH	139	pr_cont("va=%0lx asid=%0lx",
	140	vwidth, (entryhi & ~0x1fffUL),
	141	asidwidth, entryhi & asidmask);
382208dc	142	if (cpu_has_guestid)
8a98495c JH	143	pr_cont(" gid=%02lx",
8a98495c JH	144	(guestctl1 & MIPS_GCTL1_RID)
382208dc	145	>> MIPS_GCTL1_RID_SHIFT);
c2bc435e JH	146	/* RI/XI are in awkward places, so mask them off separately */
c2bc435e JH	147	pa = entrylo0 & ~(MIPS_ENTRYLO_RI \| MIPS_ENTRYLO_XI);
24ca1d98 JH	148	if (xpa)
24ca1d98 JH	149	pa \|= (unsigned long long)readx_c0_entrylo0() << 30;
c2bc435e	150	pa = (pa << 6) & PAGE_MASK;
8a98495c	151	pr_cont("\n\t[");
c2bc435e	152	if (cpu_has_rixi)
8a98495c JH	153	pr_cont("ri=%d xi=%d ",
	154	(entrylo0 & MIPS_ENTRYLO_RI) ? 1 : 0,
	155	(entrylo0 & MIPS_ENTRYLO_XI) ? 1 : 0);
	156	pr_cont("pa=%0*llx c=%d d=%d v=%d g=%d] [",
	157	pwidth, pa, c0,
	158	(entrylo0 & ENTRYLO_D) ? 1 : 0,
	159	(entrylo0 & ENTRYLO_V) ? 1 : 0,
	160	(entrylo0 & ENTRYLO_G) ? 1 : 0);
c2bc435e JH	161	/* RI/XI are in awkward places, so mask them off separately */
c2bc435e JH	162	pa = entrylo1 & ~(MIPS_ENTRYLO_RI \| MIPS_ENTRYLO_XI);
24ca1d98 JH	163	if (xpa)
24ca1d98 JH	164	pa \|= (unsigned long long)readx_c0_entrylo1() << 30;
c2bc435e JH	165	pa = (pa << 6) & PAGE_MASK;
c2bc435e JH	166	if (cpu_has_rixi)
8a98495c JH	167	pr_cont("ri=%d xi=%d ",
	168	(entrylo1 & MIPS_ENTRYLO_RI) ? 1 : 0,
	169	(entrylo1 & MIPS_ENTRYLO_XI) ? 1 : 0);
	170	pr_cont("pa=%0*llx c=%d d=%d v=%d g=%d]\n",
	171	pwidth, pa, c1,
	172	(entrylo1 & ENTRYLO_D) ? 1 : 0,
	173	(entrylo1 & ENTRYLO_V) ? 1 : 0,
	174	(entrylo1 & ENTRYLO_G) ? 1 : 0);
1da177e4 LT	175	}
	176	printk("\n");
	177
	178	write_c0_entryhi(s_entryhi);
	179	write_c0_index(s_index);
01422ff4	180	write_c0_pagemask(s_pagemask);
382208dc JH	181	if (cpu_has_guestid)
382208dc JH	182	write_c0_guestctl1(s_guestctl1);
1da177e4 LT	183	}
	184
	185	void dump_tlb_all(void)
	186	{
	187	dump_tlb(0, current_cpu_data.tlbsize - 1);
	188	}