[mirror_ubuntu-artful-kernel.git] / arch / mips / lib / dump_tlb.c

/*
 * Dump R4x00 TLB for debugging purposes.
 *
 * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
 * Copyright (C) 1999 by Silicon Graphics, Inc.
 */
#include <linux/kernel.h>
#include <linux/mm.h>

#include <asm/mipsregs.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/tlbdebug.h>

static inline const char *msk2str(unsigned int mask)
{
	switch (mask) {
	case PM_4K:	return "4kb";
	case PM_16K:	return "16kb";
	case PM_64K:	return "64kb";
	case PM_256K:	return "256kb";
#ifdef CONFIG_CPU_CAVIUM_OCTEON
	case PM_8K:	return "8kb";
	case PM_32K:	return "32kb";
	case PM_128K:	return "128kb";
	case PM_512K:	return "512kb";
	case PM_2M:	return "2Mb";
	case PM_8M:	return "8Mb";
	case PM_32M:	return "32Mb";
#endif
#ifndef CONFIG_CPU_VR41XX
	case PM_1M:	return "1Mb";
	case PM_4M:	return "4Mb";
	case PM_16M:	return "16Mb";
	case PM_64M:	return "64Mb";
	case PM_256M:	return "256Mb";
	case PM_1G:	return "1Gb";
#endif
	}
	return "";
}

#define BARRIER()					\
	__asm__ __volatile__(				\
		".set\tnoreorder\n\t"			\
		"nop;nop;nop;nop;nop;nop;nop\n\t"	\
		".set\treorder");

static void dump_tlb(int first, int last)
{
	unsigned long s_entryhi, entryhi, asid;
	unsigned long long entrylo0, entrylo1;
	unsigned int s_index, s_pagemask, pagemask, c0, c1, i;

	s_pagemask = read_c0_pagemask();
	s_entryhi = read_c0_entryhi();
	s_index = read_c0_index();
	asid = s_entryhi & 0xff;

	for (i = first; i <= last; i++) {
		write_c0_index(i);
		BARRIER();
		tlb_read();
		BARRIER();
		pagemask = read_c0_pagemask();
		entryhi  = read_c0_entryhi();
		entrylo0 = read_c0_entrylo0();
		entrylo1 = read_c0_entrylo1();

		/* Unused entries have a virtual address of CKSEG0.  */
		if ((entryhi & ~0x1ffffUL) != CKSEG0
		    && (entryhi & 0xff) == asid) {
#ifdef CONFIG_32BIT
			int width = 8;
#else
			int width = 11;
#endif
			/*
			 * Only print entries in use
			 */
			printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));

			c0 = (entrylo0 >> 3) & 7;
			c1 = (entrylo1 >> 3) & 7;

			printk("va=%0*lx asid=%02lx\n",
			       width, (entryhi & ~0x1fffUL),
			       entryhi & 0xff);
			printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
			       width,
			       (entrylo0 << 6) & PAGE_MASK, c0,
			       (entrylo0 & 4) ? 1 : 0,
			       (entrylo0 & 2) ? 1 : 0,
			       (entrylo0 & 1) ? 1 : 0);
			printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
			       width,
			       (entrylo1 << 6) & PAGE_MASK, c1,
			       (entrylo1 & 4) ? 1 : 0,
			       (entrylo1 & 2) ? 1 : 0,
			       (entrylo1 & 1) ? 1 : 0);
		}
	}
	printk("\n");

	write_c0_entryhi(s_entryhi);
	write_c0_index(s_index);
	write_c0_pagemask(s_pagemask);
}

void dump_tlb_all(void)
{
	dump_tlb(0, current_cpu_data.tlbsize - 1);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Dump R4x00 TLB for debugging purposes.
	3	*
	4	* Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
	5	* Copyright (C) 1999 by Silicon Graphics, Inc.
	6	*/
1da177e4 LT	7	#include <linux/kernel.h>
1da177e4 LT	8	#include <linux/mm.h>
1da177e4	9
1da177e4 LT	10	#include <asm/mipsregs.h>
	11	#include <asm/page.h>
	12	#include <asm/pgtable.h>
40df3831	13	#include <asm/tlbdebug.h>
1da177e4 LT	14
	15	static inline const char *msk2str(unsigned int mask)
	16	{
	17	switch (mask) {
	18	case PM_4K: return "4kb";
	19	case PM_16K: return "16kb";
	20	case PM_64K: return "64kb";
	21	case PM_256K: return "256kb";
c52399be RB	22	#ifdef CONFIG_CPU_CAVIUM_OCTEON
	23	case PM_8K: return "8kb";
	24	case PM_32K: return "32kb";
	25	case PM_128K: return "128kb";
	26	case PM_512K: return "512kb";
	27	case PM_2M: return "2Mb";
	28	case PM_8M: return "8Mb";
	29	case PM_32M: return "32Mb";
	30	#endif
1da177e4 LT	31	#ifndef CONFIG_CPU_VR41XX
	32	case PM_1M: return "1Mb";
	33	case PM_4M: return "4Mb";
	34	case PM_16M: return "16Mb";
	35	case PM_64M: return "64Mb";
	36	case PM_256M: return "256Mb";
542c1020	37	case PM_1G: return "1Gb";
1da177e4 LT	38	#endif
1da177e4 LT	39	}
4becef1d	40	return "";
1da177e4 LT	41	}
	42
	43	#define BARRIER() \
	44	__asm__ __volatile__( \
	45	".set\tnoreorder\n\t" \
	46	"nop;nop;nop;nop;nop;nop;nop\n\t" \
	47	".set\treorder");
	48
69ed25b8	49	static void dump_tlb(int first, int last)
1da177e4	50	{
4becef1d AN	51	unsigned long s_entryhi, entryhi, asid;
4becef1d AN	52	unsigned long long entrylo0, entrylo1;
01422ff4	53	unsigned int s_index, s_pagemask, pagemask, c0, c1, i;
1da177e4	54
01422ff4	55	s_pagemask = read_c0_pagemask();
1da177e4 LT	56	s_entryhi = read_c0_entryhi();
	57	s_index = read_c0_index();
	58	asid = s_entryhi & 0xff;
	59
	60	for (i = first; i <= last; i++) {
	61	write_c0_index(i);
	62	BARRIER();
	63	tlb_read();
	64	BARRIER();
	65	pagemask = read_c0_pagemask();
	66	entryhi = read_c0_entryhi();
	67	entrylo0 = read_c0_entrylo0();
	68	entrylo1 = read_c0_entrylo1();
	69
	70	/* Unused entries have a virtual address of CKSEG0. */
	71	if ((entryhi & ~0x1ffffUL) != CKSEG0
	72	&& (entryhi & 0xff) == asid) {
4becef1d AN	73	#ifdef CONFIG_32BIT
	74	int width = 8;
	75	#else
	76	int width = 11;
	77	#endif
1da177e4 LT	78	/*
	79	* Only print entries in use
	80	*/
	81	printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
	82
	83	c0 = (entrylo0 >> 3) & 7;
	84	c1 = (entrylo1 >> 3) & 7;
	85
4becef1d AN	86	printk("va=%0*lx asid=%02lx\n",
4becef1d AN	87	width, (entryhi & ~0x1fffUL),
1da177e4	88	entryhi & 0xff);
4becef1d AN	89	printk("\t[pa=%0*llx c=%d d=%d v=%d g=%d] ",
4becef1d AN	90	width,
1da177e4 LT	91	(entrylo0 << 6) & PAGE_MASK, c0,
	92	(entrylo0 & 4) ? 1 : 0,
	93	(entrylo0 & 2) ? 1 : 0,
4becef1d AN	94	(entrylo0 & 1) ? 1 : 0);
	95	printk("[pa=%0*llx c=%d d=%d v=%d g=%d]\n",
	96	width,
1da177e4 LT	97	(entrylo1 << 6) & PAGE_MASK, c1,
	98	(entrylo1 & 4) ? 1 : 0,
	99	(entrylo1 & 2) ? 1 : 0,
4becef1d	100	(entrylo1 & 1) ? 1 : 0);
1da177e4 LT	101	}
	102	}
	103	printk("\n");
	104
	105	write_c0_entryhi(s_entryhi);
	106	write_c0_index(s_index);
01422ff4	107	write_c0_pagemask(s_pagemask);
1da177e4 LT	108	}
	109
	110	void dump_tlb_all(void)
	111	{
	112	dump_tlb(0, current_cpu_data.tlbsize - 1);
	113	}