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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Dump R4x00 TLB for debugging purposes. | |
3 | * | |
4 | * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle. | |
5 | * Copyright (C) 1999 by Silicon Graphics, Inc. | |
6 | */ | |
1da177e4 LT |
7 | #include <linux/kernel.h> |
8 | #include <linux/mm.h> | |
1da177e4 | 9 | |
137877e4 | 10 | #include <asm/hazards.h> |
1da177e4 LT |
11 | #include <asm/mipsregs.h> |
12 | #include <asm/page.h> | |
13 | #include <asm/pgtable.h> | |
40df3831 | 14 | #include <asm/tlbdebug.h> |
1da177e4 | 15 | |
3c865dd9 JH |
16 | void dump_tlb_regs(void) |
17 | { | |
18 | const int field = 2 * sizeof(unsigned long); | |
19 | ||
20 | pr_info("Index : %0x\n", read_c0_index()); | |
21 | pr_info("PageMask : %0x\n", read_c0_pagemask()); | |
22 | pr_info("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
23 | pr_info("EntryLo0 : %0*lx\n", field, read_c0_entrylo0()); | |
24 | pr_info("EntryLo1 : %0*lx\n", field, read_c0_entrylo1()); | |
25 | pr_info("Wired : %0x\n", read_c0_wired()); | |
9bd860ca JH |
26 | switch (current_cpu_type()) { |
27 | case CPU_R10000: | |
28 | case CPU_R12000: | |
29 | case CPU_R14000: | |
30 | case CPU_R16000: | |
31 | pr_info("FrameMask: %0x\n", read_c0_framemask()); | |
32 | break; | |
33 | } | |
5d3c3c7d JH |
34 | if (cpu_has_small_pages || cpu_has_rixi || cpu_has_xpa) |
35 | pr_info("PageGrain: %0x\n", read_c0_pagegrain()); | |
3c865dd9 JH |
36 | if (cpu_has_htw) { |
37 | pr_info("PWField : %0*lx\n", field, read_c0_pwfield()); | |
38 | pr_info("PWSize : %0*lx\n", field, read_c0_pwsize()); | |
39 | pr_info("PWCtl : %0x\n", read_c0_pwctl()); | |
40 | } | |
41 | } | |
42 | ||
1da177e4 LT |
43 | static inline const char *msk2str(unsigned int mask) |
44 | { | |
45 | switch (mask) { | |
46 | case PM_4K: return "4kb"; | |
47 | case PM_16K: return "16kb"; | |
48 | case PM_64K: return "64kb"; | |
49 | case PM_256K: return "256kb"; | |
c52399be RB |
50 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
51 | case PM_8K: return "8kb"; | |
52 | case PM_32K: return "32kb"; | |
53 | case PM_128K: return "128kb"; | |
54 | case PM_512K: return "512kb"; | |
55 | case PM_2M: return "2Mb"; | |
56 | case PM_8M: return "8Mb"; | |
57 | case PM_32M: return "32Mb"; | |
58 | #endif | |
1da177e4 LT |
59 | #ifndef CONFIG_CPU_VR41XX |
60 | case PM_1M: return "1Mb"; | |
61 | case PM_4M: return "4Mb"; | |
62 | case PM_16M: return "16Mb"; | |
63 | case PM_64M: return "64Mb"; | |
64 | case PM_256M: return "256Mb"; | |
542c1020 | 65 | case PM_1G: return "1Gb"; |
1da177e4 LT |
66 | #endif |
67 | } | |
4becef1d | 68 | return ""; |
1da177e4 LT |
69 | } |
70 | ||
69ed25b8 | 71 | static void dump_tlb(int first, int last) |
1da177e4 | 72 | { |
4becef1d | 73 | unsigned long s_entryhi, entryhi, asid; |
c2bc435e | 74 | unsigned long long entrylo0, entrylo1, pa; |
01422ff4 | 75 | unsigned int s_index, s_pagemask, pagemask, c0, c1, i; |
4edf00a4 PB |
76 | unsigned long asidmask = cpu_asid_mask(¤t_cpu_data); |
77 | int asidwidth = DIV_ROUND_UP(ilog2(asidmask) + 1, 4); | |
d1ce483e | 78 | #ifdef CONFIG_32BIT |
24ca1d98 JH |
79 | bool xpa = cpu_has_xpa && (read_c0_pagegrain() & PG_ELPA); |
80 | int pwidth = xpa ? 11 : 8; | |
81 | int vwidth = 8; | |
d1ce483e | 82 | #else |
24ca1d98 JH |
83 | bool xpa = false; |
84 | int pwidth = 11; | |
85 | int vwidth = 11; | |
d1ce483e | 86 | #endif |
1da177e4 | 87 | |
01422ff4 | 88 | s_pagemask = read_c0_pagemask(); |
1da177e4 LT |
89 | s_entryhi = read_c0_entryhi(); |
90 | s_index = read_c0_index(); | |
4edf00a4 | 91 | asid = s_entryhi & asidmask; |
1da177e4 LT |
92 | |
93 | for (i = first; i <= last; i++) { | |
94 | write_c0_index(i); | |
137877e4 | 95 | mtc0_tlbr_hazard(); |
1da177e4 | 96 | tlb_read(); |
137877e4 | 97 | tlb_read_hazard(); |
1da177e4 | 98 | pagemask = read_c0_pagemask(); |
70342287 | 99 | entryhi = read_c0_entryhi(); |
1da177e4 LT |
100 | entrylo0 = read_c0_entrylo0(); |
101 | entrylo1 = read_c0_entrylo1(); | |
102 | ||
decebccd JH |
103 | /* EHINV bit marks entire entry as invalid */ |
104 | if (cpu_has_tlbinv && entryhi & MIPS_ENTRYHI_EHINV) | |
105 | continue; | |
d1ce483e JH |
106 | /* |
107 | * Prior to tlbinv, unused entries have a virtual address of | |
108 | * CKSEG0. | |
109 | */ | |
110 | if ((entryhi & ~0x1ffffUL) == CKSEG0) | |
111 | continue; | |
48269c78 JH |
112 | /* |
113 | * ASID takes effect in absence of G (global) bit. | |
114 | * We check both G bits, even though architecturally they should | |
115 | * match one another, because some revisions of the SB1 core may | |
116 | * leave only a single G bit set after a machine check exception | |
117 | * due to duplicate TLB entry. | |
118 | */ | |
bae637a2 | 119 | if (!((entrylo0 | entrylo1) & ENTRYLO_G) && |
4edf00a4 | 120 | (entryhi & asidmask) != asid) |
d1ce483e JH |
121 | continue; |
122 | ||
123 | /* | |
124 | * Only print entries in use | |
125 | */ | |
126 | printk("Index: %2d pgmask=%s ", i, msk2str(pagemask)); | |
1da177e4 | 127 | |
bae637a2 JH |
128 | c0 = (entrylo0 & ENTRYLO_C) >> ENTRYLO_C_SHIFT; |
129 | c1 = (entrylo1 & ENTRYLO_C) >> ENTRYLO_C_SHIFT; | |
1da177e4 | 130 | |
4edf00a4 | 131 | printk("va=%0*lx asid=%0*lx\n", |
24ca1d98 | 132 | vwidth, (entryhi & ~0x1fffUL), |
4edf00a4 | 133 | asidwidth, entryhi & asidmask); |
c2bc435e JH |
134 | /* RI/XI are in awkward places, so mask them off separately */ |
135 | pa = entrylo0 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); | |
24ca1d98 JH |
136 | if (xpa) |
137 | pa |= (unsigned long long)readx_c0_entrylo0() << 30; | |
c2bc435e JH |
138 | pa = (pa << 6) & PAGE_MASK; |
139 | printk("\t["); | |
140 | if (cpu_has_rixi) | |
141 | printk("ri=%d xi=%d ", | |
142 | (entrylo0 & MIPS_ENTRYLO_RI) ? 1 : 0, | |
143 | (entrylo0 & MIPS_ENTRYLO_XI) ? 1 : 0); | |
144 | printk("pa=%0*llx c=%d d=%d v=%d g=%d] [", | |
24ca1d98 | 145 | pwidth, pa, c0, |
bae637a2 JH |
146 | (entrylo0 & ENTRYLO_D) ? 1 : 0, |
147 | (entrylo0 & ENTRYLO_V) ? 1 : 0, | |
148 | (entrylo0 & ENTRYLO_G) ? 1 : 0); | |
c2bc435e JH |
149 | /* RI/XI are in awkward places, so mask them off separately */ |
150 | pa = entrylo1 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); | |
24ca1d98 JH |
151 | if (xpa) |
152 | pa |= (unsigned long long)readx_c0_entrylo1() << 30; | |
c2bc435e JH |
153 | pa = (pa << 6) & PAGE_MASK; |
154 | if (cpu_has_rixi) | |
155 | printk("ri=%d xi=%d ", | |
156 | (entrylo1 & MIPS_ENTRYLO_RI) ? 1 : 0, | |
157 | (entrylo1 & MIPS_ENTRYLO_XI) ? 1 : 0); | |
158 | printk("pa=%0*llx c=%d d=%d v=%d g=%d]\n", | |
24ca1d98 | 159 | pwidth, pa, c1, |
bae637a2 JH |
160 | (entrylo1 & ENTRYLO_D) ? 1 : 0, |
161 | (entrylo1 & ENTRYLO_V) ? 1 : 0, | |
162 | (entrylo1 & ENTRYLO_G) ? 1 : 0); | |
1da177e4 LT |
163 | } |
164 | printk("\n"); | |
165 | ||
166 | write_c0_entryhi(s_entryhi); | |
167 | write_c0_index(s_index); | |
01422ff4 | 168 | write_c0_pagemask(s_pagemask); |
1da177e4 LT |
169 | } |
170 | ||
171 | void dump_tlb_all(void) | |
172 | { | |
173 | dump_tlb(0, current_cpu_data.tlbsize - 1); | |
174 | } |