[mirror_ubuntu-artful-kernel.git] / arch / mips / lib / memset.S

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1998, 1999, 2000 by Ralf Baechle
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2007 by Maciej W. Rozycki
 * Copyright (C) 2011, 2012 MIPS Technologies, Inc.
 */
#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/export.h>
#include <asm/regdef.h>

#if LONGSIZE == 4
#define LONG_S_L swl
#define LONG_S_R swr
#else
#define LONG_S_L sdl
#define LONG_S_R sdr
#endif

#ifdef CONFIG_CPU_MICROMIPS
#define STORSIZE (LONGSIZE * 2)
#define STORMASK (STORSIZE - 1)
#define FILL64RG t8
#define FILLPTRG t7
#undef  LONG_S
#define LONG_S LONG_SP
#else
#define STORSIZE LONGSIZE
#define STORMASK LONGMASK
#define FILL64RG a1
#define FILLPTRG t0
#endif

#define LEGACY_MODE 1
#define EVA_MODE    2

/*
 * No need to protect it with EVA #ifdefery. The generated block of code
 * will never be assembled if EVA is not enabled.
 */
#define __EVAFY(insn, reg, addr) __BUILD_EVA_INSN(insn##e, reg, addr)
#define ___BUILD_EVA_INSN(insn, reg, addr) __EVAFY(insn, reg, addr)

#define EX(insn,reg,addr,handler)			\
	.if \mode == LEGACY_MODE;			\
9:		insn	reg, addr;			\
	.else;						\
9:		___BUILD_EVA_INSN(insn, reg, addr);	\
	.endif;						\
	.section __ex_table,"a";			\
	PTR	9b, handler;				\
	.previous

	.macro	f_fill64 dst, offset, val, fixup, mode
	EX(LONG_S, \val, (\offset +  0 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset +  1 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset +  2 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset +  3 * STORSIZE)(\dst), \fixup)
#if ((defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4)) || !defined(CONFIG_CPU_MICROMIPS))
	EX(LONG_S, \val, (\offset +  4 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset +  5 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset +  6 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset +  7 * STORSIZE)(\dst), \fixup)
#endif
#if (!defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4))
	EX(LONG_S, \val, (\offset +  8 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset +  9 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset + 10 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset + 11 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset + 12 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset + 13 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset + 14 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset + 15 * STORSIZE)(\dst), \fixup)
#endif
	.endm

	.set	noreorder
	.align	5

	/*
	 * Macro to generate the __bzero{,_user} symbol
	 * Arguments:
	 * mode: LEGACY_MODE or EVA_MODE
	 */
	.macro __BUILD_BZERO mode
	/* Initialize __memset if this is the first time we call this macro */
	.ifnotdef __memset
	.set __memset, 1
	.hidden __memset /* Make sure it does not leak */
	.endif

	sltiu		t0, a2, STORSIZE	/* very small region? */
	bnez		t0, .Lsmall_memset\@
	andi		t0, a0, STORMASK	/* aligned? */

#ifdef CONFIG_CPU_MICROMIPS
	move		t8, a1			/* used by 'swp' instruction */
	move		t9, a1
#endif
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
	beqz		t0, 1f
	PTR_SUBU	t0, STORSIZE		/* alignment in bytes */
#else
	.set		noat
	li		AT, STORSIZE
	beqz		t0, 1f
	PTR_SUBU	t0, AT			/* alignment in bytes */
	.set		at
#endif

#ifndef CONFIG_CPU_MIPSR6
	R10KCBARRIER(0(ra))
#ifdef __MIPSEB__
	EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@)	/* make word/dword aligned */
#else
	EX(LONG_S_R, a1, (a0), .Lfirst_fixup\@)	/* make word/dword aligned */
#endif
	PTR_SUBU	a0, t0			/* long align ptr */
	PTR_ADDU	a2, t0			/* correct size */

#else /* CONFIG_CPU_MIPSR6 */
#define STORE_BYTE(N)				\
	EX(sb, a1, N(a0), .Lbyte_fixup\@);	\
	beqz		t0, 0f;			\
	PTR_ADDU	t0, 1;

	PTR_ADDU	a2, t0			/* correct size */
	PTR_ADDU	t0, 1
	STORE_BYTE(0)
	STORE_BYTE(1)
#if LONGSIZE == 4
	EX(sb, a1, 2(a0), .Lbyte_fixup\@)
#else
	STORE_BYTE(2)
	STORE_BYTE(3)
	STORE_BYTE(4)
	STORE_BYTE(5)
	EX(sb, a1, 6(a0), .Lbyte_fixup\@)
#endif
0:
	ori		a0, STORMASK
	xori		a0, STORMASK
	PTR_ADDIU	a0, STORSIZE
#endif /* CONFIG_CPU_MIPSR6 */
1:	ori		t1, a2, 0x3f		/* # of full blocks */
	xori		t1, 0x3f
	beqz		t1, .Lmemset_partial\@	/* no block to fill */
	andi		t0, a2, 0x40-STORSIZE

	PTR_ADDU	t1, a0			/* end address */
	.set		reorder
1:	PTR_ADDIU	a0, 64
	R10KCBARRIER(0(ra))
	f_fill64 a0, -64, FILL64RG, .Lfwd_fixup\@, \mode
	bne		t1, a0, 1b
	.set		noreorder

.Lmemset_partial\@:
	R10KCBARRIER(0(ra))
	PTR_LA		t1, 2f			/* where to start */
#ifdef CONFIG_CPU_MICROMIPS
	LONG_SRL	t7, t0, 1
#endif
#if LONGSIZE == 4
	PTR_SUBU	t1, FILLPTRG
#else
	.set		noat
	LONG_SRL	AT, FILLPTRG, 1
	PTR_SUBU	t1, AT
	.set		at
#endif
	jr		t1
	PTR_ADDU	a0, t0			/* dest ptr */

	.set		push
	.set		noreorder
	.set		nomacro
	/* ... but first do longs ... */
	f_fill64 a0, -64, FILL64RG, .Lpartial_fixup\@, \mode
2:	.set		pop
	andi		a2, STORMASK		/* At most one long to go */

	beqz		a2, 1f
#ifndef CONFIG_CPU_MIPSR6
	PTR_ADDU	a0, a2			/* What's left */
	R10KCBARRIER(0(ra))
#ifdef __MIPSEB__
	EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@)
#else
	EX(LONG_S_L, a1, -1(a0), .Llast_fixup\@)
#endif
#else
	PTR_SUBU	t0, $0, a2
	PTR_ADDIU	t0, 1
	STORE_BYTE(0)
	STORE_BYTE(1)
#if LONGSIZE == 4
	EX(sb, a1, 2(a0), .Lbyte_fixup\@)
#else
	STORE_BYTE(2)
	STORE_BYTE(3)
	STORE_BYTE(4)
	STORE_BYTE(5)
	EX(sb, a1, 6(a0), .Lbyte_fixup\@)
#endif
0:
#endif
1:	jr		ra
	move		a2, zero

.Lsmall_memset\@:
	beqz		a2, 2f
	PTR_ADDU	t1, a0, a2

1:	PTR_ADDIU	a0, 1			/* fill bytewise */
	R10KCBARRIER(0(ra))
	bne		t1, a0, 1b
	sb		a1, -1(a0)

2:	jr		ra			/* done */
	move		a2, zero
	.if __memset == 1
	END(memset)
	.set __memset, 0
	.hidden __memset
	.endif

#ifdef CONFIG_CPU_MIPSR6
.Lbyte_fixup\@:
	PTR_SUBU	a2, $0, t0
	jr		ra
	 PTR_ADDIU	a2, 1
#endif /* CONFIG_CPU_MIPSR6 */

.Lfirst_fixup\@:
	jr	ra
	nop

.Lfwd_fixup\@:
	PTR_L		t0, TI_TASK($28)
	andi		a2, 0x3f
	LONG_L		t0, THREAD_BUADDR(t0)
	LONG_ADDU	a2, t1
	jr		ra
	LONG_SUBU	a2, t0

.Lpartial_fixup\@:
	PTR_L		t0, TI_TASK($28)
	andi		a2, STORMASK
	LONG_L		t0, THREAD_BUADDR(t0)
	LONG_ADDU	a2, t1
	jr		ra
	LONG_SUBU	a2, t0

.Llast_fixup\@:
	jr		ra
	andi		v1, a2, STORMASK

	.endm

/*
 * memset(void *s, int c, size_t n)
 *
 * a0: start of area to clear
 * a1: char to fill with
 * a2: size of area to clear
 */

LEAF(memset)
EXPORT_SYMBOL(memset)
	beqz		a1, 1f
	move		v0, a0			/* result */

	andi		a1, 0xff		/* spread fillword */
	LONG_SLL		t1, a1, 8
	or		a1, t1
	LONG_SLL		t1, a1, 16
#if LONGSIZE == 8
	or		a1, t1
	LONG_SLL		t1, a1, 32
#endif
	or		a1, t1
1:
#ifndef CONFIG_EVA
FEXPORT(__bzero)
EXPORT_SYMBOL(__bzero)
#else
FEXPORT(__bzero_kernel)
EXPORT_SYMBOL(__bzero_kernel)
#endif
	__BUILD_BZERO LEGACY_MODE

#ifdef CONFIG_EVA
LEAF(__bzero)
EXPORT_SYMBOL(__bzero)
	__BUILD_BZERO EVA_MODE
END(__bzero)
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1998, 1999, 2000 by Ralf Baechle
	7	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
26c5e07d SH	8	* Copyright (C) 2007 by Maciej W. Rozycki
26c5e07d SH	9	* Copyright (C) 2011, 2012 MIPS Technologies, Inc.
1da177e4 LT	10	*/
1da177e4 LT	11	#include <asm/asm.h>
048eb582	12	#include <asm/asm-offsets.h>
576a2f0c	13	#include <asm/export.h>
1da177e4 LT	14	#include <asm/regdef.h>
1da177e4 LT	15
a583158c AN	16	#if LONGSIZE == 4
	17	#define LONG_S_L swl
	18	#define LONG_S_R swr
	19	#else
	20	#define LONG_S_L sdl
	21	#define LONG_S_R sdr
	22	#endif
	23
26c5e07d SH	24	#ifdef CONFIG_CPU_MICROMIPS
	25	#define STORSIZE (LONGSIZE * 2)
	26	#define STORMASK (STORSIZE - 1)
	27	#define FILL64RG t8
	28	#define FILLPTRG t7
	29	#undef LONG_S
	30	#define LONG_S LONG_SP
	31	#else
	32	#define STORSIZE LONGSIZE
	33	#define STORMASK LONGMASK
	34	#define FILL64RG a1
	35	#define FILLPTRG t0
	36	#endif
	37
6d5155c2 MC	38	#define LEGACY_MODE 1
	39	#define EVA_MODE 2
	40
fd9720e9 MC	41	/*
	42	* No need to protect it with EVA #ifdefery. The generated block of code
	43	* will never be assembled if EVA is not enabled.
	44	*/
	45	#define __EVAFY(insn, reg, addr) __BUILD_EVA_INSN(insn##e, reg, addr)
	46	#define ___BUILD_EVA_INSN(insn, reg, addr) __EVAFY(insn, reg, addr)
	47
1da177e4	48	#define EX(insn,reg,addr,handler) \
fd9720e9 MC	49	.if \mode == LEGACY_MODE; \
	50	9: insn reg, addr; \
	51	.else; \
	52	9: ___BUILD_EVA_INSN(insn, reg, addr); \
	53	.endif; \
70342287 RB	54	.section __ex_table,"a"; \
70342287 RB	55	PTR 9b, handler; \
1da177e4 LT	56	.previous
1da177e4 LT	57
fd9720e9	58	.macro f_fill64 dst, offset, val, fixup, mode
26c5e07d SH	59	EX(LONG_S, \val, (\offset + 0 * STORSIZE)(\dst), \fixup)
	60	EX(LONG_S, \val, (\offset + 1 * STORSIZE)(\dst), \fixup)
	61	EX(LONG_S, \val, (\offset + 2 * STORSIZE)(\dst), \fixup)
	62	EX(LONG_S, \val, (\offset + 3 * STORSIZE)(\dst), \fixup)
	63	#if ((defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4)) \|\| !defined(CONFIG_CPU_MICROMIPS))
	64	EX(LONG_S, \val, (\offset + 4 * STORSIZE)(\dst), \fixup)
	65	EX(LONG_S, \val, (\offset + 5 * STORSIZE)(\dst), \fixup)
	66	EX(LONG_S, \val, (\offset + 6 * STORSIZE)(\dst), \fixup)
	67	EX(LONG_S, \val, (\offset + 7 * STORSIZE)(\dst), \fixup)
	68	#endif
	69	#if (!defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4))
	70	EX(LONG_S, \val, (\offset + 8 * STORSIZE)(\dst), \fixup)
	71	EX(LONG_S, \val, (\offset + 9 * STORSIZE)(\dst), \fixup)
	72	EX(LONG_S, \val, (\offset + 10 * STORSIZE)(\dst), \fixup)
	73	EX(LONG_S, \val, (\offset + 11 * STORSIZE)(\dst), \fixup)
	74	EX(LONG_S, \val, (\offset + 12 * STORSIZE)(\dst), \fixup)
	75	EX(LONG_S, \val, (\offset + 13 * STORSIZE)(\dst), \fixup)
	76	EX(LONG_S, \val, (\offset + 14 * STORSIZE)(\dst), \fixup)
	77	EX(LONG_S, \val, (\offset + 15 * STORSIZE)(\dst), \fixup)
a583158c	78	#endif
1da177e4 LT	79	.endm
1da177e4 LT	80
1da177e4 LT	81	.set noreorder
1da177e4 LT	82	.align 5
1da177e4	83
6d5155c2 MC	84	/*
	85	* Macro to generate the __bzero{,_user} symbol
	86	* Arguments:
	87	* mode: LEGACY_MODE or EVA_MODE
	88	*/
	89	.macro __BUILD_BZERO mode
	90	/* Initialize __memset if this is the first time we call this macro */
	91	.ifnotdef __memset
	92	.set __memset, 1
	93	.hidden __memset /* Make sure it does not leak */
	94	.endif
1da177e4	95
26c5e07d	96	sltiu t0, a2, STORSIZE /* very small region? */
6d5155c2	97	bnez t0, .Lsmall_memset\@
8483b14a	98	andi t0, a0, STORMASK /* aligned? */
1da177e4	99
26c5e07d SH	100	#ifdef CONFIG_CPU_MICROMIPS
	101	move t8, a1 /* used by 'swp' instruction */
	102	move t9, a1
	103	#endif
619b6e18	104	#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
1da177e4	105	beqz t0, 1f
8483b14a	106	PTR_SUBU t0, STORSIZE /* alignment in bytes */
619b6e18 MR	107	#else
619b6e18 MR	108	.set noat
26c5e07d	109	li AT, STORSIZE
619b6e18	110	beqz t0, 1f
8483b14a	111	PTR_SUBU t0, AT /* alignment in bytes */
619b6e18 MR	112	.set at
619b6e18 MR	113	#endif
1da177e4	114
8c56208a	115	#ifndef CONFIG_CPU_MIPSR6
930bff88	116	R10KCBARRIER(0(ra))
1da177e4	117	#ifdef __MIPSEB__
6d5155c2	118	EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
dd2adea4	119	#else
6d5155c2	120	EX(LONG_S_R, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
1da177e4 LT	121	#endif
	122	PTR_SUBU a0, t0 /* long align ptr */
	123	PTR_ADDU a2, t0 /* correct size */
	124
8c56208a LY	125	#else /* CONFIG_CPU_MIPSR6 */
	126	#define STORE_BYTE(N) \
	127	EX(sb, a1, N(a0), .Lbyte_fixup\@); \
	128	beqz t0, 0f; \
	129	PTR_ADDU t0, 1;
	130
	131	PTR_ADDU a2, t0 /* correct size */
	132	PTR_ADDU t0, 1
	133	STORE_BYTE(0)
	134	STORE_BYTE(1)
	135	#if LONGSIZE == 4
	136	EX(sb, a1, 2(a0), .Lbyte_fixup\@)
	137	#else
	138	STORE_BYTE(2)
	139	STORE_BYTE(3)
	140	STORE_BYTE(4)
	141	STORE_BYTE(5)
	142	EX(sb, a1, 6(a0), .Lbyte_fixup\@)
	143	#endif
	144	0:
	145	ori a0, STORMASK
	146	xori a0, STORMASK
	147	PTR_ADDIU a0, STORSIZE
	148	#endif /* CONFIG_CPU_MIPSR6 */
1da177e4 LT	149	1: ori t1, a2, 0x3f /* # of full blocks */
1da177e4 LT	150	xori t1, 0x3f
6d5155c2	151	beqz t1, .Lmemset_partial\@ /* no block to fill */
8483b14a	152	andi t0, a2, 0x40-STORSIZE
1da177e4 LT	153
	154	PTR_ADDU t1, a0 /* end address */
	155	.set reorder
	156	1: PTR_ADDIU a0, 64
930bff88	157	R10KCBARRIER(0(ra))
fd9720e9	158	f_fill64 a0, -64, FILL64RG, .Lfwd_fixup\@, \mode
1da177e4 LT	159	bne t1, a0, 1b
	160	.set noreorder
	161
6d5155c2	162	.Lmemset_partial\@:
930bff88	163	R10KCBARRIER(0(ra))
1da177e4	164	PTR_LA t1, 2f /* where to start */
26c5e07d SH	165	#ifdef CONFIG_CPU_MICROMIPS
	166	LONG_SRL t7, t0, 1
	167	#endif
a583158c	168	#if LONGSIZE == 4
26c5e07d	169	PTR_SUBU t1, FILLPTRG
a583158c AN	170	#else
a583158c AN	171	.set noat
26c5e07d	172	LONG_SRL AT, FILLPTRG, 1
a583158c	173	PTR_SUBU t1, AT
619b6e18	174	.set at
a583158c	175	#endif
1da177e4	176	jr t1
8483b14a	177	PTR_ADDU a0, t0 /* dest ptr */
1da177e4 LT	178
	179	.set push
	180	.set noreorder
	181	.set nomacro
6d5155c2	182	/* ... but first do longs ... */
fd9720e9	183	f_fill64 a0, -64, FILL64RG, .Lpartial_fixup\@, \mode
1da177e4	184	2: .set pop
26c5e07d	185	andi a2, STORMASK /* At most one long to go */
1da177e4 LT	186
1da177e4 LT	187	beqz a2, 1f
8c56208a	188	#ifndef CONFIG_CPU_MIPSR6
8483b14a	189	PTR_ADDU a0, a2 /* What's left */
930bff88	190	R10KCBARRIER(0(ra))
1da177e4	191	#ifdef __MIPSEB__
6d5155c2	192	EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@)
dd2adea4	193	#else
6d5155c2	194	EX(LONG_S_L, a1, -1(a0), .Llast_fixup\@)
1da177e4	195	#endif
8c56208a LY	196	#else
	197	PTR_SUBU t0, $0, a2
	198	PTR_ADDIU t0, 1
	199	STORE_BYTE(0)
	200	STORE_BYTE(1)
	201	#if LONGSIZE == 4
	202	EX(sb, a1, 2(a0), .Lbyte_fixup\@)
	203	#else
	204	STORE_BYTE(2)
	205	STORE_BYTE(3)
	206	STORE_BYTE(4)
	207	STORE_BYTE(5)
	208	EX(sb, a1, 6(a0), .Lbyte_fixup\@)
	209	#endif
	210	0:
	211	#endif
1da177e4	212	1: jr ra
8483b14a	213	move a2, zero
1da177e4	214
6d5155c2	215	.Lsmall_memset\@:
1da177e4	216	beqz a2, 2f
8483b14a	217	PTR_ADDU t1, a0, a2
1da177e4 LT	218
1da177e4 LT	219	1: PTR_ADDIU a0, 1 /* fill bytewise */
930bff88	220	R10KCBARRIER(0(ra))
1da177e4	221	bne t1, a0, 1b
8483b14a	222	sb a1, -1(a0)
1da177e4 LT	223
1da177e4 LT	224	2: jr ra /* done */
8483b14a	225	move a2, zero
6d5155c2	226	.if __memset == 1
1da177e4	227	END(memset)
6d5155c2 MC	228	.set __memset, 0
	229	.hidden __memset
	230	.endif
1da177e4	231
8e85f275	232	#ifdef CONFIG_CPU_MIPSR6
8c56208a LY	233	.Lbyte_fixup\@:
	234	PTR_SUBU a2, $0, t0
	235	jr ra
	236	PTR_ADDIU a2, 1
8e85f275	237	#endif /* CONFIG_CPU_MIPSR6 */
8c56208a	238
6d5155c2	239	.Lfirst_fixup\@:
1da177e4	240	jr ra
8483b14a	241	nop
1da177e4	242
6d5155c2	243	.Lfwd_fixup\@:
1da177e4	244	PTR_L t0, TI_TASK($28)
1da177e4	245	andi a2, 0x3f
e5674ad6	246	LONG_L t0, THREAD_BUADDR(t0)
1da177e4 LT	247	LONG_ADDU a2, t1
1da177e4 LT	248	jr ra
8483b14a	249	LONG_SUBU a2, t0
1da177e4	250
6d5155c2	251	.Lpartial_fixup\@:
1da177e4	252	PTR_L t0, TI_TASK($28)
26c5e07d	253	andi a2, STORMASK
e5674ad6	254	LONG_L t0, THREAD_BUADDR(t0)
1da177e4 LT	255	LONG_ADDU a2, t1
1da177e4 LT	256	jr ra
8483b14a	257	LONG_SUBU a2, t0
1da177e4	258
6d5155c2	259	.Llast_fixup\@:
1da177e4	260	jr ra
8483b14a	261	andi v1, a2, STORMASK
6d5155c2 MC	262
	263	.endm
	264
	265	/*
	266	* memset(void *s, int c, size_t n)
	267	*
	268	* a0: start of area to clear
	269	* a1: char to fill with
	270	* a2: size of area to clear
	271	*/
	272
	273	LEAF(memset)
576a2f0c	274	EXPORT_SYMBOL(memset)
6d5155c2 MC	275	beqz a1, 1f
	276	move v0, a0 /* result */
	277
	278	andi a1, 0xff /* spread fillword */
	279	LONG_SLL t1, a1, 8
	280	or a1, t1
	281	LONG_SLL t1, a1, 16
	282	#if LONGSIZE == 8
	283	or a1, t1
	284	LONG_SLL t1, a1, 32
	285	#endif
	286	or a1, t1
	287	1:
fd9720e9	288	#ifndef CONFIG_EVA
6d5155c2	289	FEXPORT(__bzero)
576a2f0c	290	EXPORT_SYMBOL(__bzero)
d6a428fb JH	291	#else
d6a428fb JH	292	FEXPORT(__bzero_kernel)
576a2f0c	293	EXPORT_SYMBOL(__bzero_kernel)
fd9720e9	294	#endif
6d5155c2	295	__BUILD_BZERO LEGACY_MODE
fd9720e9 MC	296
	297	#ifdef CONFIG_EVA
	298	LEAF(__bzero)
576a2f0c	299	EXPORT_SYMBOL(__bzero)
fd9720e9 MC	300	__BUILD_BZERO EVA_MODE
	301	END(__bzero)
	302	#endif