[mirror_ubuntu-hirsute-kernel.git] / arch / mips / lib / memset.S

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1998, 1999, 2000 by Ralf Baechle
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2007 by Maciej W. Rozycki
 * Copyright (C) 2011, 2012 MIPS Technologies, Inc.
 */
#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/regdef.h>

#if LONGSIZE == 4
#define LONG_S_L swl
#define LONG_S_R swr
#else
#define LONG_S_L sdl
#define LONG_S_R sdr
#endif

#ifdef CONFIG_CPU_MICROMIPS
#define STORSIZE (LONGSIZE * 2)
#define STORMASK (STORSIZE - 1)
#define FILL64RG t8
#define FILLPTRG t7
#undef  LONG_S
#define LONG_S LONG_SP
#else
#define STORSIZE LONGSIZE
#define STORMASK LONGMASK
#define FILL64RG a1
#define FILLPTRG t0
#endif

#define EX(insn,reg,addr,handler)			\
9:	insn	reg, addr;				\
	.section __ex_table,"a";			\
	PTR	9b, handler;				\
	.previous

	.macro	f_fill64 dst, offset, val, fixup
	EX(LONG_S, \val, (\offset +  0 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset +  1 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset +  2 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset +  3 * STORSIZE)(\dst), \fixup)
#if ((defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4)) || !defined(CONFIG_CPU_MICROMIPS))
	EX(LONG_S, \val, (\offset +  4 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset +  5 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset +  6 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset +  7 * STORSIZE)(\dst), \fixup)
#endif
#if (!defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4))
	EX(LONG_S, \val, (\offset +  8 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset +  9 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset + 10 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset + 11 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset + 12 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset + 13 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset + 14 * STORSIZE)(\dst), \fixup)
	EX(LONG_S, \val, (\offset + 15 * STORSIZE)(\dst), \fixup)
#endif
	.endm

/*
 * memset(void *s, int c, size_t n)
 *
 * a0: start of area to clear
 * a1: char to fill with
 * a2: size of area to clear
 */
	.set	noreorder
	.align	5
LEAF(memset)
	beqz		a1, 1f
	move		v0, a0			/* result */

	andi		a1, 0xff		/* spread fillword */
	LONG_SLL		t1, a1, 8
	or		a1, t1
	LONG_SLL		t1, a1, 16
#if LONGSIZE == 8
	or		a1, t1
	LONG_SLL		t1, a1, 32
#endif
	or		a1, t1
1:

FEXPORT(__bzero)
	sltiu		t0, a2, STORSIZE	/* very small region? */
	bnez		t0, .Lsmall_memset
	andi		t0, a0, STORMASK	/* aligned? */

#ifdef CONFIG_CPU_MICROMIPS
	move		t8, a1			/* used by 'swp' instruction */
	move		t9, a1
#endif
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
	beqz		t0, 1f
	PTR_SUBU	t0, STORSIZE		/* alignment in bytes */
#else
	.set		noat
	li		AT, STORSIZE
	beqz		t0, 1f
	PTR_SUBU	t0, AT			/* alignment in bytes */
	.set		at
#endif

	R10KCBARRIER(0(ra))
#ifdef __MIPSEB__
	EX(LONG_S_L, a1, (a0), .Lfirst_fixup)	/* make word/dword aligned */
#endif
#ifdef __MIPSEL__
	EX(LONG_S_R, a1, (a0), .Lfirst_fixup)	/* make word/dword aligned */
#endif
	PTR_SUBU	a0, t0			/* long align ptr */
	PTR_ADDU	a2, t0			/* correct size */

1:	ori		t1, a2, 0x3f		/* # of full blocks */
	xori		t1, 0x3f
	beqz		t1, .Lmemset_partial	/* no block to fill */
	andi		t0, a2, 0x40-STORSIZE

	PTR_ADDU	t1, a0			/* end address */
	.set		reorder
1:	PTR_ADDIU	a0, 64
	R10KCBARRIER(0(ra))
	f_fill64 a0, -64, FILL64RG, .Lfwd_fixup
	bne		t1, a0, 1b
	.set		noreorder

.Lmemset_partial:
	R10KCBARRIER(0(ra))
	PTR_LA		t1, 2f			/* where to start */
#ifdef CONFIG_CPU_MICROMIPS
	LONG_SRL	t7, t0, 1
#endif
#if LONGSIZE == 4
	PTR_SUBU	t1, FILLPTRG
#else
	.set		noat
	LONG_SRL	AT, FILLPTRG, 1
	PTR_SUBU	t1, AT
	.set		at
#endif
	jr		t1
	PTR_ADDU	a0, t0			/* dest ptr */

	.set		push
	.set		noreorder
	.set		nomacro
	f_fill64 a0, -64, FILL64RG, .Lpartial_fixup	/* ... but first do longs ... */
2:	.set		pop
	andi		a2, STORMASK		/* At most one long to go */

	beqz		a2, 1f
	PTR_ADDU	a0, a2			/* What's left */
	R10KCBARRIER(0(ra))
#ifdef __MIPSEB__
	EX(LONG_S_R, a1, -1(a0), .Llast_fixup)
#endif
#ifdef __MIPSEL__
	EX(LONG_S_L, a1, -1(a0), .Llast_fixup)
#endif
1:	jr		ra
	move		a2, zero

.Lsmall_memset:
	beqz		a2, 2f
	PTR_ADDU	t1, a0, a2

1:	PTR_ADDIU	a0, 1			/* fill bytewise */
	R10KCBARRIER(0(ra))
	bne		t1, a0, 1b
	sb		a1, -1(a0)

2:	jr		ra			/* done */
	move		a2, zero
	END(memset)

.Lfirst_fixup:
	jr	ra
	nop

.Lfwd_fixup:
	PTR_L		t0, TI_TASK($28)
	andi		a2, 0x3f
	LONG_L		t0, THREAD_BUADDR(t0)
	LONG_ADDU	a2, t1
	jr		ra
	LONG_SUBU	a2, t0

.Lpartial_fixup:
	PTR_L		t0, TI_TASK($28)
	andi		a2, STORMASK
	LONG_L		t0, THREAD_BUADDR(t0)
	LONG_ADDU	a2, t1
	jr		ra
	LONG_SUBU	a2, t0

.Llast_fixup:
	jr		ra
	andi		v1, a2, STORMASK
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1998, 1999, 2000 by Ralf Baechle
	7	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
26c5e07d SH	8	* Copyright (C) 2007 by Maciej W. Rozycki
26c5e07d SH	9	* Copyright (C) 2011, 2012 MIPS Technologies, Inc.
1da177e4 LT	10	*/
1da177e4 LT	11	#include <asm/asm.h>
048eb582	12	#include <asm/asm-offsets.h>
1da177e4 LT	13	#include <asm/regdef.h>
1da177e4 LT	14
a583158c AN	15	#if LONGSIZE == 4
	16	#define LONG_S_L swl
	17	#define LONG_S_R swr
	18	#else
	19	#define LONG_S_L sdl
	20	#define LONG_S_R sdr
	21	#endif
	22
26c5e07d SH	23	#ifdef CONFIG_CPU_MICROMIPS
	24	#define STORSIZE (LONGSIZE * 2)
	25	#define STORMASK (STORSIZE - 1)
	26	#define FILL64RG t8
	27	#define FILLPTRG t7
	28	#undef LONG_S
	29	#define LONG_S LONG_SP
	30	#else
	31	#define STORSIZE LONGSIZE
	32	#define STORMASK LONGMASK
	33	#define FILL64RG a1
	34	#define FILLPTRG t0
	35	#endif
	36
1da177e4 LT	37	#define EX(insn,reg,addr,handler) \
1da177e4 LT	38	9: insn reg, addr; \
70342287 RB	39	.section __ex_table,"a"; \
70342287 RB	40	PTR 9b, handler; \
1da177e4 LT	41	.previous
	42
	43	.macro f_fill64 dst, offset, val, fixup
26c5e07d SH	44	EX(LONG_S, \val, (\offset + 0 * STORSIZE)(\dst), \fixup)
	45	EX(LONG_S, \val, (\offset + 1 * STORSIZE)(\dst), \fixup)
	46	EX(LONG_S, \val, (\offset + 2 * STORSIZE)(\dst), \fixup)
	47	EX(LONG_S, \val, (\offset + 3 * STORSIZE)(\dst), \fixup)
	48	#if ((defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4)) \|\| !defined(CONFIG_CPU_MICROMIPS))
	49	EX(LONG_S, \val, (\offset + 4 * STORSIZE)(\dst), \fixup)
	50	EX(LONG_S, \val, (\offset + 5 * STORSIZE)(\dst), \fixup)
	51	EX(LONG_S, \val, (\offset + 6 * STORSIZE)(\dst), \fixup)
	52	EX(LONG_S, \val, (\offset + 7 * STORSIZE)(\dst), \fixup)
	53	#endif
	54	#if (!defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4))
	55	EX(LONG_S, \val, (\offset + 8 * STORSIZE)(\dst), \fixup)
	56	EX(LONG_S, \val, (\offset + 9 * STORSIZE)(\dst), \fixup)
	57	EX(LONG_S, \val, (\offset + 10 * STORSIZE)(\dst), \fixup)
	58	EX(LONG_S, \val, (\offset + 11 * STORSIZE)(\dst), \fixup)
	59	EX(LONG_S, \val, (\offset + 12 * STORSIZE)(\dst), \fixup)
	60	EX(LONG_S, \val, (\offset + 13 * STORSIZE)(\dst), \fixup)
	61	EX(LONG_S, \val, (\offset + 14 * STORSIZE)(\dst), \fixup)
	62	EX(LONG_S, \val, (\offset + 15 * STORSIZE)(\dst), \fixup)
a583158c	63	#endif
1da177e4 LT	64	.endm
	65
	66	/*
	67	* memset(void *s, int c, size_t n)
	68	*
	69	* a0: start of area to clear
	70	* a1: char to fill with
	71	* a2: size of area to clear
	72	*/
	73	.set noreorder
	74	.align 5
	75	LEAF(memset)
	76	beqz a1, 1f
8483b14a	77	move v0, a0 /* result */
1da177e4 LT	78
1da177e4 LT	79	andi a1, 0xff /* spread fillword */
a583158c	80	LONG_SLL t1, a1, 8
1da177e4	81	or a1, t1
a583158c AN	82	LONG_SLL t1, a1, 16
	83	#if LONGSIZE == 8
	84	or a1, t1
	85	LONG_SLL t1, a1, 32
	86	#endif
1da177e4 LT	87	or a1, t1
	88	1:
	89
	90	FEXPORT(__bzero)
26c5e07d	91	sltiu t0, a2, STORSIZE /* very small region? */
c5ec1983	92	bnez t0, .Lsmall_memset
8483b14a	93	andi t0, a0, STORMASK /* aligned? */
1da177e4	94
26c5e07d SH	95	#ifdef CONFIG_CPU_MICROMIPS
	96	move t8, a1 /* used by 'swp' instruction */
	97	move t9, a1
	98	#endif
619b6e18	99	#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
1da177e4	100	beqz t0, 1f
8483b14a	101	PTR_SUBU t0, STORSIZE /* alignment in bytes */
619b6e18 MR	102	#else
619b6e18 MR	103	.set noat
26c5e07d	104	li AT, STORSIZE
619b6e18	105	beqz t0, 1f
8483b14a	106	PTR_SUBU t0, AT /* alignment in bytes */
619b6e18 MR	107	.set at
619b6e18 MR	108	#endif
1da177e4	109
930bff88	110	R10KCBARRIER(0(ra))
1da177e4	111	#ifdef __MIPSEB__
c5ec1983	112	EX(LONG_S_L, a1, (a0), .Lfirst_fixup) /* make word/dword aligned */
1da177e4 LT	113	#endif
1da177e4 LT	114	#ifdef __MIPSEL__
c5ec1983	115	EX(LONG_S_R, a1, (a0), .Lfirst_fixup) /* make word/dword aligned */
1da177e4 LT	116	#endif
	117	PTR_SUBU a0, t0 /* long align ptr */
	118	PTR_ADDU a2, t0 /* correct size */
	119
	120	1: ori t1, a2, 0x3f /* # of full blocks */
	121	xori t1, 0x3f
c5ec1983	122	beqz t1, .Lmemset_partial /* no block to fill */
8483b14a	123	andi t0, a2, 0x40-STORSIZE
1da177e4 LT	124
	125	PTR_ADDU t1, a0 /* end address */
	126	.set reorder
	127	1: PTR_ADDIU a0, 64
930bff88	128	R10KCBARRIER(0(ra))
26c5e07d	129	f_fill64 a0, -64, FILL64RG, .Lfwd_fixup
1da177e4 LT	130	bne t1, a0, 1b
	131	.set noreorder
	132
c5ec1983	133	.Lmemset_partial:
930bff88	134	R10KCBARRIER(0(ra))
1da177e4	135	PTR_LA t1, 2f /* where to start */
26c5e07d SH	136	#ifdef CONFIG_CPU_MICROMIPS
	137	LONG_SRL t7, t0, 1
	138	#endif
a583158c	139	#if LONGSIZE == 4
26c5e07d	140	PTR_SUBU t1, FILLPTRG
a583158c AN	141	#else
a583158c AN	142	.set noat
26c5e07d	143	LONG_SRL AT, FILLPTRG, 1
a583158c	144	PTR_SUBU t1, AT
619b6e18	145	.set at
a583158c	146	#endif
1da177e4	147	jr t1
8483b14a	148	PTR_ADDU a0, t0 /* dest ptr */
1da177e4 LT	149
	150	.set push
	151	.set noreorder
	152	.set nomacro
26c5e07d	153	f_fill64 a0, -64, FILL64RG, .Lpartial_fixup /* ... but first do longs ... */
1da177e4	154	2: .set pop
26c5e07d	155	andi a2, STORMASK /* At most one long to go */
1da177e4 LT	156
1da177e4 LT	157	beqz a2, 1f
8483b14a	158	PTR_ADDU a0, a2 /* What's left */
930bff88	159	R10KCBARRIER(0(ra))
1da177e4	160	#ifdef __MIPSEB__
c5ec1983	161	EX(LONG_S_R, a1, -1(a0), .Llast_fixup)
1da177e4 LT	162	#endif
1da177e4 LT	163	#ifdef __MIPSEL__
c5ec1983	164	EX(LONG_S_L, a1, -1(a0), .Llast_fixup)
1da177e4 LT	165	#endif
1da177e4 LT	166	1: jr ra
8483b14a	167	move a2, zero
1da177e4	168
c5ec1983	169	.Lsmall_memset:
1da177e4	170	beqz a2, 2f
8483b14a	171	PTR_ADDU t1, a0, a2
1da177e4 LT	172
1da177e4 LT	173	1: PTR_ADDIU a0, 1 /* fill bytewise */
930bff88	174	R10KCBARRIER(0(ra))
1da177e4	175	bne t1, a0, 1b
8483b14a	176	sb a1, -1(a0)
1da177e4 LT	177
1da177e4 LT	178	2: jr ra /* done */
8483b14a	179	move a2, zero
1da177e4 LT	180	END(memset)
1da177e4 LT	181
c5ec1983	182	.Lfirst_fixup:
1da177e4	183	jr ra
8483b14a	184	nop
1da177e4	185
c5ec1983	186	.Lfwd_fixup:
1da177e4	187	PTR_L t0, TI_TASK($28)
1da177e4	188	andi a2, 0x3f
e5674ad6	189	LONG_L t0, THREAD_BUADDR(t0)
1da177e4 LT	190	LONG_ADDU a2, t1
1da177e4 LT	191	jr ra
8483b14a	192	LONG_SUBU a2, t0
1da177e4	193
c5ec1983	194	.Lpartial_fixup:
1da177e4	195	PTR_L t0, TI_TASK($28)
26c5e07d	196	andi a2, STORMASK
e5674ad6	197	LONG_L t0, THREAD_BUADDR(t0)
1da177e4 LT	198	LONG_ADDU a2, t1
1da177e4 LT	199	jr ra
8483b14a	200	LONG_SUBU a2, t0
1da177e4	201
c5ec1983	202	.Llast_fixup:
1da177e4	203	jr ra
8483b14a	204	andi v1, a2, STORMASK