]>
Commit | Line | Data |
---|---|---|
42d226c7 ST |
1 | /* |
2 | * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology | |
3 | * Author: Fuxin Zhang, zhangfx@lemote.com | |
4 | * | |
70342287 RB |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
42d226c7 | 8 | * option) any later version. |
42d226c7 | 9 | */ |
42d226c7 | 10 | #include <linux/interrupt.h> |
42d226c7 ST |
11 | |
12 | #include <asm/irq_cpu.h> | |
13 | #include <asm/i8259.h> | |
42d226c7 | 14 | |
5e983ff6 | 15 | #include <loongson.h> |
42d226c7 ST |
16 | |
17 | static void i8259_irqdispatch(void) | |
18 | { | |
19 | int irq; | |
20 | ||
21 | irq = i8259_irq(); | |
5e983ff6 | 22 | if (irq >= 0) |
42d226c7 | 23 | do_IRQ(irq); |
5e983ff6 | 24 | else |
42d226c7 | 25 | spurious_interrupt(); |
42d226c7 ST |
26 | } |
27 | ||
85749d24 | 28 | asmlinkage void mach_irq_dispatch(unsigned int pending) |
42d226c7 | 29 | { |
5e983ff6 | 30 | if (pending & CAUSEF_IP7) |
42d226c7 | 31 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
67b35e5d | 32 | else if (pending & CAUSEF_IP6) /* perf counter loverflow */ |
de3bc0e7 | 33 | do_perfcnt_IRQ(); |
5e983ff6 | 34 | else if (pending & CAUSEF_IP5) |
42d226c7 | 35 | i8259_irqdispatch(); |
5e983ff6 | 36 | else if (pending & CAUSEF_IP2) |
42d226c7 | 37 | bonito_irqdispatch(); |
5e983ff6 | 38 | else |
42d226c7 | 39 | spurious_interrupt(); |
42d226c7 ST |
40 | } |
41 | ||
42 | static struct irqaction cascade_irqaction = { | |
43 | .handler = no_action, | |
42d226c7 | 44 | .name = "cascade", |
77cbece7 | 45 | .flags = IRQF_NO_THREAD, |
42d226c7 ST |
46 | }; |
47 | ||
85749d24 WZ |
48 | void __init mach_init_irq(void) |
49 | { | |
42d226c7 | 50 | /* init all controller |
70342287 RB |
51 | * 0-15 ------> i8259 interrupt |
52 | * 16-23 ------> mips cpu interrupt | |
53 | * 32-63 ------> bonito irq | |
42d226c7 ST |
54 | */ |
55 | ||
b8c7428a WZ |
56 | /* most bonito irq should be level triggered */ |
57 | LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR | | |
58 | LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES; | |
59 | ||
42d226c7 ST |
60 | /* Sets the first-level interrupt dispatcher. */ |
61 | mips_cpu_irq_init(); | |
62 | init_i8259_irqs(); | |
63 | bonito_irq_init(); | |
64 | ||
42d226c7 ST |
65 | /* bonito irq at IP2 */ |
66 | setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); | |
67 | /* 8259 irq at IP5 */ | |
68 | setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); | |
42d226c7 | 69 | } |