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42d226c7 ST |
1 | /* |
2 | * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology | |
3 | * Author: Fuxin Zhang, zhangfx@lemote.com | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
42d226c7 | 9 | */ |
42d226c7 | 10 | #include <linux/interrupt.h> |
42d226c7 ST |
11 | |
12 | #include <asm/irq_cpu.h> | |
13 | #include <asm/i8259.h> | |
42d226c7 | 14 | |
5e983ff6 | 15 | #include <loongson.h> |
42d226c7 ST |
16 | |
17 | static void i8259_irqdispatch(void) | |
18 | { | |
19 | int irq; | |
20 | ||
21 | irq = i8259_irq(); | |
5e983ff6 | 22 | if (irq >= 0) |
42d226c7 | 23 | do_IRQ(irq); |
5e983ff6 | 24 | else |
42d226c7 | 25 | spurious_interrupt(); |
42d226c7 ST |
26 | } |
27 | ||
85749d24 | 28 | asmlinkage void mach_irq_dispatch(unsigned int pending) |
42d226c7 | 29 | { |
5e983ff6 | 30 | if (pending & CAUSEF_IP7) |
42d226c7 | 31 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
67b35e5d WZ |
32 | else if (pending & CAUSEF_IP6) /* perf counter loverflow */ |
33 | do_IRQ(LOONGSON2_PERFCNT_IRQ); | |
5e983ff6 | 34 | else if (pending & CAUSEF_IP5) |
42d226c7 | 35 | i8259_irqdispatch(); |
5e983ff6 | 36 | else if (pending & CAUSEF_IP2) |
42d226c7 | 37 | bonito_irqdispatch(); |
5e983ff6 | 38 | else |
42d226c7 | 39 | spurious_interrupt(); |
42d226c7 ST |
40 | } |
41 | ||
42 | static struct irqaction cascade_irqaction = { | |
43 | .handler = no_action, | |
42d226c7 ST |
44 | .name = "cascade", |
45 | }; | |
46 | ||
85749d24 | 47 | void __init set_irq_trigger_mode(void) |
42d226c7 | 48 | { |
42d226c7 ST |
49 | /* most bonito irq should be level triggered */ |
50 | BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR | | |
85749d24 WZ |
51 | BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; |
52 | } | |
42d226c7 | 53 | |
85749d24 WZ |
54 | void __init mach_init_irq(void) |
55 | { | |
42d226c7 ST |
56 | /* init all controller |
57 | * 0-15 ------> i8259 interrupt | |
58 | * 16-23 ------> mips cpu interrupt | |
59 | * 32-63 ------> bonito irq | |
60 | */ | |
61 | ||
62 | /* Sets the first-level interrupt dispatcher. */ | |
63 | mips_cpu_irq_init(); | |
64 | init_i8259_irqs(); | |
65 | bonito_irq_init(); | |
66 | ||
42d226c7 ST |
67 | /* bonito irq at IP2 */ |
68 | setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); | |
69 | /* 8259 irq at IP5 */ | |
70 | setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); | |
42d226c7 | 71 | } |