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f8ede0f7 WZ |
1 | /* |
2 | * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology | |
3 | * Author: Yanhua, yanh@lemote.com | |
4 | * | |
5 | * This file is subject to the terms and conditions of the GNU General Public | |
6 | * License. See the file "COPYING" in the main directory of this archive | |
7 | * for more details. | |
8 | */ | |
95cf1468 | 9 | #include <linux/clk.h> |
f8ede0f7 | 10 | #include <linux/cpufreq.h> |
95cf1468 RB |
11 | #include <linux/errno.h> |
12 | #include <linux/export.h> | |
95cf1468 RB |
13 | #include <linux/list.h> |
14 | #include <linux/mutex.h> | |
15 | #include <linux/spinlock.h> | |
f8ede0f7 WZ |
16 | |
17 | #include <asm/clock.h> | |
95cf1468 | 18 | #include <asm/mach-loongson/loongson.h> |
f8ede0f7 WZ |
19 | |
20 | static LIST_HEAD(clock_list); | |
21 | static DEFINE_SPINLOCK(clock_lock); | |
22 | static DEFINE_MUTEX(clock_list_sem); | |
23 | ||
24 | /* Minimum CLK support */ | |
25 | enum { | |
26 | DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT, | |
27 | DC_87PT, DC_DISABLE, DC_RESV | |
28 | }; | |
29 | ||
30 | struct cpufreq_frequency_table loongson2_clockmod_table[] = { | |
7f4b0461 VK |
31 | {0, DC_RESV, CPUFREQ_ENTRY_INVALID}, |
32 | {0, DC_ZERO, CPUFREQ_ENTRY_INVALID}, | |
33 | {0, DC_25PT, 0}, | |
34 | {0, DC_37PT, 0}, | |
35 | {0, DC_50PT, 0}, | |
36 | {0, DC_62PT, 0}, | |
37 | {0, DC_75PT, 0}, | |
38 | {0, DC_87PT, 0}, | |
39 | {0, DC_DISABLE, 0}, | |
40 | {0, DC_RESV, CPUFREQ_TABLE_END}, | |
f8ede0f7 WZ |
41 | }; |
42 | EXPORT_SYMBOL_GPL(loongson2_clockmod_table); | |
43 | ||
44 | static struct clk cpu_clk = { | |
45 | .name = "cpu_clk", | |
46 | .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES, | |
47 | .rate = 800000000, | |
48 | }; | |
49 | ||
50 | struct clk *clk_get(struct device *dev, const char *id) | |
51 | { | |
52 | return &cpu_clk; | |
53 | } | |
54 | EXPORT_SYMBOL(clk_get); | |
55 | ||
56 | static void propagate_rate(struct clk *clk) | |
57 | { | |
58 | struct clk *clkp; | |
59 | ||
60 | list_for_each_entry(clkp, &clock_list, node) { | |
61 | if (likely(clkp->parent != clk)) | |
62 | continue; | |
63 | if (likely(clkp->ops && clkp->ops->recalc)) | |
64 | clkp->ops->recalc(clkp); | |
65 | if (unlikely(clkp->flags & CLK_RATE_PROPAGATES)) | |
66 | propagate_rate(clkp); | |
67 | } | |
68 | } | |
69 | ||
70 | int clk_enable(struct clk *clk) | |
71 | { | |
72 | return 0; | |
73 | } | |
74 | EXPORT_SYMBOL(clk_enable); | |
75 | ||
76 | void clk_disable(struct clk *clk) | |
77 | { | |
78 | } | |
79 | EXPORT_SYMBOL(clk_disable); | |
80 | ||
81 | unsigned long clk_get_rate(struct clk *clk) | |
82 | { | |
83 | return (unsigned long)clk->rate; | |
84 | } | |
85 | EXPORT_SYMBOL(clk_get_rate); | |
86 | ||
87 | void clk_put(struct clk *clk) | |
88 | { | |
89 | } | |
90 | EXPORT_SYMBOL(clk_put); | |
91 | ||
92 | int clk_set_rate(struct clk *clk, unsigned long rate) | |
f8ede0f7 WZ |
93 | { |
94 | int ret = 0; | |
95 | int regval; | |
96 | int i; | |
97 | ||
98 | if (likely(clk->ops && clk->ops->set_rate)) { | |
99 | unsigned long flags; | |
100 | ||
101 | spin_lock_irqsave(&clock_lock, flags); | |
95cf1468 | 102 | ret = clk->ops->set_rate(clk, rate, 0); |
f8ede0f7 WZ |
103 | spin_unlock_irqrestore(&clock_lock, flags); |
104 | } | |
105 | ||
106 | if (unlikely(clk->flags & CLK_RATE_PROPAGATES)) | |
107 | propagate_rate(clk); | |
108 | ||
109 | for (i = 0; loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END; | |
110 | i++) { | |
111 | if (loongson2_clockmod_table[i].frequency == | |
112 | CPUFREQ_ENTRY_INVALID) | |
113 | continue; | |
114 | if (rate == loongson2_clockmod_table[i].frequency) | |
115 | break; | |
116 | } | |
117 | if (rate != loongson2_clockmod_table[i].frequency) | |
118 | return -ENOTSUPP; | |
119 | ||
120 | clk->rate = rate; | |
121 | ||
122 | regval = LOONGSON_CHIPCFG0; | |
50701588 VK |
123 | regval = (regval & ~0x7) | |
124 | (loongson2_clockmod_table[i].driver_data - 1); | |
f8ede0f7 WZ |
125 | LOONGSON_CHIPCFG0 = regval; |
126 | ||
127 | return ret; | |
128 | } | |
95cf1468 | 129 | EXPORT_SYMBOL_GPL(clk_set_rate); |
f8ede0f7 WZ |
130 | |
131 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
132 | { | |
133 | if (likely(clk->ops && clk->ops->round_rate)) { | |
134 | unsigned long flags, rounded; | |
135 | ||
136 | spin_lock_irqsave(&clock_lock, flags); | |
137 | rounded = clk->ops->round_rate(clk, rate); | |
138 | spin_unlock_irqrestore(&clock_lock, flags); | |
139 | ||
140 | return rounded; | |
141 | } | |
142 | ||
143 | return rate; | |
144 | } | |
145 | EXPORT_SYMBOL_GPL(clk_round_rate); |