[mirror_ubuntu-artful-kernel.git] / arch / mips / loongson / loongson-3 / smp.c

/*
 * Copyright (C) 2010, 2011, 2012, Lemote, Inc.
 * Author: Chen Huacai, chenhc@lemote.com
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/cpufreq.h>
#include <asm/processor.h>
#include <asm/time.h>
#include <asm/clock.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
#include <loongson.h>

#include "smp.h"

DEFINE_PER_CPU(int, cpu_state);
DEFINE_PER_CPU(uint32_t, core0_c0count);

/* read a 32bit value from ipi register */
#define loongson3_ipi_read32(addr) readl(addr)
/* read a 64bit value from ipi register */
#define loongson3_ipi_read64(addr) readq(addr)
/* write a 32bit value to ipi register */
#define loongson3_ipi_write32(action, addr)	\
	do {					\
		writel(action, addr);		\
		__wbflush();			\
	} while (0)
/* write a 64bit value to ipi register */
#define loongson3_ipi_write64(action, addr)	\
	do {					\
		writeq(action, addr);		\
		__wbflush();			\
	} while (0)

static void *ipi_set0_regs[] = {
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0),
};

static void *ipi_clear0_regs[] = {
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0),
};

static void *ipi_status0_regs[] = {
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0),
};

static void *ipi_en0_regs[] = {
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0),
};

static void *ipi_mailbox_buf[] = {
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF),
	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF),
};

/*
 * Simple enough, just poke the appropriate ipi register
 */
static void loongson3_send_ipi_single(int cpu, unsigned int action)
{
	loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]);
}

static void
loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
{
	unsigned int i;

	for_each_cpu(i, mask)
		loongson3_ipi_write32((u32)action, ipi_set0_regs[i]);
}

void loongson3_ipi_interrupt(struct pt_regs *regs)
{
	int i, cpu = smp_processor_id();
	unsigned int action, c0count;

	/* Load the ipi register to figure out what we're supposed to do */
	action = loongson3_ipi_read32(ipi_status0_regs[cpu]);

	/* Clear the ipi register to clear the interrupt */
	loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu]);

	if (action & SMP_RESCHEDULE_YOURSELF)
		scheduler_ipi();

	if (action & SMP_CALL_FUNCTION)
		smp_call_function_interrupt();

	if (action & SMP_ASK_C0COUNT) {
		BUG_ON(cpu != 0);
		c0count = read_c0_count();
		for (i = 1; i < loongson_sysconf.nr_cpus; i++)
			per_cpu(core0_c0count, i) = c0count;
	}
}

#define MAX_LOOPS 1111
/*
 * SMP init and finish on secondary CPUs
 */
static void loongson3_init_secondary(void)
{
	int i;
	uint32_t initcount;
	unsigned int cpu = smp_processor_id();
	unsigned int imask = STATUSF_IP7 | STATUSF_IP6 |
			     STATUSF_IP3 | STATUSF_IP2;

	/* Set interrupt mask, but don't enable */
	change_c0_status(ST0_IM, imask);

	for (i = 0; i < loongson_sysconf.nr_cpus; i++)
		loongson3_ipi_write32(0xffffffff, ipi_en0_regs[i]);

	cpu_data[cpu].package = cpu / loongson_sysconf.cores_per_package;
	cpu_data[cpu].core = cpu % loongson_sysconf.cores_per_package;
	per_cpu(cpu_state, cpu) = CPU_ONLINE;

	i = 0;
	__get_cpu_var(core0_c0count) = 0;
	loongson3_send_ipi_single(0, SMP_ASK_C0COUNT);
	while (!__get_cpu_var(core0_c0count)) {
		i++;
		cpu_relax();
	}

	if (i > MAX_LOOPS)
		i = MAX_LOOPS;
	initcount = __get_cpu_var(core0_c0count) + i;
	write_c0_count(initcount);
}

static void loongson3_smp_finish(void)
{
	write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
	local_irq_enable();
	loongson3_ipi_write64(0,
			(void *)(ipi_mailbox_buf[smp_processor_id()]+0x0));
	pr_info("CPU#%d finished, CP0_ST=%x\n",
			smp_processor_id(), read_c0_status());
}

static void __init loongson3_smp_setup(void)
{
	int i, num;

	init_cpu_possible(cpu_none_mask);
	set_cpu_possible(0, true);

	__cpu_number_map[0] = 0;
	__cpu_logical_map[0] = 0;

	/* For unified kernel, NR_CPUS is the maximum possible value,
	 * loongson_sysconf.nr_cpus is the really present value */
	for (i = 1, num = 0; i < loongson_sysconf.nr_cpus; i++) {
		set_cpu_possible(i, true);
		__cpu_number_map[i] = ++num;
		__cpu_logical_map[num] = i;
	}
	pr_info("Detected %i available secondary CPU(s)\n", num);
}

static void __init loongson3_prepare_cpus(unsigned int max_cpus)
{
	init_cpu_present(cpu_possible_mask);
	per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
}

/*
 * Setup the PC, SP, and GP of a secondary processor and start it runing!
 */
static void loongson3_boot_secondary(int cpu, struct task_struct *idle)
{
	unsigned long startargs[4];

	pr_info("Booting CPU#%d...\n", cpu);

	/* startargs[] are initial PC, SP and GP for secondary CPU */
	startargs[0] = (unsigned long)&smp_bootstrap;
	startargs[1] = (unsigned long)__KSTK_TOS(idle);
	startargs[2] = (unsigned long)task_thread_info(idle);
	startargs[3] = 0;

	pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
			cpu, startargs[0], startargs[1], startargs[2]);

	loongson3_ipi_write64(startargs[3], (void *)(ipi_mailbox_buf[cpu]+0x18));
	loongson3_ipi_write64(startargs[2], (void *)(ipi_mailbox_buf[cpu]+0x10));
	loongson3_ipi_write64(startargs[1], (void *)(ipi_mailbox_buf[cpu]+0x8));
	loongson3_ipi_write64(startargs[0], (void *)(ipi_mailbox_buf[cpu]+0x0));
}

#ifdef CONFIG_HOTPLUG_CPU

static int loongson3_cpu_disable(void)
{
	unsigned long flags;
	unsigned int cpu = smp_processor_id();

	if (cpu == 0)
		return -EBUSY;

	set_cpu_online(cpu, false);
	cpu_clear(cpu, cpu_callin_map);
	local_irq_save(flags);
	fixup_irqs();
	local_irq_restore(flags);
	flush_cache_all();
	local_flush_tlb_all();

	return 0;
}


static void loongson3_cpu_die(unsigned int cpu)
{
	while (per_cpu(cpu_state, cpu) != CPU_DEAD)
		cpu_relax();

	mb();
}

/* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and
 * flush all L1 entries at first. Then, another core (usually Core 0) can
 * safely disable the clock of the target core. loongson3_play_dead() is
 * called via CKSEG1 (uncached and unmmaped) */
static void loongson3_play_dead(int *state_addr)
{
	register int val;
	register long cpuid, core, node, count;
	register void *addr, *base, *initfunc;

	__asm__ __volatile__(
		"   .set push                     \n"
		"   .set noreorder                \n"
		"   li %[addr], 0x80000000        \n" /* KSEG0 */
		"1: cache 0, 0(%[addr])           \n" /* flush L1 ICache */
		"   cache 0, 1(%[addr])           \n"
		"   cache 0, 2(%[addr])           \n"
		"   cache 0, 3(%[addr])           \n"
		"   cache 1, 0(%[addr])           \n" /* flush L1 DCache */
		"   cache 1, 1(%[addr])           \n"
		"   cache 1, 2(%[addr])           \n"
		"   cache 1, 3(%[addr])           \n"
		"   addiu %[sets], %[sets], -1    \n"
		"   bnez  %[sets], 1b             \n"
		"   addiu %[addr], %[addr], 0x20  \n"
		"   li    %[val], 0x7             \n" /* *state_addr = CPU_DEAD; */
		"   sw    %[val], (%[state_addr]) \n"
		"   sync                          \n"
		"   cache 21, (%[state_addr])     \n" /* flush entry of *state_addr */
		"   .set pop                      \n"
		: [addr] "=&r" (addr), [val] "=&r" (val)
		: [state_addr] "r" (state_addr),
		  [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));

	__asm__ __volatile__(
		"   .set push                         \n"
		"   .set noreorder                    \n"
		"   .set mips64                       \n"
		"   mfc0  %[cpuid], $15, 1            \n"
		"   andi  %[cpuid], 0x3ff             \n"
		"   dli   %[base], 0x900000003ff01000 \n"
		"   andi  %[core], %[cpuid], 0x3      \n"
		"   sll   %[core], 8                  \n" /* get core id */
		"   or    %[base], %[base], %[core]   \n"
		"   andi  %[node], %[cpuid], 0xc      \n"
		"   dsll  %[node], 42                 \n" /* get node id */
		"   or    %[base], %[base], %[node]   \n"
		"1: li    %[count], 0x100             \n" /* wait for init loop */
		"2: bnez  %[count], 2b                \n" /* limit mailbox access */
		"   addiu %[count], -1                \n"
		"   ld    %[initfunc], 0x20(%[base])  \n" /* get PC via mailbox */
		"   beqz  %[initfunc], 1b             \n"
		"   nop                               \n"
		"   ld    $sp, 0x28(%[base])          \n" /* get SP via mailbox */
		"   ld    $gp, 0x30(%[base])          \n" /* get GP via mailbox */
		"   ld    $a1, 0x38(%[base])          \n"
		"   jr    %[initfunc]                 \n" /* jump to initial PC */
		"   nop                               \n"
		"   .set pop                          \n"
		: [core] "=&r" (core), [node] "=&r" (node),
		  [base] "=&r" (base), [cpuid] "=&r" (cpuid),
		  [count] "=&r" (count), [initfunc] "=&r" (initfunc)
		: /* No Input */
		: "a1");
}

void play_dead(void)
{
	int *state_addr;
	unsigned int cpu = smp_processor_id();
	void (*play_dead_at_ckseg1)(int *);

	idle_task_exit();
	play_dead_at_ckseg1 =
		(void *)CKSEG1ADDR((unsigned long)loongson3_play_dead);
	state_addr = &per_cpu(cpu_state, cpu);
	mb();
	play_dead_at_ckseg1(state_addr);
}

#define CPU_POST_DEAD_FROZEN	(CPU_POST_DEAD | CPU_TASKS_FROZEN)
static int loongson3_cpu_callback(struct notifier_block *nfb,
	unsigned long action, void *hcpu)
{
	unsigned int cpu = (unsigned long)hcpu;
	uint64_t core_id = cpu_data[cpu].core;
	uint64_t package_id = cpu_data[cpu].package;

	switch (action) {
	case CPU_POST_DEAD:
	case CPU_POST_DEAD_FROZEN:
		pr_info("Disable clock for CPU#%d\n", cpu);
		LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id));
		break;
	case CPU_UP_PREPARE:
	case CPU_UP_PREPARE_FROZEN:
		pr_info("Enable clock for CPU#%d\n", cpu);
		LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id);
		break;
	}

	return NOTIFY_OK;
}

static int register_loongson3_notifier(void)
{
	hotcpu_notifier(loongson3_cpu_callback, 0);
	return 0;
}
early_initcall(register_loongson3_notifier);

#endif

struct plat_smp_ops loongson3_smp_ops = {
	.send_ipi_single = loongson3_send_ipi_single,
	.send_ipi_mask = loongson3_send_ipi_mask,
	.init_secondary = loongson3_init_secondary,
	.smp_finish = loongson3_smp_finish,
	.boot_secondary = loongson3_boot_secondary,
	.smp_setup = loongson3_smp_setup,
	.prepare_cpus = loongson3_prepare_cpus,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_disable = loongson3_cpu_disable,
	.cpu_die = loongson3_cpu_die,
#endif
};
Commit	Line	Data
300459d5 HC	1	/*
	2	* Copyright (C) 2010, 2011, 2012, Lemote, Inc.
	3	* Author: Chen Huacai, chenhc@lemote.com
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
	17	#include <linux/init.h>
	18	#include <linux/cpu.h>
	19	#include <linux/sched.h>
	20	#include <linux/smp.h>
	21	#include <linux/cpufreq.h>
	22	#include <asm/processor.h>
	23	#include <asm/time.h>
	24	#include <asm/clock.h>
	25	#include <asm/tlbflush.h>
c4a987db	26	#include <asm/cacheflush.h>
300459d5 HC	27	#include <loongson.h>
	28
	29	#include "smp.h"
	30
c4a987db HC	31	DEFINE_PER_CPU(int, cpu_state);
	32	DEFINE_PER_CPU(uint32_t, core0_c0count);
	33
300459d5 HC	34	/* read a 32bit value from ipi register */
	35	#define loongson3_ipi_read32(addr) readl(addr)
	36	/* read a 64bit value from ipi register */
	37	#define loongson3_ipi_read64(addr) readq(addr)
	38	/* write a 32bit value to ipi register */
	39	#define loongson3_ipi_write32(action, addr) \
	40	do { \
	41	writel(action, addr); \
	42	__wbflush(); \
	43	} while (0)
	44	/* write a 64bit value to ipi register */
	45	#define loongson3_ipi_write64(action, addr) \
	46	do { \
	47	writeq(action, addr); \
	48	__wbflush(); \
	49	} while (0)
	50
	51	static void *ipi_set0_regs[] = {
	52	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0),
	53	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0),
	54	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0),
	55	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0),
	56	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0),
	57	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0),
	58	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0),
	59	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0),
	60	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0),
	61	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0),
	62	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0),
	63	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0),
	64	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0),
	65	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0),
	66	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0),
	67	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0),
	68	};
	69
	70	static void *ipi_clear0_regs[] = {
	71	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0),
	72	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0),
	73	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0),
	74	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0),
	75	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0),
	76	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0),
	77	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0),
	78	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0),
	79	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0),
	80	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0),
	81	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0),
	82	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0),
	83	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0),
	84	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0),
	85	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0),
	86	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0),
	87	};
	88
	89	static void *ipi_status0_regs[] = {
	90	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0),
	91	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0),
	92	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0),
	93	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0),
	94	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0),
	95	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0),
	96	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0),
	97	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0),
98	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0),
99	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0),
100	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0),
101	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0),
102	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0),
103	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0),
104	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0),
105	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0),
106	};
107
108	static void *ipi_en0_regs[] = {
109	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0),
110	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0),
111	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0),
112	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0),
113	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0),
114	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0),
115	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0),
116	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0),
117	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0),
118	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0),
119	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0),
120	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0),
121	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0),
122	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0),
123	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0),
124	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0),
125	};
126
127	static void *ipi_mailbox_buf[] = {
128	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF),
129	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF),
130	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF),
131	(void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF),
132	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF),
133	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF),
134	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF),
135	(void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF),
136	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF),
137	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF),
138	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF),
139	(void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF),
140	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF),
141	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF),
142	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF),
143	(void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF),
144	};
145
146	/*
147	* Simple enough, just poke the appropriate ipi register
148	*/
149	static void loongson3_send_ipi_single(int cpu, unsigned int action)
150	{
151	loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]);
152	}
153
154	static void
155	loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
156	{
157	unsigned int i;
158
159	for_each_cpu(i, mask)
160	loongson3_ipi_write32((u32)action, ipi_set0_regs[i]);
161	}
162
163	void loongson3_ipi_interrupt(struct pt_regs *regs)
164	{
c4a987db HC	165	int i, cpu = smp_processor_id();
c4a987db HC	166	unsigned int action, c0count;
300459d5 HC	167
	168	/* Load the ipi register to figure out what we're supposed to do */
	169	action = loongson3_ipi_read32(ipi_status0_regs[cpu]);
	170
	171	/* Clear the ipi register to clear the interrupt */
	172	loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu]);
	173
	174	if (action & SMP_RESCHEDULE_YOURSELF)
	175	scheduler_ipi();
	176
	177	if (action & SMP_CALL_FUNCTION)
	178	smp_call_function_interrupt();
c4a987db HC	179
	180	if (action & SMP_ASK_C0COUNT) {
	181	BUG_ON(cpu != 0);
	182	c0count = read_c0_count();
	183	for (i = 1; i < loongson_sysconf.nr_cpus; i++)
	184	per_cpu(core0_c0count, i) = c0count;
	185	}
300459d5 HC	186	}
300459d5 HC	187
c4a987db	188	#define MAX_LOOPS 1111
300459d5 HC	189	/*
	190	* SMP init and finish on secondary CPUs
	191	*/
	192	static void loongson3_init_secondary(void)
	193	{
	194	int i;
c4a987db HC	195	uint32_t initcount;
c4a987db HC	196	unsigned int cpu = smp_processor_id();
300459d5 HC	197	unsigned int imask = STATUSF_IP7 \| STATUSF_IP6 \|
	198	STATUSF_IP3 \| STATUSF_IP2;
	199
	200	/* Set interrupt mask, but don't enable */
	201	change_c0_status(ST0_IM, imask);
	202
	203	for (i = 0; i < loongson_sysconf.nr_cpus; i++)
	204	loongson3_ipi_write32(0xffffffff, ipi_en0_regs[i]);
c4a987db	205
c4617318 HC	206	cpu_data[cpu].package = cpu / loongson_sysconf.cores_per_package;
c4617318 HC	207	cpu_data[cpu].core = cpu % loongson_sysconf.cores_per_package;
c4a987db HC	208	per_cpu(cpu_state, cpu) = CPU_ONLINE;
	209
	210	i = 0;
	211	__get_cpu_var(core0_c0count) = 0;
	212	loongson3_send_ipi_single(0, SMP_ASK_C0COUNT);
	213	while (!__get_cpu_var(core0_c0count)) {
	214	i++;
	215	cpu_relax();
	216	}
	217
	218	if (i > MAX_LOOPS)
	219	i = MAX_LOOPS;
	220	initcount = __get_cpu_var(core0_c0count) + i;
	221	write_c0_count(initcount);
300459d5 HC	222	}
	223
	224	static void loongson3_smp_finish(void)
	225	{
	226	write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
	227	local_irq_enable();
	228	loongson3_ipi_write64(0,
	229	(void *)(ipi_mailbox_buf[smp_processor_id()]+0x0));
	230	pr_info("CPU#%d finished, CP0_ST=%x\n",
	231	smp_processor_id(), read_c0_status());
	232	}
	233
	234	static void __init loongson3_smp_setup(void)
	235	{
	236	int i, num;
	237
	238	init_cpu_possible(cpu_none_mask);
	239	set_cpu_possible(0, true);
	240
	241	__cpu_number_map[0] = 0;
	242	__cpu_logical_map[0] = 0;
	243
	244	/* For unified kernel, NR_CPUS is the maximum possible value,
	245	* loongson_sysconf.nr_cpus is the really present value */
	246	for (i = 1, num = 0; i < loongson_sysconf.nr_cpus; i++) {
	247	set_cpu_possible(i, true);
	248	__cpu_number_map[i] = ++num;
	249	__cpu_logical_map[num] = i;
	250	}
	251	pr_info("Detected %i available secondary CPU(s)\n", num);
	252	}
	253
	254	static void __init loongson3_prepare_cpus(unsigned int max_cpus)
	255	{
c4a987db HC	256	init_cpu_present(cpu_possible_mask);
c4a987db HC	257	per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
300459d5 HC	258	}
	259
	260	/*
	261	* Setup the PC, SP, and GP of a secondary processor and start it runing!
	262	*/
	263	static void loongson3_boot_secondary(int cpu, struct task_struct *idle)
	264	{
	265	unsigned long startargs[4];
	266
	267	pr_info("Booting CPU#%d...\n", cpu);
	268
	269	/* startargs[] are initial PC, SP and GP for secondary CPU */
	270	startargs[0] = (unsigned long)&smp_bootstrap;
	271	startargs[1] = (unsigned long)__KSTK_TOS(idle);
	272	startargs[2] = (unsigned long)task_thread_info(idle);
	273	startargs[3] = 0;
	274
	275	pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
	276	cpu, startargs[0], startargs[1], startargs[2]);
	277
	278	loongson3_ipi_write64(startargs[3], (void *)(ipi_mailbox_buf[cpu]+0x18));
	279	loongson3_ipi_write64(startargs[2], (void *)(ipi_mailbox_buf[cpu]+0x10));
	280	loongson3_ipi_write64(startargs[1], (void *)(ipi_mailbox_buf[cpu]+0x8));
	281	loongson3_ipi_write64(startargs[0], (void *)(ipi_mailbox_buf[cpu]+0x0));
	282	}
	283
c4a987db HC	284	#ifdef CONFIG_HOTPLUG_CPU
	285
	286	static int loongson3_cpu_disable(void)
	287	{
	288	unsigned long flags;
	289	unsigned int cpu = smp_processor_id();
	290
	291	if (cpu == 0)
	292	return -EBUSY;
	293
	294	set_cpu_online(cpu, false);
	295	cpu_clear(cpu, cpu_callin_map);
	296	local_irq_save(flags);
	297	fixup_irqs();
	298	local_irq_restore(flags);
	299	flush_cache_all();
	300	local_flush_tlb_all();
	301
	302	return 0;
	303	}
	304
	305
	306	static void loongson3_cpu_die(unsigned int cpu)
	307	{
	308	while (per_cpu(cpu_state, cpu) != CPU_DEAD)
	309	cpu_relax();
	310
	311	mb();
	312	}
	313
	314	/* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and
	315	* flush all L1 entries at first. Then, another core (usually Core 0) can
	316	* safely disable the clock of the target core. loongson3_play_dead() is
	317	* called via CKSEG1 (uncached and unmmaped) */
	318	static void loongson3_play_dead(int *state_addr)
	319	{
	320	register int val;
	321	register long cpuid, core, node, count;
	322	register void addr, base, *initfunc;
	323
	324	__asm__ __volatile__(
	325	" .set push \n"
	326	" .set noreorder \n"
	327	" li %[addr], 0x80000000 \n" /* KSEG0 */
	328	"1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
	329	" cache 0, 1(%[addr]) \n"
	330	" cache 0, 2(%[addr]) \n"
	331	" cache 0, 3(%[addr]) \n"
	332	" cache 1, 0(%[addr]) \n" /* flush L1 DCache */
	333	" cache 1, 1(%[addr]) \n"
	334	" cache 1, 2(%[addr]) \n"
	335	" cache 1, 3(%[addr]) \n"
	336	" addiu %[sets], %[sets], -1 \n"
	337	" bnez %[sets], 1b \n"
	338	" addiu %[addr], %[addr], 0x20 \n"
	339	" li %[val], 0x7 \n" /* state_addr = CPU_DEAD; /
	340	" sw %[val], (%[state_addr]) \n"
	341	" sync \n"
	342	" cache 21, (%[state_addr]) \n" /* flush entry of state_addr /
	343	" .set pop \n"
	344	: [addr] "=&r" (addr), [val] "=&r" (val)
	345	: [state_addr] "r" (state_addr),
	346	[sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
	347
348	__asm__ __volatile__(
349	" .set push \n"
350	" .set noreorder \n"
351	" .set mips64 \n"
352	" mfc0 %[cpuid], $15, 1 \n"
353	" andi %[cpuid], 0x3ff \n"
354	" dli %[base], 0x900000003ff01000 \n"
355	" andi %[core], %[cpuid], 0x3 \n"
356	" sll %[core], 8 \n" /* get core id */
357	" or %[base], %[base], %[core] \n"
358	" andi %[node], %[cpuid], 0xc \n"
359	" dsll %[node], 42 \n" /* get node id */
360	" or %[base], %[base], %[node] \n"
361	"1: li %[count], 0x100 \n" /* wait for init loop */
362	"2: bnez %[count], 2b \n" /* limit mailbox access */
363	" addiu %[count], -1 \n"
364	" ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
365	" beqz %[initfunc], 1b \n"
366	" nop \n"
367	" ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
368	" ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
369	" ld $a1, 0x38(%[base]) \n"
370	" jr %[initfunc] \n" /* jump to initial PC */
371	" nop \n"
372	" .set pop \n"
373	: [core] "=&r" (core), [node] "=&r" (node),
374	[base] "=&r" (base), [cpuid] "=&r" (cpuid),
375	[count] "=&r" (count), [initfunc] "=&r" (initfunc)
376	: /* No Input */
377	: "a1");
378	}
379
380	void play_dead(void)
381	{
382	int *state_addr;
383	unsigned int cpu = smp_processor_id();
384	void (play_dead_at_ckseg1)(int );
385
386	idle_task_exit();
387	play_dead_at_ckseg1 =
388	(void *)CKSEG1ADDR((unsigned long)loongson3_play_dead);
389	state_addr = &per_cpu(cpu_state, cpu);
390	mb();
391	play_dead_at_ckseg1(state_addr);
392	}
393
394	#define CPU_POST_DEAD_FROZEN (CPU_POST_DEAD \| CPU_TASKS_FROZEN)
395	static int loongson3_cpu_callback(struct notifier_block *nfb,
396	unsigned long action, void *hcpu)
397	{
398	unsigned int cpu = (unsigned long)hcpu;
c4617318 HC	399	uint64_t core_id = cpu_data[cpu].core;
c4617318 HC	400	uint64_t package_id = cpu_data[cpu].package;
c4a987db HC	401
	402	switch (action) {
	403	case CPU_POST_DEAD:
	404	case CPU_POST_DEAD_FROZEN:
	405	pr_info("Disable clock for CPU#%d\n", cpu);
c4617318	406	LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id));
c4a987db HC	407	break;
	408	case CPU_UP_PREPARE:
	409	case CPU_UP_PREPARE_FROZEN:
	410	pr_info("Enable clock for CPU#%d\n", cpu);
c4617318	411	LOONGSON_CHIPCFG(package_id) \|= 1 << (12 + core_id);
c4a987db HC	412	break;
	413	}
	414
	415	return NOTIFY_OK;
	416	}
	417
	418	static int register_loongson3_notifier(void)
	419	{
	420	hotcpu_notifier(loongson3_cpu_callback, 0);
	421	return 0;
	422	}
	423	early_initcall(register_loongson3_notifier);
	424
	425	#endif
	426
300459d5 HC	427	struct plat_smp_ops loongson3_smp_ops = {
	428	.send_ipi_single = loongson3_send_ipi_single,
	429	.send_ipi_mask = loongson3_send_ipi_mask,
	430	.init_secondary = loongson3_init_secondary,
	431	.smp_finish = loongson3_smp_finish,
300459d5 HC	432	.boot_secondary = loongson3_boot_secondary,
	433	.smp_setup = loongson3_smp_setup,
	434	.prepare_cpus = loongson3_prepare_cpus,
c4a987db HC	435	#ifdef CONFIG_HOTPLUG_CPU
	436	.cpu_disable = loongson3_cpu_disable,
	437	.cpu_die = loongson3_cpu_die,
	438	#endif
300459d5	439	};