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Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
42d226c7 | 2 | /* |
42d226c7 ST |
3 | * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology |
4 | * Author: Fuxin Zhang, zhangfx@lemote.com | |
42d226c7 | 5 | */ |
42d226c7 | 6 | #include <linux/pci.h> |
42d226c7 | 7 | |
5e983ff6 WZ |
8 | #include <pci.h> |
9 | #include <loongson.h> | |
1a08f152 | 10 | #include <boot_param.h> |
42d226c7 | 11 | |
85749d24 | 12 | static struct resource loongson_pci_mem_resource = { |
70342287 RB |
13 | .name = "pci memory space", |
14 | .start = LOONGSON_PCI_MEM_START, | |
15 | .end = LOONGSON_PCI_MEM_END, | |
16 | .flags = IORESOURCE_MEM, | |
42d226c7 ST |
17 | }; |
18 | ||
85749d24 | 19 | static struct resource loongson_pci_io_resource = { |
70342287 RB |
20 | .name = "pci io space", |
21 | .start = LOONGSON_PCI_IO_START, | |
22 | .end = IO_SPACE_LIMIT, | |
23 | .flags = IORESOURCE_IO, | |
42d226c7 ST |
24 | }; |
25 | ||
85749d24 | 26 | static struct pci_controller loongson_pci_controller = { |
70342287 RB |
27 | .pci_ops = &loongson_pci_ops, |
28 | .io_resource = &loongson_pci_io_resource, | |
29 | .mem_resource = &loongson_pci_mem_resource, | |
30 | .mem_offset = 0x00000000UL, | |
31 | .io_offset = 0x00000000UL, | |
42d226c7 ST |
32 | }; |
33 | ||
f7face03 | 34 | static void __init setup_pcimap(void) |
42d226c7 ST |
35 | { |
36 | /* | |
f7face03 | 37 | * local to PCI mapping for CPU accessing PCI space |
42d226c7 | 38 | * CPU address space [256M,448M] is window for accessing pci space |
f7face03 WZ |
39 | * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M] |
40 | * | |
41 | * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 | |
70342287 | 42 | * [<2G] [384M,448M] [320M,384M] [0M,64M] |
42d226c7 | 43 | */ |
e2fee572 WZ |
44 | LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 | |
45 | LOONGSON_PCIMAP_WIN(2, LOONGSON_PCILO2_BASE) | | |
46 | LOONGSON_PCIMAP_WIN(1, LOONGSON_PCILO1_BASE) | | |
47 | LOONGSON_PCIMAP_WIN(0, 0); | |
42d226c7 ST |
48 | |
49 | /* | |
f7face03 | 50 | * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] |
42d226c7 | 51 | */ |
e2fee572 | 52 | LOONGSON_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ |
f7face03 WZ |
53 | /* size: 256M, burst transmission, pre-fetch enable, 64bit */ |
54 | LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; | |
55 | LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; | |
56 | LOONGSON_PCI_HIT1_SEL_L = 0x00000006ul; /* set this BAR as invalid */ | |
57 | LOONGSON_PCI_HIT1_SEL_H = 0x00000000ul; | |
58 | LOONGSON_PCI_HIT2_SEL_L = 0x00000006ul; /* set this BAR as invalid */ | |
59 | LOONGSON_PCI_HIT2_SEL_H = 0x00000000ul; | |
60 | ||
61 | /* avoid deadlock of PCI reading/writing lock operation */ | |
62 | LOONGSON_PCI_ISR4C = 0xd2000001ul; | |
42d226c7 | 63 | |
f7face03 WZ |
64 | /* can not change gnt to break pci transfer when device's gnt not |
65 | deassert for some broken device */ | |
66 | LOONGSON_PXARB_CFG = 0x00fe0105ul; | |
6f7a251a | 67 | |
55045ff5 | 68 | #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG |
6f7a251a WZ |
69 | /* |
70 | * set cpu addr window2 to map CPU address space to PCI address space | |
71 | */ | |
72 | LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC, | |
73 | LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE); | |
74 | #endif | |
42d226c7 ST |
75 | } |
76 | ||
9c057b3e HC |
77 | extern int sbx00_acpi_init(void); |
78 | ||
42d226c7 ST |
79 | static int __init pcibios_init(void) |
80 | { | |
f7face03 | 81 | setup_pcimap(); |
3a63913f | 82 | |
85749d24 | 83 | loongson_pci_controller.io_map_base = mips_io_port_base; |
1a08f152 HC |
84 | #ifdef CONFIG_LEFI_FIRMWARE_INTERFACE |
85 | loongson_pci_mem_resource.start = loongson_sysconf.pci_mem_start_addr; | |
86 | loongson_pci_mem_resource.end = loongson_sysconf.pci_mem_end_addr; | |
87 | #endif | |
85749d24 | 88 | register_pci_controller(&loongson_pci_controller); |
42d226c7 | 89 | |
9c057b3e HC |
90 | #ifdef CONFIG_CPU_LOONGSON3 |
91 | sbx00_acpi_init(); | |
92 | #endif | |
93 | ||
42d226c7 ST |
94 | return 0; |
95 | } | |
96 | ||
97 | arch_initcall(pcibios_init); |