[mirror_ubuntu-artful-kernel.git] / arch / mips / loongson64 / common / uart_base.c

/*
 * Copyright (C) 2009 Lemote Inc.
 * Author: Wu Zhangjin, wuzhangjin@gmail.com
 *
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/export.h>
#include <asm/bootinfo.h>

#include <loongson.h>

/* raw */
unsigned long loongson_uart_base[MAX_UARTS] = {};
/* ioremapped */
unsigned long _loongson_uart_base[MAX_UARTS] = {};

EXPORT_SYMBOL(loongson_uart_base);
EXPORT_SYMBOL(_loongson_uart_base);

void prom_init_loongson_uart_base(void)
{
	switch (mips_machtype) {
	case MACH_LOONGSON_GENERIC:
		/* The CPU provided serial port (CPU) */
		loongson_uart_base[0] = LOONGSON_REG_BASE + 0x1e0;
		break;
	case MACH_LEMOTE_FL2E:
		loongson_uart_base[0] = LOONGSON_PCIIO_BASE + 0x3f8;
		break;
	case MACH_LEMOTE_FL2F:
	case MACH_LEMOTE_LL2F:
		loongson_uart_base[0] = LOONGSON_PCIIO_BASE + 0x2f8;
		break;
	case MACH_LEMOTE_ML2F7:
	case MACH_LEMOTE_YL2F89:
	case MACH_DEXXON_GDIUM2F10:
	case MACH_LEMOTE_NAS:
	default:
		/* The CPU provided serial port (LPC) */
		loongson_uart_base[0] = LOONGSON_LIO1_BASE + 0x3f8;
		break;
	}

	_loongson_uart_base[0] =
		(unsigned long)ioremap_nocache(loongson_uart_base[0], 8);
}
Commit	Line	Data
a3ed4951 WZ	1	/*
a3ed4951 WZ	2	* Copyright (C) 2009 Lemote Inc.
f7a904df	3	* Author: Wu Zhangjin, wuzhangjin@gmail.com
a3ed4951	4	*
70342287 RB	5	* This program is free software; you can redistribute it and/or modify it
70342287 RB	6	* under the terms of the GNU General Public License as published by the
a3ed4951 WZ	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*/
	10
26dd3e4f	11	#include <linux/export.h>
a3ed4951 WZ	12	#include <asm/bootinfo.h>
	13
	14	#include <loongson.h>
	15
c3d8d850	16	/* raw */
3adeb256 HC	17	unsigned long loongson_uart_base[MAX_UARTS] = {};
	18	/* ioremapped */
	19	unsigned long _loongson_uart_base[MAX_UARTS] = {};
	20
c3d8d850	21	EXPORT_SYMBOL(loongson_uart_base);
3adeb256	22	EXPORT_SYMBOL(_loongson_uart_base);
a3ed4951	23
c3d8d850	24	void prom_init_loongson_uart_base(void)
a3ed4951	25	{
c3d8d850	26	switch (mips_machtype) {
3adeb256 HC	27	case MACH_LOONGSON_GENERIC:
	28	/* The CPU provided serial port (CPU) */
	29	loongson_uart_base[0] = LOONGSON_REG_BASE + 0x1e0;
	30	break;
c3d8d850	31	case MACH_LEMOTE_FL2E:
3adeb256	32	loongson_uart_base[0] = LOONGSON_PCIIO_BASE + 0x3f8;
c3d8d850 WZ	33	break;
	34	case MACH_LEMOTE_FL2F:
	35	case MACH_LEMOTE_LL2F:
3adeb256	36	loongson_uart_base[0] = LOONGSON_PCIIO_BASE + 0x2f8;
c3d8d850 WZ	37	break;
	38	case MACH_LEMOTE_ML2F7:
	39	case MACH_LEMOTE_YL2F89:
	40	case MACH_DEXXON_GDIUM2F10:
	41	case MACH_LEMOTE_NAS:
	42	default:
7546d2f4	43	/* The CPU provided serial port (LPC) */
3adeb256	44	loongson_uart_base[0] = LOONGSON_LIO1_BASE + 0x3f8;
7546d2f4	45	break;
c3d8d850 WZ	46	}
c3d8d850 WZ	47
3adeb256 HC	48	_loongson_uart_base[0] =
3adeb256 HC	49	(unsigned long)ioremap_nocache(loongson_uart_base[0], 8);
a3ed4951	50	}