[mirror_ubuntu-artful-kernel.git] / arch / mips / loongson64 / loongson-3 / irq.c

#include <loongson.h>
#include <irq.h>
#include <linux/interrupt.h>
#include <linux/init.h>

#include <asm/irq_cpu.h>
#include <asm/i8259.h>
#include <asm/mipsregs.h>

#include "smp.h"

extern void loongson3_send_irq_by_ipi(int cpu, int irqs);

unsigned int irq_cpu[16] = {[0 ... 15] = -1};
unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
unsigned int local_irq = 1<<0 | 1<<1 | 1<<2 | 1<<7 | 1<<8 | 1<<12;

int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
			  bool force)
{
	unsigned int cpu;
	struct cpumask new_affinity;

	/* I/O devices are connected on package-0 */
	cpumask_copy(&new_affinity, affinity);
	for_each_cpu(cpu, affinity)
		if (cpu_data[cpu].package > 0)
			cpumask_clear_cpu(cpu, &new_affinity);

	if (cpumask_empty(&new_affinity))
		return -EINVAL;

	cpumask_copy(d->common->affinity, &new_affinity);

	return IRQ_SET_MASK_OK_NOCOPY;
}

static void ht_irqdispatch(void)
{
	unsigned int i, irq;
	struct irq_data *irqd;
	struct cpumask affinity;

	irq = LOONGSON_HT1_INT_VECTOR(0);
	LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */

	for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
		if (!(irq & (0x1 << ht_irq[i])))
			continue;

		/* handled by local core */
		if (local_irq & (0x1 << ht_irq[i])) {
			do_IRQ(ht_irq[i]);
			continue;
		}

		irqd = irq_get_irq_data(ht_irq[i]);
		cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask);
		if (cpumask_empty(&affinity)) {
			do_IRQ(ht_irq[i]);
			continue;
		}

		irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity);
		if (irq_cpu[ht_irq[i]] >= nr_cpu_ids)
			irq_cpu[ht_irq[i]] = cpumask_first(&affinity);

		if (irq_cpu[ht_irq[i]] == 0) {
			do_IRQ(ht_irq[i]);
			continue;
		}

		/* balanced by other cores */
		loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i]));
	}
}

#define UNUSED_IPS (CAUSEF_IP5 | CAUSEF_IP4 | CAUSEF_IP1 | CAUSEF_IP0)

void mach_irq_dispatch(unsigned int pending)
{
	if (pending & CAUSEF_IP7)
		do_IRQ(LOONGSON_TIMER_IRQ);
#if defined(CONFIG_SMP)
	if (pending & CAUSEF_IP6)
		loongson3_ipi_interrupt(NULL);
#endif
	if (pending & CAUSEF_IP3)
		ht_irqdispatch();
	if (pending & CAUSEF_IP2)
		do_IRQ(LOONGSON_UART_IRQ);
	if (pending & UNUSED_IPS) {
		pr_err("%s : spurious interrupt\n", __func__);
		spurious_interrupt();
	}
}

static struct irqaction cascade_irqaction = {
	.handler = no_action,
	.flags = IRQF_NO_SUSPEND,
	.name = "cascade",
};

static inline void mask_loongson_irq(struct irq_data *d)
{
	clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
	irq_disable_hazard();

	/* Workaround: UART IRQ may deliver to any core */
	if (d->irq == LOONGSON_UART_IRQ) {
		int cpu = smp_processor_id();
		int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
		int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
		u64 intenclr_addr = smp_group[node_id] |
			(u64)(&LOONGSON_INT_ROUTER_INTENCLR);
		u64 introuter_lpc_addr = smp_group[node_id] |
			(u64)(&LOONGSON_INT_ROUTER_LPC);

		*(volatile u32 *)intenclr_addr = 1 << 10;
		*(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
	}
}

static inline void unmask_loongson_irq(struct irq_data *d)
{
	/* Workaround: UART IRQ may deliver to any core */
	if (d->irq == LOONGSON_UART_IRQ) {
		int cpu = smp_processor_id();
		int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
		int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
		u64 intenset_addr = smp_group[node_id] |
			(u64)(&LOONGSON_INT_ROUTER_INTENSET);
		u64 introuter_lpc_addr = smp_group[node_id] |
			(u64)(&LOONGSON_INT_ROUTER_LPC);

		*(volatile u32 *)intenset_addr = 1 << 10;
		*(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
	}

	set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
	irq_enable_hazard();
}

 /* For MIPS IRQs which shared by all cores */
static struct irq_chip loongson_irq_chip = {
	.name		= "Loongson",
	.irq_ack	= mask_loongson_irq,
	.irq_mask	= mask_loongson_irq,
	.irq_mask_ack	= mask_loongson_irq,
	.irq_unmask	= unmask_loongson_irq,
	.irq_eoi	= unmask_loongson_irq,
};

void irq_router_init(void)
{
	int i;

	/* route LPC int to cpu core0 int 0 */
	LOONGSON_INT_ROUTER_LPC =
		LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0);
	/* route HT1 int0 ~ int7 to cpu core0 INT1*/
	for (i = 0; i < 8; i++)
		LOONGSON_INT_ROUTER_HT1(i) =
			LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1);
	/* enable HT1 interrupt */
	LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
	/* enable router interrupt intenset */
	LOONGSON_INT_ROUTER_INTENSET =
		LOONGSON_INT_ROUTER_INTEN | (0xffff << 16) | 0x1 << 10;
}

void __init mach_init_irq(void)
{
	struct irq_chip *chip;

	clear_c0_status(ST0_IM | ST0_BEV);

	irq_router_init();
	mips_cpu_irq_init();
	init_i8259_irqs();
	chip = irq_get_chip(I8259A_IRQ_BASE);
	chip->irq_set_affinity = plat_set_irq_affinity;

	irq_set_chip_and_handler(LOONGSON_UART_IRQ,
			&loongson_irq_chip, handle_level_irq);

	/* setup HT1 irq */
	setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);

	set_c0_status(STATUSF_IP2 | STATUSF_IP6);
}

#ifdef CONFIG_HOTPLUG_CPU

void fixup_irqs(void)
{
	irq_cpu_offline();
	clear_c0_status(ST0_IM);
}

#endif
Commit	Line	Data
d788bfa9 HC	1	#include <loongson.h>
	2	#include <irq.h>
	3	#include <linux/interrupt.h>
26dd3e4f	4	#include <linux/init.h>
d788bfa9 HC	5
	6	#include <asm/irq_cpu.h>
	7	#include <asm/i8259.h>
	8	#include <asm/mipsregs.h>
	9
e7841be5 HC	10	#include "smp.h"
e7841be5 HC	11
e1b88ca8	12	extern void loongson3_send_irq_by_ipi(int cpu, int irqs);
ecc38a09 HC	13
ecc38a09 HC	14	unsigned int irq_cpu[16] = {[0 ... 15] = -1};
e292ccde	15	unsigned int ht_irq[] = {0, 1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
e1b88ca8	16	unsigned int local_irq = 1<<0 \| 1<<1 \| 1<<2 \| 1<<7 \| 1<<8 \| 1<<12;
d788bfa9	17
ecc38a09 HC	18	int plat_set_irq_affinity(struct irq_data d, const struct cpumask affinity,
	19	bool force)
	20	{
	21	unsigned int cpu;
	22	struct cpumask new_affinity;
	23
	24	/* I/O devices are connected on package-0 */
	25	cpumask_copy(&new_affinity, affinity);
	26	for_each_cpu(cpu, affinity)
	27	if (cpu_data[cpu].package > 0)
	28	cpumask_clear_cpu(cpu, &new_affinity);
	29
	30	if (cpumask_empty(&new_affinity))
	31	return -EINVAL;
	32
	33	cpumask_copy(d->common->affinity, &new_affinity);
	34
	35	return IRQ_SET_MASK_OK_NOCOPY;
	36	}
	37
d788bfa9 HC	38	static void ht_irqdispatch(void)
d788bfa9 HC	39	{
ecc38a09 HC	40	unsigned int i, irq;
	41	struct irq_data *irqd;
	42	struct cpumask affinity;
d788bfa9 HC	43
	44	irq = LOONGSON_HT1_INT_VECTOR(0);
	45	LOONGSON_HT1_INT_VECTOR(0) = irq; /* Acknowledge the IRQs */
	46
ecc38a09 HC	47	for (i = 0; i < ARRAY_SIZE(ht_irq); i++) {
	48	if (!(irq & (0x1 << ht_irq[i])))
	49	continue;
e1b88ca8	50
ecc38a09 HC	51	/* handled by local core */
	52	if (local_irq & (0x1 << ht_irq[i])) {
	53	do_IRQ(ht_irq[i]);
	54	continue;
	55	}
e1b88ca8	56
ecc38a09 HC	57	irqd = irq_get_irq_data(ht_irq[i]);
	58	cpumask_and(&affinity, irqd->common->affinity, cpu_active_mask);
	59	if (cpumask_empty(&affinity)) {
	60	do_IRQ(ht_irq[i]);
	61	continue;
	62	}
e1b88ca8	63
ecc38a09 HC	64	irq_cpu[ht_irq[i]] = cpumask_next(irq_cpu[ht_irq[i]], &affinity);
	65	if (irq_cpu[ht_irq[i]] >= nr_cpu_ids)
	66	irq_cpu[ht_irq[i]] = cpumask_first(&affinity);
	67
	68	if (irq_cpu[ht_irq[i]] == 0) {
d788bfa9	69	do_IRQ(ht_irq[i]);
ecc38a09 HC	70	continue;
	71	}
	72
	73	/* balanced by other cores */
	74	loongson3_send_irq_by_ipi(irq_cpu[ht_irq[i]], (0x1 << ht_irq[i]));
d788bfa9 HC	75	}
	76	}
	77
24653515 HC	78	#define UNUSED_IPS (CAUSEF_IP5 \| CAUSEF_IP4 \| CAUSEF_IP1 \| CAUSEF_IP0)
24653515 HC	79
d788bfa9 HC	80	void mach_irq_dispatch(unsigned int pending)
	81	{
	82	if (pending & CAUSEF_IP7)
	83	do_IRQ(LOONGSON_TIMER_IRQ);
300459d5	84	#if defined(CONFIG_SMP)
24653515	85	if (pending & CAUSEF_IP6)
300459d5 HC	86	loongson3_ipi_interrupt(NULL);
300459d5 HC	87	#endif
24653515	88	if (pending & CAUSEF_IP3)
d788bfa9	89	ht_irqdispatch();
24653515	90	if (pending & CAUSEF_IP2)
d788bfa9	91	do_IRQ(LOONGSON_UART_IRQ);
24653515	92	if (pending & UNUSED_IPS) {
d788bfa9 HC	93	pr_err("%s : spurious interrupt\n", __func__);
	94	spurious_interrupt();
	95	}
	96	}
	97
	98	static struct irqaction cascade_irqaction = {
	99	.handler = no_action,
0add9c2f	100	.flags = IRQF_NO_SUSPEND,
d788bfa9 HC	101	.name = "cascade",
	102	};
	103
	104	static inline void mask_loongson_irq(struct irq_data *d)
	105	{
	106	clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
	107	irq_disable_hazard();
300459d5 HC	108
	109	/* Workaround: UART IRQ may deliver to any core */
	110	if (d->irq == LOONGSON_UART_IRQ) {
	111	int cpu = smp_processor_id();
ec0f8d3f HC	112	int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
ec0f8d3f HC	113	int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
e7841be5 HC	114	u64 intenclr_addr = smp_group[node_id] \|
	115	(u64)(&LOONGSON_INT_ROUTER_INTENCLR);
	116	u64 introuter_lpc_addr = smp_group[node_id] \|
	117	(u64)(&LOONGSON_INT_ROUTER_LPC);
300459d5	118
e7841be5 HC	119	(volatile u32 )intenclr_addr = 1 << 10;
e7841be5 HC	120	(volatile u8 )introuter_lpc_addr = 0x10 + (1<<core_id);
300459d5	121	}
d788bfa9 HC	122	}
	123
	124	static inline void unmask_loongson_irq(struct irq_data *d)
	125	{
300459d5 HC	126	/* Workaround: UART IRQ may deliver to any core */
	127	if (d->irq == LOONGSON_UART_IRQ) {
	128	int cpu = smp_processor_id();
ec0f8d3f HC	129	int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
ec0f8d3f HC	130	int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
e7841be5 HC	131	u64 intenset_addr = smp_group[node_id] \|
	132	(u64)(&LOONGSON_INT_ROUTER_INTENSET);
	133	u64 introuter_lpc_addr = smp_group[node_id] \|
	134	(u64)(&LOONGSON_INT_ROUTER_LPC);
300459d5	135
e7841be5 HC	136	(volatile u32 )intenset_addr = 1 << 10;
e7841be5 HC	137	(volatile u8 )introuter_lpc_addr = 0x10 + (1<<core_id);
300459d5 HC	138	}
300459d5 HC	139
d788bfa9 HC	140	set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
	141	irq_enable_hazard();
	142	}
	143
	144	/* For MIPS IRQs which shared by all cores */
	145	static struct irq_chip loongson_irq_chip = {
	146	.name = "Loongson",
	147	.irq_ack = mask_loongson_irq,
	148	.irq_mask = mask_loongson_irq,
	149	.irq_mask_ack = mask_loongson_irq,
	150	.irq_unmask = unmask_loongson_irq,
	151	.irq_eoi = unmask_loongson_irq,
	152	};
	153
	154	void irq_router_init(void)
	155	{
	156	int i;
	157
	158	/* route LPC int to cpu core0 int 0 */
ec0f8d3f HC	159	LOONGSON_INT_ROUTER_LPC =
ec0f8d3f HC	160	LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 0);
d788bfa9 HC	161	/* route HT1 int0 ~ int7 to cpu core0 INT1*/
d788bfa9 HC	162	for (i = 0; i < 8; i++)
ec0f8d3f HC	163	LOONGSON_INT_ROUTER_HT1(i) =
ec0f8d3f HC	164	LOONGSON_INT_COREx_INTy(loongson_sysconf.boot_cpu_id, 1);
d788bfa9 HC	165	/* enable HT1 interrupt */
	166	LOONGSON_HT1_INTN_EN(0) = 0xffffffff;
	167	/* enable router interrupt intenset */
	168	LOONGSON_INT_ROUTER_INTENSET =
	169	LOONGSON_INT_ROUTER_INTEN \| (0xffff << 16) \| 0x1 << 10;
	170	}
	171
	172	void __init mach_init_irq(void)
	173	{
ecc38a09 HC	174	struct irq_chip *chip;
ecc38a09 HC	175
d788bfa9 HC	176	clear_c0_status(ST0_IM \| ST0_BEV);
	177
	178	irq_router_init();
	179	mips_cpu_irq_init();
	180	init_i8259_irqs();
ecc38a09 HC	181	chip = irq_get_chip(I8259A_IRQ_BASE);
	182	chip->irq_set_affinity = plat_set_irq_affinity;
	183
d788bfa9 HC	184	irq_set_chip_and_handler(LOONGSON_UART_IRQ,
	185	&loongson_irq_chip, handle_level_irq);
	186
	187	/* setup HT1 irq */
	188	setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
	189
	190	set_c0_status(STATUSF_IP2 \| STATUSF_IP6);
	191	}
c4a987db HC	192
	193	#ifdef CONFIG_HOTPLUG_CPU
	194
	195	void fixup_irqs(void)
	196	{
	197	irq_cpu_offline();
	198	clear_c0_status(ST0_IM);
	199	}
	200
	201	#endif