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Merge branches 'for-4.11/upstream-fixes', 'for-4.12/accutouch', 'for-4.12/cp2112...
[mirror_ubuntu-artful-kernel.git] / arch / mips / loongson64 / loongson-3 / smp.c
CommitLineData
300459d5
HC		 1/*
2 * Copyright (C) 2010, 2011, 2012, Lemote, Inc.
3 * Author: Chen Huacai, chenhc@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/init.h>
18#include <linux/cpu.h>
19#include <linux/sched.h>
20#include <linux/smp.h>
21#include <linux/cpufreq.h>
22#include <asm/processor.h>
23#include <asm/time.h>
24#include <asm/clock.h>
25#include <asm/tlbflush.h>
c4a987db 26#include <asm/cacheflush.h>
300459d5 27#include <loongson.h>
3adeb256 28#include <workarounds.h>
300459d5
HC		 29
30#include "smp.h"
31
c4a987db 32DEFINE_PER_CPU(int, cpu_state);
c4a987db 33
e7841be5
HC		 34static void *ipi_set0_regs[16];
35static void *ipi_clear0_regs[16];
36static void *ipi_status0_regs[16];
37static void *ipi_en0_regs[16];
38static void *ipi_mailbox_buf[16];
57548432 39static uint32_t core0_c0count[NR_CPUS];
e7841be5 40
300459d5
HC		 41/* read a 32bit value from ipi register */
42#define loongson3_ipi_read32(addr) readl(addr)
43/* read a 64bit value from ipi register */
44#define loongson3_ipi_read64(addr) readq(addr)
45/* write a 32bit value to ipi register */
46#define loongson3_ipi_write32(action, addr) \
47 do { \
48 writel(action, addr); \
49 __wbflush(); \
50 } while (0)
51/* write a 64bit value to ipi register */
52#define loongson3_ipi_write64(action, addr) \
53 do { \
54 writeq(action, addr); \
55 __wbflush(); \
56 } while (0)
57
e7841be5
HC		 58static void ipi_set0_regs_init(void)
59{
60 ipi_set0_regs[0] = (void *)
61 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0);
62 ipi_set0_regs[1] = (void *)
63 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0);
64 ipi_set0_regs[2] = (void *)
65 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0);
66 ipi_set0_regs[3] = (void *)
67 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0);
68 ipi_set0_regs[4] = (void *)
69 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0);
70 ipi_set0_regs[5] = (void *)
71 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0);
72 ipi_set0_regs[6] = (void *)
73 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0);
74 ipi_set0_regs[7] = (void *)
75 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0);
76 ipi_set0_regs[8] = (void *)
77 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0);
78 ipi_set0_regs[9] = (void *)
79 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0);
80 ipi_set0_regs[10] = (void *)
81 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0);
82 ipi_set0_regs[11] = (void *)
83 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0);
84 ipi_set0_regs[12] = (void *)
85 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0);
86 ipi_set0_regs[13] = (void *)
87 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0);
88 ipi_set0_regs[14] = (void *)
89 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0);
90 ipi_set0_regs[15] = (void *)
91 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0);
92}
300459d5 93
e7841be5
HC		 94static void ipi_clear0_regs_init(void)
95{
96 ipi_clear0_regs[0] = (void *)
97 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0);
98 ipi_clear0_regs[1] = (void *)
99 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0);
100 ipi_clear0_regs[2] = (void *)
101 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0);
102 ipi_clear0_regs[3] = (void *)
103 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0);
104 ipi_clear0_regs[4] = (void *)
105 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0);
106 ipi_clear0_regs[5] = (void *)
107 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0);
108 ipi_clear0_regs[6] = (void *)
109 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0);
110 ipi_clear0_regs[7] = (void *)
111 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0);
112 ipi_clear0_regs[8] = (void *)
113 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0);
114 ipi_clear0_regs[9] = (void *)
115 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0);
116 ipi_clear0_regs[10] = (void *)
117 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0);
118 ipi_clear0_regs[11] = (void *)
119 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0);
120 ipi_clear0_regs[12] = (void *)
121 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0);
122 ipi_clear0_regs[13] = (void *)
123 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0);
124 ipi_clear0_regs[14] = (void *)
125 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0);
126 ipi_clear0_regs[15] = (void *)
127 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0);
128}
300459d5 129
e7841be5
HC		 130static void ipi_status0_regs_init(void)
131{
132 ipi_status0_regs[0] = (void *)
133 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0);
134 ipi_status0_regs[1] = (void *)
135 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0);
136 ipi_status0_regs[2] = (void *)
137 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0);
138 ipi_status0_regs[3] = (void *)
139 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0);
140 ipi_status0_regs[4] = (void *)
141 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0);
142 ipi_status0_regs[5] = (void *)
143 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0);
144 ipi_status0_regs[6] = (void *)
145 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0);
146 ipi_status0_regs[7] = (void *)
147 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0);
148 ipi_status0_regs[8] = (void *)
149 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0);
150 ipi_status0_regs[9] = (void *)
151 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0);
152 ipi_status0_regs[10] = (void *)
153 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0);
154 ipi_status0_regs[11] = (void *)
155 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0);
156 ipi_status0_regs[12] = (void *)
157 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0);
158 ipi_status0_regs[13] = (void *)
159 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0);
160 ipi_status0_regs[14] = (void *)
161 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0);
162 ipi_status0_regs[15] = (void *)
163 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0);
164}
300459d5 165
e7841be5
HC		 166static void ipi_en0_regs_init(void)
167{
168 ipi_en0_regs[0] = (void *)
169 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0);
170 ipi_en0_regs[1] = (void *)
171 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0);
172 ipi_en0_regs[2] = (void *)
173 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0);
174 ipi_en0_regs[3] = (void *)
175 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0);
176 ipi_en0_regs[4] = (void *)
177 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0);
178 ipi_en0_regs[5] = (void *)
179 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0);
180 ipi_en0_regs[6] = (void *)
181 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0);
182 ipi_en0_regs[7] = (void *)
183 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0);
184 ipi_en0_regs[8] = (void *)
185 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0);
186 ipi_en0_regs[9] = (void *)
187 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0);
188 ipi_en0_regs[10] = (void *)
189 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0);
190 ipi_en0_regs[11] = (void *)
191 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0);
192 ipi_en0_regs[12] = (void *)
193 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0);
194 ipi_en0_regs[13] = (void *)
195 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0);
196 ipi_en0_regs[14] = (void *)
197 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0);
198 ipi_en0_regs[15] = (void *)
199 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0);
200}
300459d5 201
e7841be5
HC		 202static void ipi_mailbox_buf_init(void)
203{
204 ipi_mailbox_buf[0] = (void *)
205 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF);
206 ipi_mailbox_buf[1] = (void *)
207 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF);
208 ipi_mailbox_buf[2] = (void *)
209 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF);
210 ipi_mailbox_buf[3] = (void *)
211 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF);
212 ipi_mailbox_buf[4] = (void *)
213 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF);
214 ipi_mailbox_buf[5] = (void *)
215 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF);
216 ipi_mailbox_buf[6] = (void *)
217 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF);
218 ipi_mailbox_buf[7] = (void *)
219 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF);
220 ipi_mailbox_buf[8] = (void *)
221 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF);
222 ipi_mailbox_buf[9] = (void *)
223 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF);
224 ipi_mailbox_buf[10] = (void *)
225 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF);
226 ipi_mailbox_buf[11] = (void *)
227 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF);
228 ipi_mailbox_buf[12] = (void *)
229 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF);
230 ipi_mailbox_buf[13] = (void *)
231 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF);
232 ipi_mailbox_buf[14] = (void *)
233 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF);
234 ipi_mailbox_buf[15] = (void *)
235 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF);
236}
300459d5
HC		 237
238/*
239 * Simple enough, just poke the appropriate ipi register
240 */
241static void loongson3_send_ipi_single(int cpu, unsigned int action)
242{
ec0f8d3f 243 loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu_logical_map(cpu)]);
300459d5
HC		 244}
245
246static void
247loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action)
248{
249 unsigned int i;
250
251 for_each_cpu(i, mask)
ec0f8d3f 252 loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu_logical_map(i)]);
300459d5
HC		 253}
254
255void loongson3_ipi_interrupt(struct pt_regs *regs)
256{
c4a987db
HC		 257 int i, cpu = smp_processor_id();
258 unsigned int action, c0count;
300459d5
HC		 259
260 /* Load the ipi register to figure out what we're supposed to do */
ec0f8d3f 261 action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]);
300459d5
HC		 262
263 /* Clear the ipi register to clear the interrupt */
ec0f8d3f 264 loongson3_ipi_write32((u32)action, ipi_clear0_regs[cpu_logical_map(cpu)]);
300459d5
HC		 265
266 if (action & SMP_RESCHEDULE_YOURSELF)
267 scheduler_ipi();
268
4ace6139
AS		 269 if (action & SMP_CALL_FUNCTION) {
270 irq_enter();
271 generic_smp_call_function_interrupt();
272 irq_exit();
273 }
c4a987db
HC		 274
275 if (action & SMP_ASK_C0COUNT) {
276 BUG_ON(cpu != 0);
277 c0count = read_c0_count();
57548432
HC		 278 c0count = c0count ? c0count : 1;
279 for (i = 1; i < nr_cpu_ids; i++)
280 core0_c0count[i] = c0count;
281 __wbflush(); /* Let others see the result ASAP */
c4a987db 282 }
300459d5
HC		 283}
284
57548432 285#define MAX_LOOPS 800
300459d5
HC		 286/*
287 * SMP init and finish on secondary CPUs
288 */
289static void loongson3_init_secondary(void)
290{
291 int i;
c4a987db
HC		 292 uint32_t initcount;
293 unsigned int cpu = smp_processor_id();
300459d5
HC		 294 unsigned int imask = STATUSF_IP7 | STATUSF_IP6 |
295 STATUSF_IP3 | STATUSF_IP2;
296
297 /* Set interrupt mask, but don't enable */
298 change_c0_status(ST0_IM, imask);
299
ec0f8d3f
HC		 300 for (i = 0; i < num_possible_cpus(); i++)
301 loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(i)]);
c4a987db
HC		 302
303 per_cpu(cpu_state, cpu) = CPU_ONLINE;
ec0f8d3f
HC		 304 cpu_data[cpu].core =
305 cpu_logical_map(cpu) % loongson_sysconf.cores_per_package;
306 cpu_data[cpu].package =
307 cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;
c4a987db
HC		 308
309 i = 0;
57548432 310 core0_c0count[cpu] = 0;
c4a987db 311 loongson3_send_ipi_single(0, SMP_ASK_C0COUNT);
57548432 312 while (!core0_c0count[cpu]) {
c4a987db
HC		 313 i++;
314 cpu_relax();
315 }
316
317 if (i > MAX_LOOPS)
318 i = MAX_LOOPS;
57548432
HC		 319 if (cpu_data[cpu].package)
320 initcount = core0_c0count[cpu] + i;
321 else /* Local access is faster for loops */
322 initcount = core0_c0count[cpu] + i/2;
323
c4a987db 324 write_c0_count(initcount);
300459d5
HC		 325}
326
327static void loongson3_smp_finish(void)
328{
ec0f8d3f
HC		 329 int cpu = smp_processor_id();
330
300459d5
HC		 331 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
332 local_irq_enable();
333 loongson3_ipi_write64(0,
ec0f8d3f 334 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x0));
300459d5
HC		 335 pr_info("CPU#%d finished, CP0_ST=%x\n",
336 smp_processor_id(), read_c0_status());
337}
338
339static void __init loongson3_smp_setup(void)
340{
ec0f8d3f 341 int i = 0, num = 0; /* i: physical id, num: logical id */
300459d5
HC		 342
343 init_cpu_possible(cpu_none_mask);
300459d5
HC		 344
345 /* For unified kernel, NR_CPUS is the maximum possible value,
346 * loongson_sysconf.nr_cpus is the really present value */
ec0f8d3f
HC		 347 while (i < loongson_sysconf.nr_cpus) {
348 if (loongson_sysconf.reserved_cpus_mask & (1<<i)) {
349 /* Reserved physical CPU cores */
350 __cpu_number_map[i] = -1;
351 } else {
352 __cpu_number_map[i] = num;
353 __cpu_logical_map[num] = i;
354 set_cpu_possible(num, true);
355 num++;
356 }
357 i++;
300459d5 358 }
ec0f8d3f
HC		 359 pr_info("Detected %i available CPU(s)\n", num);
360
361 while (num < loongson_sysconf.nr_cpus) {
362 __cpu_logical_map[num] = -1;
363 num++;
364 }
365
e7841be5
HC		 366 ipi_set0_regs_init();
367 ipi_clear0_regs_init();
368 ipi_status0_regs_init();
369 ipi_en0_regs_init();
370 ipi_mailbox_buf_init();
ec0f8d3f
HC		 371 cpu_data[0].core = cpu_logical_map(0) % loongson_sysconf.cores_per_package;
372 cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
300459d5
HC		 373}
374
375static void __init loongson3_prepare_cpus(unsigned int max_cpus)
376{
c4a987db
HC		 377 init_cpu_present(cpu_possible_mask);
378 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
300459d5
HC		 379}
380
381/*
382 * Setup the PC, SP, and GP of a secondary processor and start it runing!
383 */
384static void loongson3_boot_secondary(int cpu, struct task_struct *idle)
385{
386 unsigned long startargs[4];
387
388 pr_info("Booting CPU#%d...\n", cpu);
389
390 /* startargs[] are initial PC, SP and GP for secondary CPU */
391 startargs[0] = (unsigned long)&smp_bootstrap;
392 startargs[1] = (unsigned long)__KSTK_TOS(idle);
393 startargs[2] = (unsigned long)task_thread_info(idle);
394 startargs[3] = 0;
395
396 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
397 cpu, startargs[0], startargs[1], startargs[2]);
398
ec0f8d3f
HC		 399 loongson3_ipi_write64(startargs[3],
400 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x18));
401 loongson3_ipi_write64(startargs[2],
402 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x10));
403 loongson3_ipi_write64(startargs[1],
404 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x8));
405 loongson3_ipi_write64(startargs[0],
406 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x0));
300459d5
HC		 407}
408
c4a987db
HC		 409#ifdef CONFIG_HOTPLUG_CPU
410
411static int loongson3_cpu_disable(void)
412{
413 unsigned long flags;
414 unsigned int cpu = smp_processor_id();
415
416 if (cpu == 0)
417 return -EBUSY;
418
419 set_cpu_online(cpu, false);
826e99be 420 calculate_cpu_foreign_map();
c4a987db
HC		 421 local_irq_save(flags);
422 fixup_irqs();
423 local_irq_restore(flags);
c4a987db
HC		 424 local_flush_tlb_all();
425
426 return 0;
427}
428
429
430static void loongson3_cpu_die(unsigned int cpu)
431{
432 while (per_cpu(cpu_state, cpu) != CPU_DEAD)
433 cpu_relax();
434
435 mb();
436}
437
438/* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and
439 * flush all L1 entries at first. Then, another core (usually Core 0) can
440 * safely disable the clock of the target core. loongson3_play_dead() is
441 * called via CKSEG1 (uncached and unmmaped) */
b2edcfc8 442static void loongson3a_r1_play_dead(int *state_addr)
c4a987db
HC		 443{
444 register int val;
445 register long cpuid, core, node, count;
446 register void *addr, *base, *initfunc;
447
448 __asm__ __volatile__(
449 " .set push \n"
450 " .set noreorder \n"
451 " li %[addr], 0x80000000 \n" /* KSEG0 */
452 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
453 " cache 0, 1(%[addr]) \n"
454 " cache 0, 2(%[addr]) \n"
455 " cache 0, 3(%[addr]) \n"
456 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
457 " cache 1, 1(%[addr]) \n"
458 " cache 1, 2(%[addr]) \n"
459 " cache 1, 3(%[addr]) \n"
460 " addiu %[sets], %[sets], -1 \n"
461 " bnez %[sets], 1b \n"
462 " addiu %[addr], %[addr], 0x20 \n"
463 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
464 " sw %[val], (%[state_addr]) \n"
465 " sync \n"
466 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
467 " .set pop \n"
468 : [addr] "=&r" (addr), [val] "=&r" (val)
469 : [state_addr] "r" (state_addr),
470 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
471
472 __asm__ __volatile__(
473 " .set push \n"
474 " .set noreorder \n"
475 " .set mips64 \n"
476 " mfc0 %[cpuid], $15, 1 \n"
477 " andi %[cpuid], 0x3ff \n"
478 " dli %[base], 0x900000003ff01000 \n"
479 " andi %[core], %[cpuid], 0x3 \n"
480 " sll %[core], 8 \n" /* get core id */
481 " or %[base], %[base], %[core] \n"
482 " andi %[node], %[cpuid], 0xc \n"
483 " dsll %[node], 42 \n" /* get node id */
484 " or %[base], %[base], %[node] \n"
485 "1: li %[count], 0x100 \n" /* wait for init loop */
486 "2: bnez %[count], 2b \n" /* limit mailbox access */
487 " addiu %[count], -1 \n"
488 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
489 " beqz %[initfunc], 1b \n"
490 " nop \n"
491 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
492 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
493 " ld $a1, 0x38(%[base]) \n"
494 " jr %[initfunc] \n" /* jump to initial PC */
495 " nop \n"
496 " .set pop \n"
497 : [core] "=&r" (core), [node] "=&r" (node),
498 [base] "=&r" (base), [cpuid] "=&r" (cpuid),
499 [count] "=&r" (count), [initfunc] "=&r" (initfunc)
500 : /* No Input */
501 : "a1");
502}
503
b2edcfc8
HC		 504static void loongson3a_r2_play_dead(int *state_addr)
505{
506 register int val;
507 register long cpuid, core, node, count;
508 register void *addr, *base, *initfunc;
509
510 __asm__ __volatile__(
511 " .set push \n"
512 " .set noreorder \n"
513 " li %[addr], 0x80000000 \n" /* KSEG0 */
514 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
515 " cache 0, 1(%[addr]) \n"
516 " cache 0, 2(%[addr]) \n"
517 " cache 0, 3(%[addr]) \n"
518 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
519 " cache 1, 1(%[addr]) \n"
520 " cache 1, 2(%[addr]) \n"
521 " cache 1, 3(%[addr]) \n"
522 " addiu %[sets], %[sets], -1 \n"
523 " bnez %[sets], 1b \n"
524 " addiu %[addr], %[addr], 0x40 \n"
525 " li %[addr], 0x80000000 \n" /* KSEG0 */
526 "2: cache 2, 0(%[addr]) \n" /* flush L1 VCache */
527 " cache 2, 1(%[addr]) \n"
528 " cache 2, 2(%[addr]) \n"
529 " cache 2, 3(%[addr]) \n"
530 " cache 2, 4(%[addr]) \n"
531 " cache 2, 5(%[addr]) \n"
532 " cache 2, 6(%[addr]) \n"
533 " cache 2, 7(%[addr]) \n"
534 " cache 2, 8(%[addr]) \n"
535 " cache 2, 9(%[addr]) \n"
536 " cache 2, 10(%[addr]) \n"
537 " cache 2, 11(%[addr]) \n"
538 " cache 2, 12(%[addr]) \n"
539 " cache 2, 13(%[addr]) \n"
540 " cache 2, 14(%[addr]) \n"
541 " cache 2, 15(%[addr]) \n"
542 " addiu %[vsets], %[vsets], -1 \n"
543 " bnez %[vsets], 2b \n"
544 " addiu %[addr], %[addr], 0x40 \n"
545 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
546 " sw %[val], (%[state_addr]) \n"
547 " sync \n"
548 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
549 " .set pop \n"
550 : [addr] "=&r" (addr), [val] "=&r" (val)
551 : [state_addr] "r" (state_addr),
552 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets),
553 [vsets] "r" (cpu_data[smp_processor_id()].vcache.sets));
554
555 __asm__ __volatile__(
556 " .set push \n"
557 " .set noreorder \n"
558 " .set mips64 \n"
559 " mfc0 %[cpuid], $15, 1 \n"
560 " andi %[cpuid], 0x3ff \n"
561 " dli %[base], 0x900000003ff01000 \n"
562 " andi %[core], %[cpuid], 0x3 \n"
563 " sll %[core], 8 \n" /* get core id */
564 " or %[base], %[base], %[core] \n"
565 " andi %[node], %[cpuid], 0xc \n"
566 " dsll %[node], 42 \n" /* get node id */
567 " or %[base], %[base], %[node] \n"
568 "1: li %[count], 0x100 \n" /* wait for init loop */
569 "2: bnez %[count], 2b \n" /* limit mailbox access */
570 " addiu %[count], -1 \n"
571 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
572 " beqz %[initfunc], 1b \n"
573 " nop \n"
574 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
575 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
576 " ld $a1, 0x38(%[base]) \n"
577 " jr %[initfunc] \n" /* jump to initial PC */
578 " nop \n"
579 " .set pop \n"
580 : [core] "=&r" (core), [node] "=&r" (node),
581 [base] "=&r" (base), [cpuid] "=&r" (cpuid),
582 [count] "=&r" (count), [initfunc] "=&r" (initfunc)
583 : /* No Input */
584 : "a1");
585}
586
e7841be5
HC		 587static void loongson3b_play_dead(int *state_addr)
588{
589 register int val;
590 register long cpuid, core, node, count;
591 register void *addr, *base, *initfunc;
592
593 __asm__ __volatile__(
594 " .set push \n"
595 " .set noreorder \n"
596 " li %[addr], 0x80000000 \n" /* KSEG0 */
597 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
598 " cache 0, 1(%[addr]) \n"
599 " cache 0, 2(%[addr]) \n"
600 " cache 0, 3(%[addr]) \n"
601 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
602 " cache 1, 1(%[addr]) \n"
603 " cache 1, 2(%[addr]) \n"
604 " cache 1, 3(%[addr]) \n"
605 " addiu %[sets], %[sets], -1 \n"
606 " bnez %[sets], 1b \n"
607 " addiu %[addr], %[addr], 0x20 \n"
608 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
609 " sw %[val], (%[state_addr]) \n"
610 " sync \n"
611 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
612 " .set pop \n"
613 : [addr] "=&r" (addr), [val] "=&r" (val)
614 : [state_addr] "r" (state_addr),
615 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
616
617 __asm__ __volatile__(
618 " .set push \n"
619 " .set noreorder \n"
620 " .set mips64 \n"
621 " mfc0 %[cpuid], $15, 1 \n"
622 " andi %[cpuid], 0x3ff \n"
623 " dli %[base], 0x900000003ff01000 \n"
624 " andi %[core], %[cpuid], 0x3 \n"
625 " sll %[core], 8 \n" /* get core id */
626 " or %[base], %[base], %[core] \n"
627 " andi %[node], %[cpuid], 0xc \n"
628 " dsll %[node], 42 \n" /* get node id */
629 " or %[base], %[base], %[node] \n"
630 " dsrl %[node], 30 \n" /* 15:14 */
631 " or %[base], %[base], %[node] \n"
632 "1: li %[count], 0x100 \n" /* wait for init loop */
633 "2: bnez %[count], 2b \n" /* limit mailbox access */
634 " addiu %[count], -1 \n"
635 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
636 " beqz %[initfunc], 1b \n"
637 " nop \n"
638 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
639 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
640 " ld $a1, 0x38(%[base]) \n"
641 " jr %[initfunc] \n" /* jump to initial PC */
642 " nop \n"
643 " .set pop \n"
644 : [core] "=&r" (core), [node] "=&r" (node),
645 [base] "=&r" (base), [cpuid] "=&r" (cpuid),
646 [count] "=&r" (count), [initfunc] "=&r" (initfunc)
647 : /* No Input */
648 : "a1");
649}
650
c4a987db
HC		 651void play_dead(void)
652{
653 int *state_addr;
654 unsigned int cpu = smp_processor_id();
655 void (*play_dead_at_ckseg1)(int *);
656
657 idle_task_exit();
b2edcfc8
HC		 658 switch (read_c0_prid() & PRID_REV_MASK) {
659 case PRID_REV_LOONGSON3A_R1:
e7841be5
HC		 660 default:
661 play_dead_at_ckseg1 =
b2edcfc8
HC		 662 (void *)CKSEG1ADDR((unsigned long)loongson3a_r1_play_dead);
663 break;
664 case PRID_REV_LOONGSON3A_R2:
665 play_dead_at_ckseg1 =
666 (void *)CKSEG1ADDR((unsigned long)loongson3a_r2_play_dead);
e7841be5 667 break;
b2edcfc8
HC		 668 case PRID_REV_LOONGSON3B_R1:
669 case PRID_REV_LOONGSON3B_R2:
e7841be5
HC		 670 play_dead_at_ckseg1 =
671 (void *)CKSEG1ADDR((unsigned long)loongson3b_play_dead);
672 break;
673 }
c4a987db
HC		 674 state_addr = &per_cpu(cpu_state, cpu);
675 mb();
676 play_dead_at_ckseg1(state_addr);
677}
678
e476d312 679static int loongson3_disable_clock(unsigned int cpu)
e7841be5
HC		 680{
681 uint64_t core_id = cpu_data[cpu].core;
682 uint64_t package_id = cpu_data[cpu].package;
683
b2edcfc8 684 if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
e7841be5 685 LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id));
b2edcfc8 686 } else {
3adeb256 687 if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG))
e7841be5
HC		 688 LOONGSON_FREQCTRL(package_id) &= ~(1 << (core_id * 4 + 3));
689 }
e476d312 690 return 0;
e7841be5
HC		 691}
692
e476d312 693static int loongson3_enable_clock(unsigned int cpu)
e7841be5
HC		 694{
695 uint64_t core_id = cpu_data[cpu].core;
696 uint64_t package_id = cpu_data[cpu].package;
697
b2edcfc8 698 if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
e7841be5 699 LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id);
b2edcfc8 700 } else {
3adeb256 701 if (!(loongson_sysconf.workarounds & WORKAROUND_CPUHOTPLUG))
e7841be5
HC		 702 LOONGSON_FREQCTRL(package_id) |= 1 << (core_id * 4 + 3);
703 }
e476d312 704 return 0;
c4a987db
HC		 705}
706
707static int register_loongson3_notifier(void)
708{
e476d312
SAS		 709 return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE,
710 "mips/loongson:prepare",
711 loongson3_enable_clock,
712 loongson3_disable_clock);
c4a987db
HC		 713}
714early_initcall(register_loongson3_notifier);
715
716#endif
717
300459d5
HC		 718struct plat_smp_ops loongson3_smp_ops = {
719 .send_ipi_single = loongson3_send_ipi_single,
720 .send_ipi_mask = loongson3_send_ipi_mask,
721 .init_secondary = loongson3_init_secondary,
722 .smp_finish = loongson3_smp_finish,
300459d5
HC		 723 .boot_secondary = loongson3_boot_secondary,
724 .smp_setup = loongson3_smp_setup,
725 .prepare_cpus = loongson3_prepare_cpus,
c4a987db
HC		 726#ifdef CONFIG_HOTPLUG_CPU
727 .cpu_disable = loongson3_cpu_disable,
728 .cpu_die = loongson3_cpu_die,
729#endif
300459d5 730};
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