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Commit | Line | Data |
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1da177e4 | 1 | /* |
3f7cac41 | 2 | * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator |
1da177e4 LT |
3 | * |
4 | * MIPS floating point support | |
5 | * Copyright (C) 1994-2000 Algorithmics Ltd. | |
1da177e4 LT |
6 | * |
7 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
8 | * Copyright (C) 2000 MIPS Technologies, Inc. | |
9 | * | |
10 | * This program is free software; you can distribute it and/or modify it | |
11 | * under the terms of the GNU General Public License (Version 2) as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | * for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, write to the Free Software Foundation, Inc., | |
3f7cac41 | 21 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
1da177e4 LT |
22 | * |
23 | * A complete emulator for MIPS coprocessor 1 instructions. This is | |
24 | * required for #float(switch) or #float(trap), where it catches all | |
25 | * COP1 instructions via the "CoProcessor Unusable" exception. | |
26 | * | |
27 | * More surprisingly it is also required for #float(ieee), to help out | |
3f7cac41 | 28 | * the hardware FPU at the boundaries of the IEEE-754 representation |
1da177e4 LT |
29 | * (denormalised values, infinities, underflow, etc). It is made |
30 | * quite nasty because emulation of some non-COP1 instructions is | |
31 | * required, e.g. in branch delay slots. | |
32 | * | |
3f7cac41 | 33 | * Note if you know that you won't have an FPU, then you'll get much |
1da177e4 LT |
34 | * better performance by compiling with -msoft-float! |
35 | */ | |
36 | #include <linux/sched.h> | |
83fd38ca | 37 | #include <linux/debugfs.h> |
08a07904 | 38 | #include <linux/kconfig.h> |
85c51c51 | 39 | #include <linux/percpu-defs.h> |
7f788d2d | 40 | #include <linux/perf_event.h> |
1da177e4 | 41 | |
cd8ee345 | 42 | #include <asm/branch.h> |
1da177e4 | 43 | #include <asm/inst.h> |
1da177e4 LT |
44 | #include <asm/ptrace.h> |
45 | #include <asm/signal.h> | |
cd8ee345 RB |
46 | #include <asm/uaccess.h> |
47 | ||
48 | #include <asm/processor.h> | |
1da177e4 | 49 | #include <asm/fpu_emulator.h> |
102cedc3 | 50 | #include <asm/fpu.h> |
1da177e4 LT |
51 | |
52 | #include "ieee754.h" | |
1da177e4 | 53 | |
1da177e4 LT |
54 | /* Function which emulates a floating point instruction. */ |
55 | ||
eae89076 | 56 | static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, |
1da177e4 LT |
57 | mips_instruction); |
58 | ||
1da177e4 | 59 | static int fpux_emu(struct pt_regs *, |
515b029d | 60 | struct mips_fpu_struct *, mips_instruction, void *__user *); |
1da177e4 | 61 | |
1da177e4 LT |
62 | /* Control registers */ |
63 | ||
64 | #define FPCREG_RID 0 /* $0 = revision id */ | |
65 | #define FPCREG_CSR 31 /* $31 = csr */ | |
66 | ||
95e8f634 SM |
67 | /* Determine rounding mode from the RM bits of the FCSR */ |
68 | #define modeindex(v) ((v) & FPU_CSR_RM) | |
69 | ||
1da177e4 LT |
70 | /* convert condition code register number to csr bit */ |
71 | static const unsigned int fpucondbit[8] = { | |
72 | FPU_CSR_COND0, | |
73 | FPU_CSR_COND1, | |
74 | FPU_CSR_COND2, | |
75 | FPU_CSR_COND3, | |
76 | FPU_CSR_COND4, | |
77 | FPU_CSR_COND5, | |
78 | FPU_CSR_COND6, | |
79 | FPU_CSR_COND7 | |
80 | }; | |
1da177e4 | 81 | |
102cedc3 LY |
82 | /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ |
83 | static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; | |
84 | static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; | |
85 | static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; | |
86 | static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; | |
87 | ||
88 | /* | |
89 | * This functions translates a 32-bit microMIPS instruction | |
90 | * into a 32-bit MIPS32 instruction. Returns 0 on success | |
91 | * and SIGILL otherwise. | |
92 | */ | |
93 | static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) | |
94 | { | |
95 | union mips_instruction insn = *insn_ptr; | |
96 | union mips_instruction mips32_insn = insn; | |
97 | int func, fmt, op; | |
98 | ||
99 | switch (insn.mm_i_format.opcode) { | |
100 | case mm_ldc132_op: | |
101 | mips32_insn.mm_i_format.opcode = ldc1_op; | |
102 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
103 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
104 | break; | |
105 | case mm_lwc132_op: | |
106 | mips32_insn.mm_i_format.opcode = lwc1_op; | |
107 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
108 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
109 | break; | |
110 | case mm_sdc132_op: | |
111 | mips32_insn.mm_i_format.opcode = sdc1_op; | |
112 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
113 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
114 | break; | |
115 | case mm_swc132_op: | |
116 | mips32_insn.mm_i_format.opcode = swc1_op; | |
117 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
118 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
119 | break; | |
120 | case mm_pool32i_op: | |
121 | /* NOTE: offset is << by 1 if in microMIPS mode. */ | |
122 | if ((insn.mm_i_format.rt == mm_bc1f_op) || | |
123 | (insn.mm_i_format.rt == mm_bc1t_op)) { | |
124 | mips32_insn.fb_format.opcode = cop1_op; | |
125 | mips32_insn.fb_format.bc = bc_op; | |
126 | mips32_insn.fb_format.flag = | |
127 | (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; | |
128 | } else | |
129 | return SIGILL; | |
130 | break; | |
131 | case mm_pool32f_op: | |
132 | switch (insn.mm_fp0_format.func) { | |
133 | case mm_32f_01_op: | |
134 | case mm_32f_11_op: | |
135 | case mm_32f_02_op: | |
136 | case mm_32f_12_op: | |
137 | case mm_32f_41_op: | |
138 | case mm_32f_51_op: | |
139 | case mm_32f_42_op: | |
140 | case mm_32f_52_op: | |
141 | op = insn.mm_fp0_format.func; | |
142 | if (op == mm_32f_01_op) | |
143 | func = madd_s_op; | |
144 | else if (op == mm_32f_11_op) | |
145 | func = madd_d_op; | |
146 | else if (op == mm_32f_02_op) | |
147 | func = nmadd_s_op; | |
148 | else if (op == mm_32f_12_op) | |
149 | func = nmadd_d_op; | |
150 | else if (op == mm_32f_41_op) | |
151 | func = msub_s_op; | |
152 | else if (op == mm_32f_51_op) | |
153 | func = msub_d_op; | |
154 | else if (op == mm_32f_42_op) | |
155 | func = nmsub_s_op; | |
156 | else | |
157 | func = nmsub_d_op; | |
158 | mips32_insn.fp6_format.opcode = cop1x_op; | |
159 | mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; | |
160 | mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; | |
161 | mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; | |
162 | mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; | |
163 | mips32_insn.fp6_format.func = func; | |
164 | break; | |
165 | case mm_32f_10_op: | |
166 | func = -1; /* Invalid */ | |
167 | op = insn.mm_fp5_format.op & 0x7; | |
168 | if (op == mm_ldxc1_op) | |
169 | func = ldxc1_op; | |
170 | else if (op == mm_sdxc1_op) | |
171 | func = sdxc1_op; | |
172 | else if (op == mm_lwxc1_op) | |
173 | func = lwxc1_op; | |
174 | else if (op == mm_swxc1_op) | |
175 | func = swxc1_op; | |
176 | ||
177 | if (func != -1) { | |
178 | mips32_insn.r_format.opcode = cop1x_op; | |
179 | mips32_insn.r_format.rs = | |
180 | insn.mm_fp5_format.base; | |
181 | mips32_insn.r_format.rt = | |
182 | insn.mm_fp5_format.index; | |
183 | mips32_insn.r_format.rd = 0; | |
184 | mips32_insn.r_format.re = insn.mm_fp5_format.fd; | |
185 | mips32_insn.r_format.func = func; | |
186 | } else | |
187 | return SIGILL; | |
188 | break; | |
189 | case mm_32f_40_op: | |
190 | op = -1; /* Invalid */ | |
191 | if (insn.mm_fp2_format.op == mm_fmovt_op) | |
192 | op = 1; | |
193 | else if (insn.mm_fp2_format.op == mm_fmovf_op) | |
194 | op = 0; | |
195 | if (op != -1) { | |
196 | mips32_insn.fp0_format.opcode = cop1_op; | |
197 | mips32_insn.fp0_format.fmt = | |
198 | sdps_format[insn.mm_fp2_format.fmt]; | |
199 | mips32_insn.fp0_format.ft = | |
200 | (insn.mm_fp2_format.cc<<2) + op; | |
201 | mips32_insn.fp0_format.fs = | |
202 | insn.mm_fp2_format.fs; | |
203 | mips32_insn.fp0_format.fd = | |
204 | insn.mm_fp2_format.fd; | |
205 | mips32_insn.fp0_format.func = fmovc_op; | |
206 | } else | |
207 | return SIGILL; | |
208 | break; | |
209 | case mm_32f_60_op: | |
210 | func = -1; /* Invalid */ | |
211 | if (insn.mm_fp0_format.op == mm_fadd_op) | |
212 | func = fadd_op; | |
213 | else if (insn.mm_fp0_format.op == mm_fsub_op) | |
214 | func = fsub_op; | |
215 | else if (insn.mm_fp0_format.op == mm_fmul_op) | |
216 | func = fmul_op; | |
217 | else if (insn.mm_fp0_format.op == mm_fdiv_op) | |
218 | func = fdiv_op; | |
219 | if (func != -1) { | |
220 | mips32_insn.fp0_format.opcode = cop1_op; | |
221 | mips32_insn.fp0_format.fmt = | |
222 | sdps_format[insn.mm_fp0_format.fmt]; | |
223 | mips32_insn.fp0_format.ft = | |
224 | insn.mm_fp0_format.ft; | |
225 | mips32_insn.fp0_format.fs = | |
226 | insn.mm_fp0_format.fs; | |
227 | mips32_insn.fp0_format.fd = | |
228 | insn.mm_fp0_format.fd; | |
229 | mips32_insn.fp0_format.func = func; | |
230 | } else | |
231 | return SIGILL; | |
232 | break; | |
233 | case mm_32f_70_op: | |
234 | func = -1; /* Invalid */ | |
235 | if (insn.mm_fp0_format.op == mm_fmovn_op) | |
236 | func = fmovn_op; | |
237 | else if (insn.mm_fp0_format.op == mm_fmovz_op) | |
238 | func = fmovz_op; | |
239 | if (func != -1) { | |
240 | mips32_insn.fp0_format.opcode = cop1_op; | |
241 | mips32_insn.fp0_format.fmt = | |
242 | sdps_format[insn.mm_fp0_format.fmt]; | |
243 | mips32_insn.fp0_format.ft = | |
244 | insn.mm_fp0_format.ft; | |
245 | mips32_insn.fp0_format.fs = | |
246 | insn.mm_fp0_format.fs; | |
247 | mips32_insn.fp0_format.fd = | |
248 | insn.mm_fp0_format.fd; | |
249 | mips32_insn.fp0_format.func = func; | |
250 | } else | |
251 | return SIGILL; | |
252 | break; | |
253 | case mm_32f_73_op: /* POOL32FXF */ | |
254 | switch (insn.mm_fp1_format.op) { | |
255 | case mm_movf0_op: | |
256 | case mm_movf1_op: | |
257 | case mm_movt0_op: | |
258 | case mm_movt1_op: | |
259 | if ((insn.mm_fp1_format.op & 0x7f) == | |
260 | mm_movf0_op) | |
261 | op = 0; | |
262 | else | |
263 | op = 1; | |
264 | mips32_insn.r_format.opcode = spec_op; | |
265 | mips32_insn.r_format.rs = insn.mm_fp4_format.fs; | |
266 | mips32_insn.r_format.rt = | |
267 | (insn.mm_fp4_format.cc << 2) + op; | |
268 | mips32_insn.r_format.rd = insn.mm_fp4_format.rt; | |
269 | mips32_insn.r_format.re = 0; | |
270 | mips32_insn.r_format.func = movc_op; | |
271 | break; | |
272 | case mm_fcvtd0_op: | |
273 | case mm_fcvtd1_op: | |
274 | case mm_fcvts0_op: | |
275 | case mm_fcvts1_op: | |
276 | if ((insn.mm_fp1_format.op & 0x7f) == | |
277 | mm_fcvtd0_op) { | |
278 | func = fcvtd_op; | |
279 | fmt = swl_format[insn.mm_fp3_format.fmt]; | |
280 | } else { | |
281 | func = fcvts_op; | |
282 | fmt = dwl_format[insn.mm_fp3_format.fmt]; | |
283 | } | |
284 | mips32_insn.fp0_format.opcode = cop1_op; | |
285 | mips32_insn.fp0_format.fmt = fmt; | |
286 | mips32_insn.fp0_format.ft = 0; | |
287 | mips32_insn.fp0_format.fs = | |
288 | insn.mm_fp3_format.fs; | |
289 | mips32_insn.fp0_format.fd = | |
290 | insn.mm_fp3_format.rt; | |
291 | mips32_insn.fp0_format.func = func; | |
292 | break; | |
293 | case mm_fmov0_op: | |
294 | case mm_fmov1_op: | |
295 | case mm_fabs0_op: | |
296 | case mm_fabs1_op: | |
297 | case mm_fneg0_op: | |
298 | case mm_fneg1_op: | |
299 | if ((insn.mm_fp1_format.op & 0x7f) == | |
300 | mm_fmov0_op) | |
301 | func = fmov_op; | |
302 | else if ((insn.mm_fp1_format.op & 0x7f) == | |
303 | mm_fabs0_op) | |
304 | func = fabs_op; | |
305 | else | |
306 | func = fneg_op; | |
307 | mips32_insn.fp0_format.opcode = cop1_op; | |
308 | mips32_insn.fp0_format.fmt = | |
309 | sdps_format[insn.mm_fp3_format.fmt]; | |
310 | mips32_insn.fp0_format.ft = 0; | |
311 | mips32_insn.fp0_format.fs = | |
312 | insn.mm_fp3_format.fs; | |
313 | mips32_insn.fp0_format.fd = | |
314 | insn.mm_fp3_format.rt; | |
315 | mips32_insn.fp0_format.func = func; | |
316 | break; | |
317 | case mm_ffloorl_op: | |
318 | case mm_ffloorw_op: | |
319 | case mm_fceill_op: | |
320 | case mm_fceilw_op: | |
321 | case mm_ftruncl_op: | |
322 | case mm_ftruncw_op: | |
323 | case mm_froundl_op: | |
324 | case mm_froundw_op: | |
325 | case mm_fcvtl_op: | |
326 | case mm_fcvtw_op: | |
327 | if (insn.mm_fp1_format.op == mm_ffloorl_op) | |
328 | func = ffloorl_op; | |
329 | else if (insn.mm_fp1_format.op == mm_ffloorw_op) | |
330 | func = ffloor_op; | |
331 | else if (insn.mm_fp1_format.op == mm_fceill_op) | |
332 | func = fceill_op; | |
333 | else if (insn.mm_fp1_format.op == mm_fceilw_op) | |
334 | func = fceil_op; | |
335 | else if (insn.mm_fp1_format.op == mm_ftruncl_op) | |
336 | func = ftruncl_op; | |
337 | else if (insn.mm_fp1_format.op == mm_ftruncw_op) | |
338 | func = ftrunc_op; | |
339 | else if (insn.mm_fp1_format.op == mm_froundl_op) | |
340 | func = froundl_op; | |
341 | else if (insn.mm_fp1_format.op == mm_froundw_op) | |
342 | func = fround_op; | |
343 | else if (insn.mm_fp1_format.op == mm_fcvtl_op) | |
344 | func = fcvtl_op; | |
345 | else | |
346 | func = fcvtw_op; | |
347 | mips32_insn.fp0_format.opcode = cop1_op; | |
348 | mips32_insn.fp0_format.fmt = | |
349 | sd_format[insn.mm_fp1_format.fmt]; | |
350 | mips32_insn.fp0_format.ft = 0; | |
351 | mips32_insn.fp0_format.fs = | |
352 | insn.mm_fp1_format.fs; | |
353 | mips32_insn.fp0_format.fd = | |
354 | insn.mm_fp1_format.rt; | |
355 | mips32_insn.fp0_format.func = func; | |
356 | break; | |
357 | case mm_frsqrt_op: | |
358 | case mm_fsqrt_op: | |
359 | case mm_frecip_op: | |
360 | if (insn.mm_fp1_format.op == mm_frsqrt_op) | |
361 | func = frsqrt_op; | |
362 | else if (insn.mm_fp1_format.op == mm_fsqrt_op) | |
363 | func = fsqrt_op; | |
364 | else | |
365 | func = frecip_op; | |
366 | mips32_insn.fp0_format.opcode = cop1_op; | |
367 | mips32_insn.fp0_format.fmt = | |
368 | sdps_format[insn.mm_fp1_format.fmt]; | |
369 | mips32_insn.fp0_format.ft = 0; | |
370 | mips32_insn.fp0_format.fs = | |
371 | insn.mm_fp1_format.fs; | |
372 | mips32_insn.fp0_format.fd = | |
373 | insn.mm_fp1_format.rt; | |
374 | mips32_insn.fp0_format.func = func; | |
375 | break; | |
376 | case mm_mfc1_op: | |
377 | case mm_mtc1_op: | |
378 | case mm_cfc1_op: | |
379 | case mm_ctc1_op: | |
9355e59c SH |
380 | case mm_mfhc1_op: |
381 | case mm_mthc1_op: | |
102cedc3 LY |
382 | if (insn.mm_fp1_format.op == mm_mfc1_op) |
383 | op = mfc_op; | |
384 | else if (insn.mm_fp1_format.op == mm_mtc1_op) | |
385 | op = mtc_op; | |
386 | else if (insn.mm_fp1_format.op == mm_cfc1_op) | |
387 | op = cfc_op; | |
9355e59c | 388 | else if (insn.mm_fp1_format.op == mm_ctc1_op) |
102cedc3 | 389 | op = ctc_op; |
9355e59c SH |
390 | else if (insn.mm_fp1_format.op == mm_mfhc1_op) |
391 | op = mfhc_op; | |
392 | else | |
393 | op = mthc_op; | |
102cedc3 LY |
394 | mips32_insn.fp1_format.opcode = cop1_op; |
395 | mips32_insn.fp1_format.op = op; | |
396 | mips32_insn.fp1_format.rt = | |
397 | insn.mm_fp1_format.rt; | |
398 | mips32_insn.fp1_format.fs = | |
399 | insn.mm_fp1_format.fs; | |
400 | mips32_insn.fp1_format.fd = 0; | |
401 | mips32_insn.fp1_format.func = 0; | |
402 | break; | |
403 | default: | |
404 | return SIGILL; | |
102cedc3 LY |
405 | } |
406 | break; | |
407 | case mm_32f_74_op: /* c.cond.fmt */ | |
408 | mips32_insn.fp0_format.opcode = cop1_op; | |
409 | mips32_insn.fp0_format.fmt = | |
410 | sdps_format[insn.mm_fp4_format.fmt]; | |
411 | mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; | |
412 | mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; | |
413 | mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; | |
414 | mips32_insn.fp0_format.func = | |
415 | insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; | |
416 | break; | |
417 | default: | |
418 | return SIGILL; | |
102cedc3 LY |
419 | } |
420 | break; | |
421 | default: | |
422 | return SIGILL; | |
102cedc3 LY |
423 | } |
424 | ||
425 | *insn_ptr = mips32_insn; | |
426 | return 0; | |
427 | } | |
428 | ||
1da177e4 LT |
429 | /* |
430 | * Redundant with logic already in kernel/branch.c, | |
431 | * embedded in compute_return_epc. At some point, | |
432 | * a single subroutine should be used across both | |
433 | * modules. | |
434 | */ | |
102cedc3 LY |
435 | static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, |
436 | unsigned long *contpc) | |
1da177e4 | 437 | { |
102cedc3 LY |
438 | union mips_instruction insn = (union mips_instruction)dec_insn.insn; |
439 | unsigned int fcr31; | |
440 | unsigned int bit = 0; | |
441 | ||
442 | switch (insn.i_format.opcode) { | |
1da177e4 | 443 | case spec_op: |
102cedc3 | 444 | switch (insn.r_format.func) { |
1da177e4 | 445 | case jalr_op: |
102cedc3 LY |
446 | regs->regs[insn.r_format.rd] = |
447 | regs->cp0_epc + dec_insn.pc_inc + | |
448 | dec_insn.next_pc_inc; | |
449 | /* Fall through */ | |
1da177e4 | 450 | case jr_op: |
102cedc3 | 451 | *contpc = regs->regs[insn.r_format.rs]; |
1da177e4 LT |
452 | return 1; |
453 | } | |
454 | break; | |
1da177e4 | 455 | case bcond_op: |
102cedc3 LY |
456 | switch (insn.i_format.rt) { |
457 | case bltzal_op: | |
458 | case bltzall_op: | |
459 | regs->regs[31] = regs->cp0_epc + | |
460 | dec_insn.pc_inc + | |
461 | dec_insn.next_pc_inc; | |
462 | /* Fall through */ | |
1da177e4 | 463 | case bltz_op: |
1da177e4 | 464 | case bltzl_op: |
102cedc3 LY |
465 | if ((long)regs->regs[insn.i_format.rs] < 0) |
466 | *contpc = regs->cp0_epc + | |
467 | dec_insn.pc_inc + | |
468 | (insn.i_format.simmediate << 2); | |
469 | else | |
470 | *contpc = regs->cp0_epc + | |
471 | dec_insn.pc_inc + | |
472 | dec_insn.next_pc_inc; | |
473 | return 1; | |
1da177e4 | 474 | case bgezal_op: |
1da177e4 | 475 | case bgezall_op: |
102cedc3 LY |
476 | regs->regs[31] = regs->cp0_epc + |
477 | dec_insn.pc_inc + | |
478 | dec_insn.next_pc_inc; | |
479 | /* Fall through */ | |
480 | case bgez_op: | |
481 | case bgezl_op: | |
482 | if ((long)regs->regs[insn.i_format.rs] >= 0) | |
483 | *contpc = regs->cp0_epc + | |
484 | dec_insn.pc_inc + | |
485 | (insn.i_format.simmediate << 2); | |
486 | else | |
487 | *contpc = regs->cp0_epc + | |
488 | dec_insn.pc_inc + | |
489 | dec_insn.next_pc_inc; | |
1da177e4 LT |
490 | return 1; |
491 | } | |
492 | break; | |
1da177e4 | 493 | case jalx_op: |
102cedc3 LY |
494 | set_isa16_mode(bit); |
495 | case jal_op: | |
496 | regs->regs[31] = regs->cp0_epc + | |
497 | dec_insn.pc_inc + | |
498 | dec_insn.next_pc_inc; | |
499 | /* Fall through */ | |
500 | case j_op: | |
501 | *contpc = regs->cp0_epc + dec_insn.pc_inc; | |
502 | *contpc >>= 28; | |
503 | *contpc <<= 28; | |
504 | *contpc |= (insn.j_format.target << 2); | |
505 | /* Set microMIPS mode bit: XOR for jalx. */ | |
506 | *contpc ^= bit; | |
507 | return 1; | |
1da177e4 | 508 | case beq_op: |
1da177e4 | 509 | case beql_op: |
102cedc3 LY |
510 | if (regs->regs[insn.i_format.rs] == |
511 | regs->regs[insn.i_format.rt]) | |
512 | *contpc = regs->cp0_epc + | |
513 | dec_insn.pc_inc + | |
514 | (insn.i_format.simmediate << 2); | |
515 | else | |
516 | *contpc = regs->cp0_epc + | |
517 | dec_insn.pc_inc + | |
518 | dec_insn.next_pc_inc; | |
519 | return 1; | |
102cedc3 | 520 | case bne_op: |
1da177e4 | 521 | case bnel_op: |
102cedc3 LY |
522 | if (regs->regs[insn.i_format.rs] != |
523 | regs->regs[insn.i_format.rt]) | |
524 | *contpc = regs->cp0_epc + | |
525 | dec_insn.pc_inc + | |
526 | (insn.i_format.simmediate << 2); | |
527 | else | |
528 | *contpc = regs->cp0_epc + | |
529 | dec_insn.pc_inc + | |
530 | dec_insn.next_pc_inc; | |
531 | return 1; | |
102cedc3 | 532 | case blez_op: |
1da177e4 | 533 | case blezl_op: |
102cedc3 LY |
534 | if ((long)regs->regs[insn.i_format.rs] <= 0) |
535 | *contpc = regs->cp0_epc + | |
536 | dec_insn.pc_inc + | |
537 | (insn.i_format.simmediate << 2); | |
538 | else | |
539 | *contpc = regs->cp0_epc + | |
540 | dec_insn.pc_inc + | |
541 | dec_insn.next_pc_inc; | |
542 | return 1; | |
102cedc3 | 543 | case bgtz_op: |
1da177e4 | 544 | case bgtzl_op: |
102cedc3 LY |
545 | if ((long)regs->regs[insn.i_format.rs] > 0) |
546 | *contpc = regs->cp0_epc + | |
547 | dec_insn.pc_inc + | |
548 | (insn.i_format.simmediate << 2); | |
549 | else | |
550 | *contpc = regs->cp0_epc + | |
551 | dec_insn.pc_inc + | |
552 | dec_insn.next_pc_inc; | |
1da177e4 | 553 | return 1; |
c26d4219 DD |
554 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
555 | case lwc2_op: /* This is bbit0 on Octeon */ | |
556 | if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) | |
557 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
558 | else | |
559 | *contpc = regs->cp0_epc + 8; | |
560 | return 1; | |
561 | case ldc2_op: /* This is bbit032 on Octeon */ | |
562 | if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) | |
563 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
564 | else | |
565 | *contpc = regs->cp0_epc + 8; | |
566 | return 1; | |
567 | case swc2_op: /* This is bbit1 on Octeon */ | |
568 | if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) | |
569 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
570 | else | |
571 | *contpc = regs->cp0_epc + 8; | |
572 | return 1; | |
573 | case sdc2_op: /* This is bbit132 on Octeon */ | |
574 | if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) | |
575 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
576 | else | |
577 | *contpc = regs->cp0_epc + 8; | |
578 | return 1; | |
579 | #endif | |
1da177e4 LT |
580 | case cop0_op: |
581 | case cop1_op: | |
582 | case cop2_op: | |
583 | case cop1x_op: | |
102cedc3 LY |
584 | if (insn.i_format.rs == bc_op) { |
585 | preempt_disable(); | |
586 | if (is_fpu_owner()) | |
587 | asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); | |
588 | else | |
589 | fcr31 = current->thread.fpu.fcr31; | |
590 | preempt_enable(); | |
591 | ||
592 | bit = (insn.i_format.rt >> 2); | |
593 | bit += (bit != 0); | |
594 | bit += 23; | |
595 | switch (insn.i_format.rt & 3) { | |
596 | case 0: /* bc1f */ | |
597 | case 2: /* bc1fl */ | |
598 | if (~fcr31 & (1 << bit)) | |
599 | *contpc = regs->cp0_epc + | |
600 | dec_insn.pc_inc + | |
601 | (insn.i_format.simmediate << 2); | |
602 | else | |
603 | *contpc = regs->cp0_epc + | |
604 | dec_insn.pc_inc + | |
605 | dec_insn.next_pc_inc; | |
606 | return 1; | |
102cedc3 LY |
607 | case 1: /* bc1t */ |
608 | case 3: /* bc1tl */ | |
609 | if (fcr31 & (1 << bit)) | |
610 | *contpc = regs->cp0_epc + | |
611 | dec_insn.pc_inc + | |
612 | (insn.i_format.simmediate << 2); | |
613 | else | |
614 | *contpc = regs->cp0_epc + | |
615 | dec_insn.pc_inc + | |
616 | dec_insn.next_pc_inc; | |
617 | return 1; | |
102cedc3 LY |
618 | } |
619 | } | |
1da177e4 LT |
620 | break; |
621 | } | |
1da177e4 LT |
622 | return 0; |
623 | } | |
624 | ||
625 | /* | |
626 | * In the Linux kernel, we support selection of FPR format on the | |
70342287 | 627 | * basis of the Status.FR bit. If an FPU is not present, the FR bit |
da0bac33 | 628 | * is hardwired to zero, which would imply a 32-bit FPU even for |
597ce172 | 629 | * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. |
51d943f0 RB |
630 | * FPU emu is slow and bulky and optimizing this function offers fairly |
631 | * sizeable benefits so we try to be clever and make this function return | |
632 | * a constant whenever possible, that is on 64-bit kernels without O32 | |
597ce172 | 633 | * compatibility enabled and on 32-bit without 64-bit FPU support. |
1da177e4 | 634 | */ |
da0bac33 DD |
635 | static inline int cop1_64bit(struct pt_regs *xcp) |
636 | { | |
08a07904 RB |
637 | if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) |
638 | return 1; | |
639 | else if (config_enabled(CONFIG_32BIT) && | |
640 | !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) | |
641 | return 0; | |
642 | ||
597ce172 | 643 | return !test_thread_flag(TIF_32BIT_FPREGS); |
da0bac33 DD |
644 | } |
645 | ||
47fa0c02 RB |
646 | #define SIFROMREG(si, x) \ |
647 | do { \ | |
bbd426f5 PB |
648 | if (cop1_64bit(xcp)) \ |
649 | (si) = get_fpr32(&ctx->fpr[x], 0); \ | |
650 | else \ | |
651 | (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ | |
652 | } while (0) | |
1da177e4 | 653 | |
47fa0c02 RB |
654 | #define SITOREG(si, x) \ |
655 | do { \ | |
ef1c47af PB |
656 | if (cop1_64bit(xcp)) { \ |
657 | unsigned i; \ | |
bbd426f5 | 658 | set_fpr32(&ctx->fpr[x], 0, si); \ |
ef1c47af PB |
659 | for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ |
660 | set_fpr32(&ctx->fpr[x], i, 0); \ | |
661 | } else { \ | |
bbd426f5 | 662 | set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ |
ef1c47af | 663 | } \ |
bbd426f5 | 664 | } while (0) |
1da177e4 | 665 | |
bbd426f5 | 666 | #define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1)) |
ef1c47af | 667 | |
47fa0c02 RB |
668 | #define SITOHREG(si, x) \ |
669 | do { \ | |
ef1c47af PB |
670 | unsigned i; \ |
671 | set_fpr32(&ctx->fpr[x], 1, si); \ | |
672 | for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ | |
673 | set_fpr32(&ctx->fpr[x], i, 0); \ | |
674 | } while (0) | |
1ac94400 | 675 | |
47fa0c02 | 676 | #define DIFROMREG(di, x) \ |
bbd426f5 PB |
677 | ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) |
678 | ||
47fa0c02 RB |
679 | #define DITOREG(di, x) \ |
680 | do { \ | |
ef1c47af PB |
681 | unsigned fpr, i; \ |
682 | fpr = (x) & ~(cop1_64bit(xcp) == 0); \ | |
683 | set_fpr64(&ctx->fpr[fpr], 0, di); \ | |
684 | for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ | |
685 | set_fpr64(&ctx->fpr[fpr], i, 0); \ | |
686 | } while (0) | |
1da177e4 | 687 | |
21a151d8 RB |
688 | #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) |
689 | #define SPTOREG(sp, x) SITOREG((sp).bits, x) | |
690 | #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) | |
691 | #define DPTOREG(dp, x) DITOREG((dp).bits, x) | |
1da177e4 LT |
692 | |
693 | /* | |
694 | * Emulate the single floating point instruction pointed at by EPC. | |
695 | * Two instructions if the instruction is in a branch delay slot. | |
696 | */ | |
697 | ||
515b029d | 698 | static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
102cedc3 | 699 | struct mm_decoded_insn dec_insn, void *__user *fault_addr) |
1da177e4 | 700 | { |
102cedc3 | 701 | unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; |
3f7cac41 RB |
702 | unsigned int cond, cbit; |
703 | mips_instruction ir; | |
704 | int likely, pc_inc; | |
705 | u32 __user *wva; | |
706 | u64 __user *dva; | |
707 | u32 value; | |
708 | u32 wval; | |
709 | u64 dval; | |
710 | int sig; | |
1da177e4 LT |
711 | |
712 | /* XXX NEC Vr54xx bug workaround */ | |
e7e9cae5 | 713 | if (delay_slot(xcp)) { |
102cedc3 LY |
714 | if (dec_insn.micro_mips_mode) { |
715 | if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) | |
e7e9cae5 | 716 | clear_delay_slot(xcp); |
102cedc3 LY |
717 | } else { |
718 | if (!isBranchInstr(xcp, dec_insn, &contpc)) | |
e7e9cae5 | 719 | clear_delay_slot(xcp); |
102cedc3 LY |
720 | } |
721 | } | |
1da177e4 | 722 | |
e7e9cae5 | 723 | if (delay_slot(xcp)) { |
1da177e4 LT |
724 | /* |
725 | * The instruction to be emulated is in a branch delay slot | |
70342287 | 726 | * which means that we have to emulate the branch instruction |
1da177e4 LT |
727 | * BEFORE we do the cop1 instruction. |
728 | * | |
729 | * This branch could be a COP1 branch, but in that case we | |
730 | * would have had a trap for that instruction, and would not | |
731 | * come through this route. | |
732 | * | |
733 | * Linux MIPS branch emulator operates on context, updating the | |
734 | * cp0_epc. | |
735 | */ | |
102cedc3 LY |
736 | ir = dec_insn.next_insn; /* process delay slot instr */ |
737 | pc_inc = dec_insn.next_pc_inc; | |
738 | } else { | |
739 | ir = dec_insn.insn; /* process current instr */ | |
740 | pc_inc = dec_insn.pc_inc; | |
741 | } | |
1da177e4 | 742 | |
102cedc3 LY |
743 | /* |
744 | * Since microMIPS FPU instructios are a subset of MIPS32 FPU | |
745 | * instructions, we want to convert microMIPS FPU instructions | |
746 | * into MIPS32 instructions so that we could reuse all of the | |
747 | * FPU emulation code. | |
748 | * | |
749 | * NOTE: We cannot do this for branch instructions since they | |
750 | * are not a subset. Example: Cannot emulate a 16-bit | |
751 | * aligned target address with a MIPS32 instruction. | |
752 | */ | |
753 | if (dec_insn.micro_mips_mode) { | |
754 | /* | |
755 | * If next instruction is a 16-bit instruction, then it | |
756 | * it cannot be a FPU instruction. This could happen | |
757 | * since we can be called for non-FPU instructions. | |
758 | */ | |
759 | if ((pc_inc == 2) || | |
760 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) | |
761 | == SIGILL)) | |
1da177e4 | 762 | return SIGILL; |
1da177e4 LT |
763 | } |
764 | ||
3f7cac41 | 765 | emul: |
a8b0ca17 | 766 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); |
b6ee75ed | 767 | MIPS_FPU_EMU_INC_STATS(emulated); |
1da177e4 | 768 | switch (MIPSInst_OPCODE(ir)) { |
3f7cac41 RB |
769 | case ldc1_op: |
770 | dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
771 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 772 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 773 | |
3f7cac41 | 774 | if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { |
b6ee75ed | 775 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 776 | *fault_addr = dva; |
1da177e4 LT |
777 | return SIGBUS; |
778 | } | |
3f7cac41 | 779 | if (__get_user(dval, dva)) { |
515b029d | 780 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 781 | *fault_addr = dva; |
515b029d DD |
782 | return SIGSEGV; |
783 | } | |
3f7cac41 | 784 | DITOREG(dval, MIPSInst_RT(ir)); |
1da177e4 | 785 | break; |
1da177e4 | 786 | |
3f7cac41 RB |
787 | case sdc1_op: |
788 | dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
789 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 790 | MIPS_FPU_EMU_INC_STATS(stores); |
3f7cac41 RB |
791 | DIFROMREG(dval, MIPSInst_RT(ir)); |
792 | if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { | |
b6ee75ed | 793 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 794 | *fault_addr = dva; |
1da177e4 LT |
795 | return SIGBUS; |
796 | } | |
3f7cac41 | 797 | if (__put_user(dval, dva)) { |
515b029d | 798 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 799 | *fault_addr = dva; |
515b029d DD |
800 | return SIGSEGV; |
801 | } | |
1da177e4 | 802 | break; |
1da177e4 | 803 | |
3f7cac41 RB |
804 | case lwc1_op: |
805 | wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
806 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 807 | MIPS_FPU_EMU_INC_STATS(loads); |
3f7cac41 | 808 | if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { |
b6ee75ed | 809 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 810 | *fault_addr = wva; |
1da177e4 LT |
811 | return SIGBUS; |
812 | } | |
3f7cac41 | 813 | if (__get_user(wval, wva)) { |
515b029d | 814 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 815 | *fault_addr = wva; |
515b029d DD |
816 | return SIGSEGV; |
817 | } | |
3f7cac41 | 818 | SITOREG(wval, MIPSInst_RT(ir)); |
1da177e4 | 819 | break; |
1da177e4 | 820 | |
3f7cac41 RB |
821 | case swc1_op: |
822 | wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
823 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 824 | MIPS_FPU_EMU_INC_STATS(stores); |
3f7cac41 RB |
825 | SIFROMREG(wval, MIPSInst_RT(ir)); |
826 | if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { | |
b6ee75ed | 827 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 828 | *fault_addr = wva; |
1da177e4 LT |
829 | return SIGBUS; |
830 | } | |
3f7cac41 | 831 | if (__put_user(wval, wva)) { |
515b029d | 832 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 833 | *fault_addr = wva; |
515b029d DD |
834 | return SIGSEGV; |
835 | } | |
1da177e4 | 836 | break; |
1da177e4 LT |
837 | |
838 | case cop1_op: | |
839 | switch (MIPSInst_RS(ir)) { | |
1da177e4 | 840 | case dmfc_op: |
08a07904 RB |
841 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
842 | return SIGILL; | |
843 | ||
1da177e4 LT |
844 | /* copregister fs -> gpr[rt] */ |
845 | if (MIPSInst_RT(ir) != 0) { | |
846 | DIFROMREG(xcp->regs[MIPSInst_RT(ir)], | |
847 | MIPSInst_RD(ir)); | |
848 | } | |
849 | break; | |
850 | ||
851 | case dmtc_op: | |
08a07904 RB |
852 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
853 | return SIGILL; | |
854 | ||
1da177e4 LT |
855 | /* copregister fs <- rt */ |
856 | DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); | |
857 | break; | |
1da177e4 | 858 | |
1ac94400 LY |
859 | case mfhc_op: |
860 | if (!cpu_has_mips_r2) | |
861 | goto sigill; | |
862 | ||
863 | /* copregister rd -> gpr[rt] */ | |
864 | if (MIPSInst_RT(ir) != 0) { | |
865 | SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], | |
866 | MIPSInst_RD(ir)); | |
867 | } | |
868 | break; | |
869 | ||
870 | case mthc_op: | |
871 | if (!cpu_has_mips_r2) | |
872 | goto sigill; | |
873 | ||
874 | /* copregister rd <- gpr[rt] */ | |
875 | SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); | |
876 | break; | |
877 | ||
1da177e4 LT |
878 | case mfc_op: |
879 | /* copregister rd -> gpr[rt] */ | |
1da177e4 LT |
880 | if (MIPSInst_RT(ir) != 0) { |
881 | SIFROMREG(xcp->regs[MIPSInst_RT(ir)], | |
882 | MIPSInst_RD(ir)); | |
883 | } | |
884 | break; | |
885 | ||
886 | case mtc_op: | |
887 | /* copregister rd <- rt */ | |
1da177e4 LT |
888 | SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); |
889 | break; | |
890 | ||
3f7cac41 | 891 | case cfc_op: |
1da177e4 | 892 | /* cop control register rd -> gpr[rt] */ |
1da177e4 LT |
893 | if (MIPSInst_RD(ir) == FPCREG_CSR) { |
894 | value = ctx->fcr31; | |
56a64733 | 895 | value = (value & ~FPU_CSR_RM) | modeindex(value); |
92df0f8b RB |
896 | pr_debug("%p gpr[%d]<-csr=%08x\n", |
897 | (void *) (xcp->cp0_epc), | |
898 | MIPSInst_RT(ir), value); | |
1da177e4 LT |
899 | } |
900 | else if (MIPSInst_RD(ir) == FPCREG_RID) | |
901 | value = 0; | |
902 | else | |
903 | value = 0; | |
904 | if (MIPSInst_RT(ir)) | |
905 | xcp->regs[MIPSInst_RT(ir)] = value; | |
906 | break; | |
1da177e4 | 907 | |
3f7cac41 | 908 | case ctc_op: |
1da177e4 | 909 | /* copregister rd <- rt */ |
1da177e4 LT |
910 | if (MIPSInst_RT(ir) == 0) |
911 | value = 0; | |
912 | else | |
913 | value = xcp->regs[MIPSInst_RT(ir)]; | |
914 | ||
915 | /* we only have one writable control reg | |
916 | */ | |
917 | if (MIPSInst_RD(ir) == FPCREG_CSR) { | |
92df0f8b RB |
918 | pr_debug("%p gpr[%d]->csr=%08x\n", |
919 | (void *) (xcp->cp0_epc), | |
920 | MIPSInst_RT(ir), value); | |
95e8f634 SM |
921 | |
922 | /* | |
923 | * Don't write reserved bits, | |
924 | * and convert to ieee library modes | |
925 | */ | |
56a64733 RB |
926 | ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) | |
927 | modeindex(value); | |
1da177e4 LT |
928 | } |
929 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { | |
930 | return SIGFPE; | |
931 | } | |
932 | break; | |
1da177e4 | 933 | |
3f7cac41 | 934 | case bc_op: |
e7e9cae5 | 935 | if (delay_slot(xcp)) |
1da177e4 LT |
936 | return SIGILL; |
937 | ||
08a07904 RB |
938 | if (cpu_has_mips_4_5_r) |
939 | cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
940 | else | |
941 | cbit = FPU_CSR_COND; | |
942 | cond = ctx->fcr31 & cbit; | |
943 | ||
3f7cac41 | 944 | likely = 0; |
1da177e4 LT |
945 | switch (MIPSInst_RT(ir) & 3) { |
946 | case bcfl_op: | |
947 | likely = 1; | |
948 | case bcf_op: | |
949 | cond = !cond; | |
950 | break; | |
951 | case bctl_op: | |
952 | likely = 1; | |
953 | case bct_op: | |
954 | break; | |
955 | default: | |
956 | /* thats an illegal instruction */ | |
957 | return SIGILL; | |
958 | } | |
959 | ||
e7e9cae5 | 960 | set_delay_slot(xcp); |
1da177e4 | 961 | if (cond) { |
3f7cac41 RB |
962 | /* |
963 | * Branch taken: emulate dslot instruction | |
1da177e4 | 964 | */ |
102cedc3 LY |
965 | xcp->cp0_epc += dec_insn.pc_inc; |
966 | ||
967 | contpc = MIPSInst_SIMM(ir); | |
968 | ir = dec_insn.next_insn; | |
969 | if (dec_insn.micro_mips_mode) { | |
970 | contpc = (xcp->cp0_epc + (contpc << 1)); | |
971 | ||
972 | /* If 16-bit instruction, not FPU. */ | |
973 | if ((dec_insn.next_pc_inc == 2) || | |
974 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { | |
975 | ||
976 | /* | |
977 | * Since this instruction will | |
978 | * be put on the stack with | |
979 | * 32-bit words, get around | |
980 | * this problem by putting a | |
981 | * NOP16 as the second one. | |
982 | */ | |
983 | if (dec_insn.next_pc_inc == 2) | |
984 | ir = (ir & (~0xffff)) | MM_NOP16; | |
985 | ||
986 | /* | |
987 | * Single step the non-CP1 | |
988 | * instruction in the dslot. | |
989 | */ | |
990 | return mips_dsemul(xcp, ir, contpc); | |
991 | } | |
992 | } else | |
993 | contpc = (xcp->cp0_epc + (contpc << 2)); | |
1da177e4 LT |
994 | |
995 | switch (MIPSInst_OPCODE(ir)) { | |
996 | case lwc1_op: | |
08a07904 | 997 | goto emul; |
3f7cac41 | 998 | |
1da177e4 | 999 | case swc1_op: |
08a07904 | 1000 | goto emul; |
3f7cac41 | 1001 | |
1da177e4 LT |
1002 | case ldc1_op: |
1003 | case sdc1_op: | |
08a07904 RB |
1004 | if (cpu_has_mips_2_3_4_5 || |
1005 | cpu_has_mips64) | |
1006 | goto emul; | |
1007 | ||
1008 | return SIGILL; | |
1009 | goto emul; | |
3f7cac41 | 1010 | |
1da177e4 | 1011 | case cop1_op: |
1da177e4 | 1012 | goto emul; |
3f7cac41 | 1013 | |
08a07904 RB |
1014 | case cop1x_op: |
1015 | if (cpu_has_mips_4_5 || cpu_has_mips64) | |
1016 | /* its one of ours */ | |
1017 | goto emul; | |
1018 | ||
1019 | return SIGILL; | |
3f7cac41 | 1020 | |
1da177e4 | 1021 | case spec_op: |
08a07904 RB |
1022 | if (!cpu_has_mips_4_5_r) |
1023 | return SIGILL; | |
1024 | ||
1da177e4 LT |
1025 | if (MIPSInst_FUNC(ir) == movc_op) |
1026 | goto emul; | |
1027 | break; | |
1da177e4 LT |
1028 | } |
1029 | ||
1030 | /* | |
1031 | * Single step the non-cp1 | |
1032 | * instruction in the dslot | |
1033 | */ | |
e70dfc10 | 1034 | return mips_dsemul(xcp, ir, contpc); |
3f7cac41 | 1035 | } else if (likely) { /* branch not taken */ |
1da177e4 LT |
1036 | /* |
1037 | * branch likely nullifies | |
1038 | * dslot if not taken | |
1039 | */ | |
102cedc3 LY |
1040 | xcp->cp0_epc += dec_insn.pc_inc; |
1041 | contpc += dec_insn.pc_inc; | |
1da177e4 LT |
1042 | /* |
1043 | * else continue & execute | |
1044 | * dslot as normal insn | |
1045 | */ | |
1046 | } | |
1da177e4 | 1047 | break; |
1da177e4 LT |
1048 | |
1049 | default: | |
1050 | if (!(MIPSInst_RS(ir) & 0x10)) | |
1051 | return SIGILL; | |
1da177e4 | 1052 | |
3f7cac41 RB |
1053 | /* a real fpu computation instruction */ |
1054 | if ((sig = fpu_emu(xcp, ctx, ir))) | |
1055 | return sig; | |
1da177e4 LT |
1056 | } |
1057 | break; | |
1058 | ||
3f7cac41 | 1059 | case cop1x_op: |
08a07904 RB |
1060 | if (!cpu_has_mips_4_5 && !cpu_has_mips64) |
1061 | return SIGILL; | |
1062 | ||
1063 | sig = fpux_emu(xcp, ctx, ir, fault_addr); | |
515b029d | 1064 | if (sig) |
1da177e4 LT |
1065 | return sig; |
1066 | break; | |
1da177e4 | 1067 | |
1da177e4 | 1068 | case spec_op: |
08a07904 RB |
1069 | if (!cpu_has_mips_4_5_r) |
1070 | return SIGILL; | |
1071 | ||
1da177e4 LT |
1072 | if (MIPSInst_FUNC(ir) != movc_op) |
1073 | return SIGILL; | |
1074 | cond = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
1075 | if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) | |
1076 | xcp->regs[MIPSInst_RD(ir)] = | |
1077 | xcp->regs[MIPSInst_RS(ir)]; | |
1078 | break; | |
1da177e4 | 1079 | default: |
1ac94400 | 1080 | sigill: |
1da177e4 LT |
1081 | return SIGILL; |
1082 | } | |
1083 | ||
1084 | /* we did it !! */ | |
e70dfc10 | 1085 | xcp->cp0_epc = contpc; |
e7e9cae5 | 1086 | clear_delay_slot(xcp); |
333d1f67 | 1087 | |
1da177e4 LT |
1088 | return 0; |
1089 | } | |
1090 | ||
1091 | /* | |
1092 | * Conversion table from MIPS compare ops 48-63 | |
1093 | * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); | |
1094 | */ | |
1095 | static const unsigned char cmptab[8] = { | |
1096 | 0, /* cmp_0 (sig) cmp_sf */ | |
1097 | IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ | |
1098 | IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ | |
1099 | IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ | |
1100 | IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ | |
1101 | IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ | |
1102 | IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ | |
1103 | IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ | |
1104 | }; | |
1105 | ||
1106 | ||
1da177e4 LT |
1107 | /* |
1108 | * Additional MIPS4 instructions | |
1109 | */ | |
1110 | ||
47fa0c02 RB |
1111 | #define DEF3OP(name, p, f1, f2, f3) \ |
1112 | static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ | |
1113 | union ieee754##p s, union ieee754##p t) \ | |
1114 | { \ | |
1115 | struct _ieee754_csr ieee754_csr_save; \ | |
1116 | s = f1(s, t); \ | |
1117 | ieee754_csr_save = ieee754_csr; \ | |
1118 | s = f2(s, r); \ | |
1119 | ieee754_csr_save.cx |= ieee754_csr.cx; \ | |
1120 | ieee754_csr_save.sx |= ieee754_csr.sx; \ | |
1121 | s = f3(s); \ | |
1122 | ieee754_csr.cx |= ieee754_csr_save.cx; \ | |
1123 | ieee754_csr.sx |= ieee754_csr_save.sx; \ | |
1124 | return s; \ | |
1da177e4 LT |
1125 | } |
1126 | ||
2209bcb1 | 1127 | static union ieee754dp fpemu_dp_recip(union ieee754dp d) |
1da177e4 LT |
1128 | { |
1129 | return ieee754dp_div(ieee754dp_one(0), d); | |
1130 | } | |
1131 | ||
2209bcb1 | 1132 | static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) |
1da177e4 LT |
1133 | { |
1134 | return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); | |
1135 | } | |
1136 | ||
2209bcb1 | 1137 | static union ieee754sp fpemu_sp_recip(union ieee754sp s) |
1da177e4 LT |
1138 | { |
1139 | return ieee754sp_div(ieee754sp_one(0), s); | |
1140 | } | |
1141 | ||
2209bcb1 | 1142 | static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) |
1da177e4 LT |
1143 | { |
1144 | return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); | |
1145 | } | |
1146 | ||
21a151d8 RB |
1147 | DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); |
1148 | DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); | |
1da177e4 LT |
1149 | DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); |
1150 | DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); | |
21a151d8 RB |
1151 | DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); |
1152 | DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); | |
1da177e4 LT |
1153 | DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); |
1154 | DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); | |
1155 | ||
eae89076 | 1156 | static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
515b029d | 1157 | mips_instruction ir, void *__user *fault_addr) |
1da177e4 LT |
1158 | { |
1159 | unsigned rcsr = 0; /* resulting csr */ | |
1160 | ||
b6ee75ed | 1161 | MIPS_FPU_EMU_INC_STATS(cp1xops); |
1da177e4 LT |
1162 | |
1163 | switch (MIPSInst_FMA_FFMT(ir)) { | |
1164 | case s_fmt:{ /* 0 */ | |
1165 | ||
2209bcb1 RB |
1166 | union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); |
1167 | union ieee754sp fd, fr, fs, ft; | |
3fccc015 | 1168 | u32 __user *va; |
1da177e4 LT |
1169 | u32 val; |
1170 | ||
1171 | switch (MIPSInst_FUNC(ir)) { | |
1172 | case lwxc1_op: | |
3fccc015 | 1173 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1174 | xcp->regs[MIPSInst_FT(ir)]); |
1175 | ||
b6ee75ed | 1176 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1177 | if (!access_ok(VERIFY_READ, va, sizeof(u32))) { |
b6ee75ed | 1178 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1179 | *fault_addr = va; |
1da177e4 LT |
1180 | return SIGBUS; |
1181 | } | |
515b029d DD |
1182 | if (__get_user(val, va)) { |
1183 | MIPS_FPU_EMU_INC_STATS(errors); | |
1184 | *fault_addr = va; | |
1185 | return SIGSEGV; | |
1186 | } | |
1da177e4 LT |
1187 | SITOREG(val, MIPSInst_FD(ir)); |
1188 | break; | |
1189 | ||
1190 | case swxc1_op: | |
3fccc015 | 1191 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1192 | xcp->regs[MIPSInst_FT(ir)]); |
1193 | ||
b6ee75ed | 1194 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 LT |
1195 | |
1196 | SIFROMREG(val, MIPSInst_FS(ir)); | |
515b029d | 1197 | if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { |
b6ee75ed | 1198 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1199 | *fault_addr = va; |
1da177e4 LT |
1200 | return SIGBUS; |
1201 | } | |
515b029d DD |
1202 | if (put_user(val, va)) { |
1203 | MIPS_FPU_EMU_INC_STATS(errors); | |
1204 | *fault_addr = va; | |
1205 | return SIGSEGV; | |
1206 | } | |
1da177e4 LT |
1207 | break; |
1208 | ||
1209 | case madd_s_op: | |
1210 | handler = fpemu_sp_madd; | |
1211 | goto scoptop; | |
1212 | case msub_s_op: | |
1213 | handler = fpemu_sp_msub; | |
1214 | goto scoptop; | |
1215 | case nmadd_s_op: | |
1216 | handler = fpemu_sp_nmadd; | |
1217 | goto scoptop; | |
1218 | case nmsub_s_op: | |
1219 | handler = fpemu_sp_nmsub; | |
1220 | goto scoptop; | |
1221 | ||
1222 | scoptop: | |
1223 | SPFROMREG(fr, MIPSInst_FR(ir)); | |
1224 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1225 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1226 | fd = (*handler) (fr, fs, ft); | |
1227 | SPTOREG(fd, MIPSInst_FD(ir)); | |
1228 | ||
1229 | copcsr: | |
1230 | if (ieee754_cxtest(IEEE754_INEXACT)) | |
1231 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; | |
1232 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) | |
1233 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; | |
1234 | if (ieee754_cxtest(IEEE754_OVERFLOW)) | |
1235 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; | |
1236 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) | |
1237 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1238 | ||
1239 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; | |
1da177e4 | 1240 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { |
3f7cac41 | 1241 | /*printk ("SIGFPE: FPU csr = %08x\n", |
1da177e4 LT |
1242 | ctx->fcr31); */ |
1243 | return SIGFPE; | |
1244 | } | |
1245 | ||
1246 | break; | |
1247 | ||
1248 | default: | |
1249 | return SIGILL; | |
1250 | } | |
1251 | break; | |
1252 | } | |
1253 | ||
1da177e4 | 1254 | case d_fmt:{ /* 1 */ |
2209bcb1 RB |
1255 | union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); |
1256 | union ieee754dp fd, fr, fs, ft; | |
3fccc015 | 1257 | u64 __user *va; |
1da177e4 LT |
1258 | u64 val; |
1259 | ||
1260 | switch (MIPSInst_FUNC(ir)) { | |
1261 | case ldxc1_op: | |
3fccc015 | 1262 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1263 | xcp->regs[MIPSInst_FT(ir)]); |
1264 | ||
b6ee75ed | 1265 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1266 | if (!access_ok(VERIFY_READ, va, sizeof(u64))) { |
b6ee75ed | 1267 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1268 | *fault_addr = va; |
1da177e4 LT |
1269 | return SIGBUS; |
1270 | } | |
515b029d DD |
1271 | if (__get_user(val, va)) { |
1272 | MIPS_FPU_EMU_INC_STATS(errors); | |
1273 | *fault_addr = va; | |
1274 | return SIGSEGV; | |
1275 | } | |
1da177e4 LT |
1276 | DITOREG(val, MIPSInst_FD(ir)); |
1277 | break; | |
1278 | ||
1279 | case sdxc1_op: | |
3fccc015 | 1280 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1281 | xcp->regs[MIPSInst_FT(ir)]); |
1282 | ||
b6ee75ed | 1283 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 | 1284 | DIFROMREG(val, MIPSInst_FS(ir)); |
515b029d | 1285 | if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { |
b6ee75ed | 1286 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1287 | *fault_addr = va; |
1da177e4 LT |
1288 | return SIGBUS; |
1289 | } | |
515b029d DD |
1290 | if (__put_user(val, va)) { |
1291 | MIPS_FPU_EMU_INC_STATS(errors); | |
1292 | *fault_addr = va; | |
1293 | return SIGSEGV; | |
1294 | } | |
1da177e4 LT |
1295 | break; |
1296 | ||
1297 | case madd_d_op: | |
1298 | handler = fpemu_dp_madd; | |
1299 | goto dcoptop; | |
1300 | case msub_d_op: | |
1301 | handler = fpemu_dp_msub; | |
1302 | goto dcoptop; | |
1303 | case nmadd_d_op: | |
1304 | handler = fpemu_dp_nmadd; | |
1305 | goto dcoptop; | |
1306 | case nmsub_d_op: | |
1307 | handler = fpemu_dp_nmsub; | |
1308 | goto dcoptop; | |
1309 | ||
1310 | dcoptop: | |
1311 | DPFROMREG(fr, MIPSInst_FR(ir)); | |
1312 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1313 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1314 | fd = (*handler) (fr, fs, ft); | |
1315 | DPTOREG(fd, MIPSInst_FD(ir)); | |
1316 | goto copcsr; | |
1317 | ||
1318 | default: | |
1319 | return SIGILL; | |
1320 | } | |
1321 | break; | |
1322 | } | |
1da177e4 | 1323 | |
51061b88 DZ |
1324 | case 0x3: |
1325 | if (MIPSInst_FUNC(ir) != pfetch_op) | |
1da177e4 | 1326 | return SIGILL; |
51061b88 | 1327 | |
1da177e4 LT |
1328 | /* ignore prefx operation */ |
1329 | break; | |
1330 | ||
1331 | default: | |
1332 | return SIGILL; | |
1333 | } | |
1334 | ||
1335 | return 0; | |
1336 | } | |
1da177e4 LT |
1337 | |
1338 | ||
1339 | ||
1340 | /* | |
1341 | * Emulate a single COP1 arithmetic instruction. | |
1342 | */ | |
eae89076 | 1343 | static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
1da177e4 LT |
1344 | mips_instruction ir) |
1345 | { | |
1346 | int rfmt; /* resulting format */ | |
1347 | unsigned rcsr = 0; /* resulting csr */ | |
3f7cac41 RB |
1348 | unsigned int oldrm; |
1349 | unsigned int cbit; | |
1da177e4 LT |
1350 | unsigned cond; |
1351 | union { | |
2209bcb1 RB |
1352 | union ieee754dp d; |
1353 | union ieee754sp s; | |
1da177e4 | 1354 | int w; |
1da177e4 | 1355 | s64 l; |
1da177e4 | 1356 | } rv; /* resulting value */ |
3f7cac41 | 1357 | u64 bits; |
1da177e4 | 1358 | |
b6ee75ed | 1359 | MIPS_FPU_EMU_INC_STATS(cp1ops); |
1da177e4 | 1360 | switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { |
3f7cac41 | 1361 | case s_fmt: { /* 0 */ |
1da177e4 | 1362 | union { |
2209bcb1 RB |
1363 | union ieee754sp(*b) (union ieee754sp, union ieee754sp); |
1364 | union ieee754sp(*u) (union ieee754sp); | |
1da177e4 | 1365 | } handler; |
3f7cac41 | 1366 | union ieee754sp fs, ft; |
1da177e4 LT |
1367 | |
1368 | switch (MIPSInst_FUNC(ir)) { | |
1369 | /* binary ops */ | |
1370 | case fadd_op: | |
1371 | handler.b = ieee754sp_add; | |
1372 | goto scopbop; | |
1373 | case fsub_op: | |
1374 | handler.b = ieee754sp_sub; | |
1375 | goto scopbop; | |
1376 | case fmul_op: | |
1377 | handler.b = ieee754sp_mul; | |
1378 | goto scopbop; | |
1379 | case fdiv_op: | |
1380 | handler.b = ieee754sp_div; | |
1381 | goto scopbop; | |
1382 | ||
1383 | /* unary ops */ | |
1da177e4 | 1384 | case fsqrt_op: |
08a07904 RB |
1385 | if (!cpu_has_mips_4_5_r) |
1386 | return SIGILL; | |
1387 | ||
1da177e4 LT |
1388 | handler.u = ieee754sp_sqrt; |
1389 | goto scopuop; | |
3f7cac41 | 1390 | |
08a07904 RB |
1391 | /* |
1392 | * Note that on some MIPS IV implementations such as the | |
1393 | * R5000 and R8000 the FSQRT and FRECIP instructions do not | |
1394 | * achieve full IEEE-754 accuracy - however this emulator does. | |
1395 | */ | |
1da177e4 | 1396 | case frsqrt_op: |
08a07904 RB |
1397 | if (!cpu_has_mips_4_5_r2) |
1398 | return SIGILL; | |
1399 | ||
1da177e4 LT |
1400 | handler.u = fpemu_sp_rsqrt; |
1401 | goto scopuop; | |
3f7cac41 | 1402 | |
1da177e4 | 1403 | case frecip_op: |
08a07904 RB |
1404 | if (!cpu_has_mips_4_5_r2) |
1405 | return SIGILL; | |
1406 | ||
1da177e4 LT |
1407 | handler.u = fpemu_sp_recip; |
1408 | goto scopuop; | |
08a07904 | 1409 | |
1da177e4 | 1410 | case fmovc_op: |
08a07904 RB |
1411 | if (!cpu_has_mips_4_5_r) |
1412 | return SIGILL; | |
1413 | ||
1da177e4 LT |
1414 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
1415 | if (((ctx->fcr31 & cond) != 0) != | |
1416 | ((MIPSInst_FT(ir) & 1) != 0)) | |
1417 | return 0; | |
1418 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1419 | break; | |
3f7cac41 | 1420 | |
1da177e4 | 1421 | case fmovz_op: |
08a07904 RB |
1422 | if (!cpu_has_mips_4_5_r) |
1423 | return SIGILL; | |
1424 | ||
1da177e4 LT |
1425 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
1426 | return 0; | |
1427 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1428 | break; | |
3f7cac41 | 1429 | |
1da177e4 | 1430 | case fmovn_op: |
08a07904 RB |
1431 | if (!cpu_has_mips_4_5_r) |
1432 | return SIGILL; | |
1433 | ||
1da177e4 LT |
1434 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
1435 | return 0; | |
1436 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1437 | break; | |
3f7cac41 | 1438 | |
1da177e4 LT |
1439 | case fabs_op: |
1440 | handler.u = ieee754sp_abs; | |
1441 | goto scopuop; | |
3f7cac41 | 1442 | |
1da177e4 LT |
1443 | case fneg_op: |
1444 | handler.u = ieee754sp_neg; | |
1445 | goto scopuop; | |
3f7cac41 | 1446 | |
1da177e4 LT |
1447 | case fmov_op: |
1448 | /* an easy one */ | |
1449 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1450 | goto copcsr; | |
1451 | ||
1452 | /* binary op on handler */ | |
3f7cac41 RB |
1453 | scopbop: |
1454 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1455 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1da177e4 | 1456 | |
3f7cac41 RB |
1457 | rv.s = (*handler.b) (fs, ft); |
1458 | goto copcsr; | |
1459 | scopuop: | |
1460 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1461 | rv.s = (*handler.u) (fs); | |
1462 | goto copcsr; | |
1463 | copcsr: | |
1da177e4 LT |
1464 | if (ieee754_cxtest(IEEE754_INEXACT)) |
1465 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; | |
1466 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) | |
1467 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; | |
1468 | if (ieee754_cxtest(IEEE754_OVERFLOW)) | |
1469 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; | |
1470 | if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) | |
1471 | rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; | |
1472 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) | |
1473 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1474 | break; | |
1475 | ||
1476 | /* unary conv ops */ | |
1477 | case fcvts_op: | |
1478 | return SIGILL; /* not defined */ | |
1da177e4 | 1479 | |
3f7cac41 | 1480 | case fcvtd_op: |
1da177e4 LT |
1481 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1482 | rv.d = ieee754dp_fsp(fs); | |
1483 | rfmt = d_fmt; | |
1484 | goto copcsr; | |
1da177e4 | 1485 | |
3f7cac41 | 1486 | case fcvtw_op: |
1da177e4 LT |
1487 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1488 | rv.w = ieee754sp_tint(fs); | |
1489 | rfmt = w_fmt; | |
1490 | goto copcsr; | |
1da177e4 | 1491 | |
1da177e4 LT |
1492 | case fround_op: |
1493 | case ftrunc_op: | |
1494 | case fceil_op: | |
3f7cac41 | 1495 | case ffloor_op: |
08a07904 RB |
1496 | if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64) |
1497 | return SIGILL; | |
1498 | ||
3f7cac41 | 1499 | oldrm = ieee754_csr.rm; |
1da177e4 | 1500 | SPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1501 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1502 | rv.w = ieee754sp_tint(fs); |
1503 | ieee754_csr.rm = oldrm; | |
1504 | rfmt = w_fmt; | |
1505 | goto copcsr; | |
1da177e4 | 1506 | |
3f7cac41 | 1507 | case fcvtl_op: |
08a07904 RB |
1508 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1509 | return SIGILL; | |
1510 | ||
1da177e4 LT |
1511 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1512 | rv.l = ieee754sp_tlong(fs); | |
1513 | rfmt = l_fmt; | |
1514 | goto copcsr; | |
1da177e4 LT |
1515 | |
1516 | case froundl_op: | |
1517 | case ftruncl_op: | |
1518 | case fceill_op: | |
3f7cac41 | 1519 | case ffloorl_op: |
08a07904 RB |
1520 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1521 | return SIGILL; | |
1522 | ||
3f7cac41 | 1523 | oldrm = ieee754_csr.rm; |
1da177e4 | 1524 | SPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1525 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1526 | rv.l = ieee754sp_tlong(fs); |
1527 | ieee754_csr.rm = oldrm; | |
1528 | rfmt = l_fmt; | |
1529 | goto copcsr; | |
1da177e4 LT |
1530 | |
1531 | default: | |
1532 | if (MIPSInst_FUNC(ir) >= fcmp_op) { | |
1533 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; | |
2209bcb1 | 1534 | union ieee754sp fs, ft; |
1da177e4 LT |
1535 | |
1536 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1537 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1538 | rv.w = ieee754sp_cmp(fs, ft, | |
1539 | cmptab[cmpop & 0x7], cmpop & 0x8); | |
1540 | rfmt = -1; | |
1541 | if ((cmpop & 0x8) && ieee754_cxtest | |
1542 | (IEEE754_INVALID_OPERATION)) | |
1543 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1544 | else | |
1545 | goto copcsr; | |
1546 | ||
3f7cac41 | 1547 | } else |
1da177e4 | 1548 | return SIGILL; |
1da177e4 LT |
1549 | break; |
1550 | } | |
1551 | break; | |
1552 | } | |
1553 | ||
3f7cac41 RB |
1554 | case d_fmt: { |
1555 | union ieee754dp fs, ft; | |
1da177e4 | 1556 | union { |
2209bcb1 RB |
1557 | union ieee754dp(*b) (union ieee754dp, union ieee754dp); |
1558 | union ieee754dp(*u) (union ieee754dp); | |
1da177e4 LT |
1559 | } handler; |
1560 | ||
1561 | switch (MIPSInst_FUNC(ir)) { | |
1562 | /* binary ops */ | |
1563 | case fadd_op: | |
1564 | handler.b = ieee754dp_add; | |
1565 | goto dcopbop; | |
1566 | case fsub_op: | |
1567 | handler.b = ieee754dp_sub; | |
1568 | goto dcopbop; | |
1569 | case fmul_op: | |
1570 | handler.b = ieee754dp_mul; | |
1571 | goto dcopbop; | |
1572 | case fdiv_op: | |
1573 | handler.b = ieee754dp_div; | |
1574 | goto dcopbop; | |
1575 | ||
1576 | /* unary ops */ | |
1da177e4 | 1577 | case fsqrt_op: |
08a07904 RB |
1578 | if (!cpu_has_mips_2_3_4_5_r) |
1579 | return SIGILL; | |
1580 | ||
1da177e4 LT |
1581 | handler.u = ieee754dp_sqrt; |
1582 | goto dcopuop; | |
08a07904 RB |
1583 | /* |
1584 | * Note that on some MIPS IV implementations such as the | |
1585 | * R5000 and R8000 the FSQRT and FRECIP instructions do not | |
1586 | * achieve full IEEE-754 accuracy - however this emulator does. | |
1587 | */ | |
1da177e4 | 1588 | case frsqrt_op: |
08a07904 RB |
1589 | if (!cpu_has_mips_4_5_r2) |
1590 | return SIGILL; | |
1591 | ||
1da177e4 LT |
1592 | handler.u = fpemu_dp_rsqrt; |
1593 | goto dcopuop; | |
1594 | case frecip_op: | |
08a07904 RB |
1595 | if (!cpu_has_mips_4_5_r2) |
1596 | return SIGILL; | |
1597 | ||
1da177e4 LT |
1598 | handler.u = fpemu_dp_recip; |
1599 | goto dcopuop; | |
1da177e4 | 1600 | case fmovc_op: |
08a07904 RB |
1601 | if (!cpu_has_mips_4_5_r) |
1602 | return SIGILL; | |
1603 | ||
1da177e4 LT |
1604 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
1605 | if (((ctx->fcr31 & cond) != 0) != | |
1606 | ((MIPSInst_FT(ir) & 1) != 0)) | |
1607 | return 0; | |
1608 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1609 | break; | |
1610 | case fmovz_op: | |
08a07904 RB |
1611 | if (!cpu_has_mips_4_5_r) |
1612 | return SIGILL; | |
1613 | ||
1da177e4 LT |
1614 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
1615 | return 0; | |
1616 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1617 | break; | |
1618 | case fmovn_op: | |
08a07904 RB |
1619 | if (!cpu_has_mips_4_5_r) |
1620 | return SIGILL; | |
1621 | ||
1da177e4 LT |
1622 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
1623 | return 0; | |
1624 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1625 | break; | |
1da177e4 LT |
1626 | case fabs_op: |
1627 | handler.u = ieee754dp_abs; | |
1628 | goto dcopuop; | |
1629 | ||
1630 | case fneg_op: | |
1631 | handler.u = ieee754dp_neg; | |
1632 | goto dcopuop; | |
1633 | ||
1634 | case fmov_op: | |
1635 | /* an easy one */ | |
1636 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1637 | goto copcsr; | |
1638 | ||
1639 | /* binary op on handler */ | |
3f7cac41 RB |
1640 | dcopbop: |
1641 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1642 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1da177e4 | 1643 | |
3f7cac41 RB |
1644 | rv.d = (*handler.b) (fs, ft); |
1645 | goto copcsr; | |
1646 | dcopuop: | |
1647 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1648 | rv.d = (*handler.u) (fs); | |
1649 | goto copcsr; | |
1da177e4 | 1650 | |
3f7cac41 RB |
1651 | /* |
1652 | * unary conv ops | |
1653 | */ | |
1654 | case fcvts_op: | |
1da177e4 LT |
1655 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1656 | rv.s = ieee754sp_fdp(fs); | |
1657 | rfmt = s_fmt; | |
1658 | goto copcsr; | |
3f7cac41 | 1659 | |
1da177e4 LT |
1660 | case fcvtd_op: |
1661 | return SIGILL; /* not defined */ | |
1662 | ||
3f7cac41 | 1663 | case fcvtw_op: |
1da177e4 LT |
1664 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1665 | rv.w = ieee754dp_tint(fs); /* wrong */ | |
1666 | rfmt = w_fmt; | |
1667 | goto copcsr; | |
1da177e4 | 1668 | |
1da177e4 LT |
1669 | case fround_op: |
1670 | case ftrunc_op: | |
1671 | case fceil_op: | |
3f7cac41 | 1672 | case ffloor_op: |
08a07904 RB |
1673 | if (!cpu_has_mips_2_3_4_5_r) |
1674 | return SIGILL; | |
1675 | ||
3f7cac41 | 1676 | oldrm = ieee754_csr.rm; |
1da177e4 | 1677 | DPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1678 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1679 | rv.w = ieee754dp_tint(fs); |
1680 | ieee754_csr.rm = oldrm; | |
1681 | rfmt = w_fmt; | |
1682 | goto copcsr; | |
1da177e4 | 1683 | |
3f7cac41 | 1684 | case fcvtl_op: |
08a07904 RB |
1685 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1686 | return SIGILL; | |
1687 | ||
1da177e4 LT |
1688 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1689 | rv.l = ieee754dp_tlong(fs); | |
1690 | rfmt = l_fmt; | |
1691 | goto copcsr; | |
1da177e4 LT |
1692 | |
1693 | case froundl_op: | |
1694 | case ftruncl_op: | |
1695 | case fceill_op: | |
3f7cac41 | 1696 | case ffloorl_op: |
08a07904 RB |
1697 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1698 | return SIGILL; | |
1699 | ||
3f7cac41 | 1700 | oldrm = ieee754_csr.rm; |
1da177e4 | 1701 | DPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1702 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1703 | rv.l = ieee754dp_tlong(fs); |
1704 | ieee754_csr.rm = oldrm; | |
1705 | rfmt = l_fmt; | |
1706 | goto copcsr; | |
1da177e4 LT |
1707 | |
1708 | default: | |
1709 | if (MIPSInst_FUNC(ir) >= fcmp_op) { | |
1710 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; | |
2209bcb1 | 1711 | union ieee754dp fs, ft; |
1da177e4 LT |
1712 | |
1713 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1714 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1715 | rv.w = ieee754dp_cmp(fs, ft, | |
1716 | cmptab[cmpop & 0x7], cmpop & 0x8); | |
1717 | rfmt = -1; | |
1718 | if ((cmpop & 0x8) | |
1719 | && | |
1720 | ieee754_cxtest | |
1721 | (IEEE754_INVALID_OPERATION)) | |
1722 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1723 | else | |
1724 | goto copcsr; | |
1725 | ||
1726 | } | |
1727 | else { | |
1728 | return SIGILL; | |
1729 | } | |
1730 | break; | |
1731 | } | |
1732 | break; | |
1da177e4 | 1733 | |
3f7cac41 | 1734 | case w_fmt: |
1da177e4 LT |
1735 | switch (MIPSInst_FUNC(ir)) { |
1736 | case fcvts_op: | |
1737 | /* convert word to single precision real */ | |
1738 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1739 | rv.s = ieee754sp_fint(fs.bits); | |
1740 | rfmt = s_fmt; | |
1741 | goto copcsr; | |
1da177e4 LT |
1742 | case fcvtd_op: |
1743 | /* convert word to double precision real */ | |
1744 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1745 | rv.d = ieee754dp_fint(fs.bits); | |
1746 | rfmt = d_fmt; | |
1747 | goto copcsr; | |
1da177e4 LT |
1748 | default: |
1749 | return SIGILL; | |
1750 | } | |
1751 | break; | |
1752 | } | |
1753 | ||
3f7cac41 | 1754 | case l_fmt: |
08a07904 RB |
1755 | |
1756 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) | |
1757 | return SIGILL; | |
1758 | ||
bbd426f5 PB |
1759 | DIFROMREG(bits, MIPSInst_FS(ir)); |
1760 | ||
1da177e4 LT |
1761 | switch (MIPSInst_FUNC(ir)) { |
1762 | case fcvts_op: | |
1763 | /* convert long to single precision real */ | |
bbd426f5 | 1764 | rv.s = ieee754sp_flong(bits); |
1da177e4 LT |
1765 | rfmt = s_fmt; |
1766 | goto copcsr; | |
1767 | case fcvtd_op: | |
1768 | /* convert long to double precision real */ | |
bbd426f5 | 1769 | rv.d = ieee754dp_flong(bits); |
1da177e4 LT |
1770 | rfmt = d_fmt; |
1771 | goto copcsr; | |
1772 | default: | |
1773 | return SIGILL; | |
1774 | } | |
1775 | break; | |
1da177e4 LT |
1776 | |
1777 | default: | |
1778 | return SIGILL; | |
1779 | } | |
1780 | ||
1781 | /* | |
1782 | * Update the fpu CSR register for this operation. | |
1783 | * If an exception is required, generate a tidy SIGFPE exception, | |
1784 | * without updating the result register. | |
1785 | * Note: cause exception bits do not accumulate, they are rewritten | |
1786 | * for each op; only the flag/sticky bits accumulate. | |
1787 | */ | |
1788 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; | |
1789 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { | |
3f7cac41 | 1790 | /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ |
1da177e4 LT |
1791 | return SIGFPE; |
1792 | } | |
1793 | ||
1794 | /* | |
1795 | * Now we can safely write the result back to the register file. | |
1796 | */ | |
1797 | switch (rfmt) { | |
08a07904 RB |
1798 | case -1: |
1799 | ||
1800 | if (cpu_has_mips_4_5_r) | |
1801 | cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
1802 | else | |
1803 | cbit = FPU_CSR_COND; | |
1da177e4 | 1804 | if (rv.w) |
08a07904 | 1805 | ctx->fcr31 |= cbit; |
1da177e4 | 1806 | else |
08a07904 | 1807 | ctx->fcr31 &= ~cbit; |
1da177e4 | 1808 | break; |
08a07904 | 1809 | |
1da177e4 LT |
1810 | case d_fmt: |
1811 | DPTOREG(rv.d, MIPSInst_FD(ir)); | |
1812 | break; | |
1da177e4 LT |
1813 | case s_fmt: |
1814 | SPTOREG(rv.s, MIPSInst_FD(ir)); | |
1815 | break; | |
1816 | case w_fmt: | |
1817 | SITOREG(rv.w, MIPSInst_FD(ir)); | |
1818 | break; | |
1da177e4 | 1819 | case l_fmt: |
08a07904 RB |
1820 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1821 | return SIGILL; | |
1822 | ||
1da177e4 LT |
1823 | DITOREG(rv.l, MIPSInst_FD(ir)); |
1824 | break; | |
1da177e4 LT |
1825 | default: |
1826 | return SIGILL; | |
1827 | } | |
1828 | ||
1829 | return 0; | |
1830 | } | |
1831 | ||
e04582b7 | 1832 | int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
515b029d | 1833 | int has_fpu, void *__user *fault_addr) |
1da177e4 | 1834 | { |
333d1f67 | 1835 | unsigned long oldepc, prevepc; |
102cedc3 LY |
1836 | struct mm_decoded_insn dec_insn; |
1837 | u16 instr[4]; | |
1838 | u16 *instr_ptr; | |
1da177e4 LT |
1839 | int sig = 0; |
1840 | ||
1841 | oldepc = xcp->cp0_epc; | |
1842 | do { | |
1843 | prevepc = xcp->cp0_epc; | |
1844 | ||
102cedc3 LY |
1845 | if (get_isa16_mode(prevepc) && cpu_has_mmips) { |
1846 | /* | |
1847 | * Get next 2 microMIPS instructions and convert them | |
1848 | * into 32-bit instructions. | |
1849 | */ | |
1850 | if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || | |
1851 | (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || | |
1852 | (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || | |
1853 | (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { | |
1854 | MIPS_FPU_EMU_INC_STATS(errors); | |
1855 | return SIGBUS; | |
1856 | } | |
1857 | instr_ptr = instr; | |
1858 | ||
1859 | /* Get first instruction. */ | |
1860 | if (mm_insn_16bit(*instr_ptr)) { | |
1861 | /* Duplicate the half-word. */ | |
1862 | dec_insn.insn = (*instr_ptr << 16) | | |
1863 | (*instr_ptr); | |
1864 | /* 16-bit instruction. */ | |
1865 | dec_insn.pc_inc = 2; | |
1866 | instr_ptr += 1; | |
1867 | } else { | |
1868 | dec_insn.insn = (*instr_ptr << 16) | | |
1869 | *(instr_ptr+1); | |
1870 | /* 32-bit instruction. */ | |
1871 | dec_insn.pc_inc = 4; | |
1872 | instr_ptr += 2; | |
1873 | } | |
1874 | /* Get second instruction. */ | |
1875 | if (mm_insn_16bit(*instr_ptr)) { | |
1876 | /* Duplicate the half-word. */ | |
1877 | dec_insn.next_insn = (*instr_ptr << 16) | | |
1878 | (*instr_ptr); | |
1879 | /* 16-bit instruction. */ | |
1880 | dec_insn.next_pc_inc = 2; | |
1881 | } else { | |
1882 | dec_insn.next_insn = (*instr_ptr << 16) | | |
1883 | *(instr_ptr+1); | |
1884 | /* 32-bit instruction. */ | |
1885 | dec_insn.next_pc_inc = 4; | |
1886 | } | |
1887 | dec_insn.micro_mips_mode = 1; | |
1888 | } else { | |
1889 | if ((get_user(dec_insn.insn, | |
1890 | (mips_instruction __user *) xcp->cp0_epc)) || | |
1891 | (get_user(dec_insn.next_insn, | |
1892 | (mips_instruction __user *)(xcp->cp0_epc+4)))) { | |
1893 | MIPS_FPU_EMU_INC_STATS(errors); | |
1894 | return SIGBUS; | |
1895 | } | |
1896 | dec_insn.pc_inc = 4; | |
1897 | dec_insn.next_pc_inc = 4; | |
1898 | dec_insn.micro_mips_mode = 0; | |
515b029d | 1899 | } |
102cedc3 LY |
1900 | |
1901 | if ((dec_insn.insn == 0) || | |
1902 | ((dec_insn.pc_inc == 2) && | |
1903 | ((dec_insn.insn & 0xffff) == MM_NOP16))) | |
1904 | xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ | |
1da177e4 | 1905 | else { |
cd21dfcf RB |
1906 | /* |
1907 | * The 'ieee754_csr' is an alias of | |
70342287 RB |
1908 | * ctx->fcr31. No need to copy ctx->fcr31 to |
1909 | * ieee754_csr. But ieee754_csr.rm is ieee | |
cd21dfcf RB |
1910 | * library modes. (not mips rounding mode) |
1911 | */ | |
102cedc3 | 1912 | sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); |
1da177e4 LT |
1913 | } |
1914 | ||
e04582b7 | 1915 | if (has_fpu) |
1da177e4 LT |
1916 | break; |
1917 | if (sig) | |
1918 | break; | |
1919 | ||
1920 | cond_resched(); | |
1921 | } while (xcp->cp0_epc > prevepc); | |
1922 | ||
1923 | /* SIGILL indicates a non-fpu instruction */ | |
1924 | if (sig == SIGILL && xcp->cp0_epc != oldepc) | |
3f7cac41 | 1925 | /* but if EPC has advanced, then ignore it */ |
1da177e4 LT |
1926 | sig = 0; |
1927 | ||
1928 | return sig; | |
1929 | } |