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Commit | Line | Data |
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1da177e4 | 1 | /* |
3f7cac41 | 2 | * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator |
1da177e4 LT |
3 | * |
4 | * MIPS floating point support | |
5 | * Copyright (C) 1994-2000 Algorithmics Ltd. | |
1da177e4 LT |
6 | * |
7 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
8 | * Copyright (C) 2000 MIPS Technologies, Inc. | |
9 | * | |
10 | * This program is free software; you can distribute it and/or modify it | |
11 | * under the terms of the GNU General Public License (Version 2) as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | * for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, write to the Free Software Foundation, Inc., | |
3f7cac41 | 21 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
1da177e4 LT |
22 | * |
23 | * A complete emulator for MIPS coprocessor 1 instructions. This is | |
24 | * required for #float(switch) or #float(trap), where it catches all | |
25 | * COP1 instructions via the "CoProcessor Unusable" exception. | |
26 | * | |
27 | * More surprisingly it is also required for #float(ieee), to help out | |
3f7cac41 | 28 | * the hardware FPU at the boundaries of the IEEE-754 representation |
1da177e4 LT |
29 | * (denormalised values, infinities, underflow, etc). It is made |
30 | * quite nasty because emulation of some non-COP1 instructions is | |
31 | * required, e.g. in branch delay slots. | |
32 | * | |
3f7cac41 | 33 | * Note if you know that you won't have an FPU, then you'll get much |
1da177e4 LT |
34 | * better performance by compiling with -msoft-float! |
35 | */ | |
36 | #include <linux/sched.h> | |
83fd38ca | 37 | #include <linux/debugfs.h> |
08a07904 | 38 | #include <linux/kconfig.h> |
85c51c51 | 39 | #include <linux/percpu-defs.h> |
7f788d2d | 40 | #include <linux/perf_event.h> |
1da177e4 | 41 | |
cd8ee345 | 42 | #include <asm/branch.h> |
1da177e4 | 43 | #include <asm/inst.h> |
1da177e4 LT |
44 | #include <asm/ptrace.h> |
45 | #include <asm/signal.h> | |
cd8ee345 RB |
46 | #include <asm/uaccess.h> |
47 | ||
48 | #include <asm/processor.h> | |
1da177e4 | 49 | #include <asm/fpu_emulator.h> |
102cedc3 | 50 | #include <asm/fpu.h> |
1da177e4 LT |
51 | |
52 | #include "ieee754.h" | |
1da177e4 | 53 | |
1da177e4 LT |
54 | /* Function which emulates a floating point instruction. */ |
55 | ||
eae89076 | 56 | static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, |
1da177e4 LT |
57 | mips_instruction); |
58 | ||
1da177e4 | 59 | static int fpux_emu(struct pt_regs *, |
515b029d | 60 | struct mips_fpu_struct *, mips_instruction, void *__user *); |
1da177e4 | 61 | |
1da177e4 LT |
62 | /* Control registers */ |
63 | ||
64 | #define FPCREG_RID 0 /* $0 = revision id */ | |
65 | #define FPCREG_CSR 31 /* $31 = csr */ | |
66 | ||
95e8f634 SM |
67 | /* Determine rounding mode from the RM bits of the FCSR */ |
68 | #define modeindex(v) ((v) & FPU_CSR_RM) | |
69 | ||
1da177e4 LT |
70 | /* convert condition code register number to csr bit */ |
71 | static const unsigned int fpucondbit[8] = { | |
72 | FPU_CSR_COND0, | |
73 | FPU_CSR_COND1, | |
74 | FPU_CSR_COND2, | |
75 | FPU_CSR_COND3, | |
76 | FPU_CSR_COND4, | |
77 | FPU_CSR_COND5, | |
78 | FPU_CSR_COND6, | |
79 | FPU_CSR_COND7 | |
80 | }; | |
1da177e4 | 81 | |
102cedc3 LY |
82 | /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ |
83 | static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; | |
84 | static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; | |
85 | static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; | |
86 | static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; | |
87 | ||
88 | /* | |
89 | * This functions translates a 32-bit microMIPS instruction | |
90 | * into a 32-bit MIPS32 instruction. Returns 0 on success | |
91 | * and SIGILL otherwise. | |
92 | */ | |
93 | static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) | |
94 | { | |
95 | union mips_instruction insn = *insn_ptr; | |
96 | union mips_instruction mips32_insn = insn; | |
97 | int func, fmt, op; | |
98 | ||
99 | switch (insn.mm_i_format.opcode) { | |
100 | case mm_ldc132_op: | |
101 | mips32_insn.mm_i_format.opcode = ldc1_op; | |
102 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
103 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
104 | break; | |
105 | case mm_lwc132_op: | |
106 | mips32_insn.mm_i_format.opcode = lwc1_op; | |
107 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
108 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
109 | break; | |
110 | case mm_sdc132_op: | |
111 | mips32_insn.mm_i_format.opcode = sdc1_op; | |
112 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
113 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
114 | break; | |
115 | case mm_swc132_op: | |
116 | mips32_insn.mm_i_format.opcode = swc1_op; | |
117 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
118 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
119 | break; | |
120 | case mm_pool32i_op: | |
121 | /* NOTE: offset is << by 1 if in microMIPS mode. */ | |
122 | if ((insn.mm_i_format.rt == mm_bc1f_op) || | |
123 | (insn.mm_i_format.rt == mm_bc1t_op)) { | |
124 | mips32_insn.fb_format.opcode = cop1_op; | |
125 | mips32_insn.fb_format.bc = bc_op; | |
126 | mips32_insn.fb_format.flag = | |
127 | (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; | |
128 | } else | |
129 | return SIGILL; | |
130 | break; | |
131 | case mm_pool32f_op: | |
132 | switch (insn.mm_fp0_format.func) { | |
133 | case mm_32f_01_op: | |
134 | case mm_32f_11_op: | |
135 | case mm_32f_02_op: | |
136 | case mm_32f_12_op: | |
137 | case mm_32f_41_op: | |
138 | case mm_32f_51_op: | |
139 | case mm_32f_42_op: | |
140 | case mm_32f_52_op: | |
141 | op = insn.mm_fp0_format.func; | |
142 | if (op == mm_32f_01_op) | |
143 | func = madd_s_op; | |
144 | else if (op == mm_32f_11_op) | |
145 | func = madd_d_op; | |
146 | else if (op == mm_32f_02_op) | |
147 | func = nmadd_s_op; | |
148 | else if (op == mm_32f_12_op) | |
149 | func = nmadd_d_op; | |
150 | else if (op == mm_32f_41_op) | |
151 | func = msub_s_op; | |
152 | else if (op == mm_32f_51_op) | |
153 | func = msub_d_op; | |
154 | else if (op == mm_32f_42_op) | |
155 | func = nmsub_s_op; | |
156 | else | |
157 | func = nmsub_d_op; | |
158 | mips32_insn.fp6_format.opcode = cop1x_op; | |
159 | mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; | |
160 | mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; | |
161 | mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; | |
162 | mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; | |
163 | mips32_insn.fp6_format.func = func; | |
164 | break; | |
165 | case mm_32f_10_op: | |
166 | func = -1; /* Invalid */ | |
167 | op = insn.mm_fp5_format.op & 0x7; | |
168 | if (op == mm_ldxc1_op) | |
169 | func = ldxc1_op; | |
170 | else if (op == mm_sdxc1_op) | |
171 | func = sdxc1_op; | |
172 | else if (op == mm_lwxc1_op) | |
173 | func = lwxc1_op; | |
174 | else if (op == mm_swxc1_op) | |
175 | func = swxc1_op; | |
176 | ||
177 | if (func != -1) { | |
178 | mips32_insn.r_format.opcode = cop1x_op; | |
179 | mips32_insn.r_format.rs = | |
180 | insn.mm_fp5_format.base; | |
181 | mips32_insn.r_format.rt = | |
182 | insn.mm_fp5_format.index; | |
183 | mips32_insn.r_format.rd = 0; | |
184 | mips32_insn.r_format.re = insn.mm_fp5_format.fd; | |
185 | mips32_insn.r_format.func = func; | |
186 | } else | |
187 | return SIGILL; | |
188 | break; | |
189 | case mm_32f_40_op: | |
190 | op = -1; /* Invalid */ | |
191 | if (insn.mm_fp2_format.op == mm_fmovt_op) | |
192 | op = 1; | |
193 | else if (insn.mm_fp2_format.op == mm_fmovf_op) | |
194 | op = 0; | |
195 | if (op != -1) { | |
196 | mips32_insn.fp0_format.opcode = cop1_op; | |
197 | mips32_insn.fp0_format.fmt = | |
198 | sdps_format[insn.mm_fp2_format.fmt]; | |
199 | mips32_insn.fp0_format.ft = | |
200 | (insn.mm_fp2_format.cc<<2) + op; | |
201 | mips32_insn.fp0_format.fs = | |
202 | insn.mm_fp2_format.fs; | |
203 | mips32_insn.fp0_format.fd = | |
204 | insn.mm_fp2_format.fd; | |
205 | mips32_insn.fp0_format.func = fmovc_op; | |
206 | } else | |
207 | return SIGILL; | |
208 | break; | |
209 | case mm_32f_60_op: | |
210 | func = -1; /* Invalid */ | |
211 | if (insn.mm_fp0_format.op == mm_fadd_op) | |
212 | func = fadd_op; | |
213 | else if (insn.mm_fp0_format.op == mm_fsub_op) | |
214 | func = fsub_op; | |
215 | else if (insn.mm_fp0_format.op == mm_fmul_op) | |
216 | func = fmul_op; | |
217 | else if (insn.mm_fp0_format.op == mm_fdiv_op) | |
218 | func = fdiv_op; | |
219 | if (func != -1) { | |
220 | mips32_insn.fp0_format.opcode = cop1_op; | |
221 | mips32_insn.fp0_format.fmt = | |
222 | sdps_format[insn.mm_fp0_format.fmt]; | |
223 | mips32_insn.fp0_format.ft = | |
224 | insn.mm_fp0_format.ft; | |
225 | mips32_insn.fp0_format.fs = | |
226 | insn.mm_fp0_format.fs; | |
227 | mips32_insn.fp0_format.fd = | |
228 | insn.mm_fp0_format.fd; | |
229 | mips32_insn.fp0_format.func = func; | |
230 | } else | |
231 | return SIGILL; | |
232 | break; | |
233 | case mm_32f_70_op: | |
234 | func = -1; /* Invalid */ | |
235 | if (insn.mm_fp0_format.op == mm_fmovn_op) | |
236 | func = fmovn_op; | |
237 | else if (insn.mm_fp0_format.op == mm_fmovz_op) | |
238 | func = fmovz_op; | |
239 | if (func != -1) { | |
240 | mips32_insn.fp0_format.opcode = cop1_op; | |
241 | mips32_insn.fp0_format.fmt = | |
242 | sdps_format[insn.mm_fp0_format.fmt]; | |
243 | mips32_insn.fp0_format.ft = | |
244 | insn.mm_fp0_format.ft; | |
245 | mips32_insn.fp0_format.fs = | |
246 | insn.mm_fp0_format.fs; | |
247 | mips32_insn.fp0_format.fd = | |
248 | insn.mm_fp0_format.fd; | |
249 | mips32_insn.fp0_format.func = func; | |
250 | } else | |
251 | return SIGILL; | |
252 | break; | |
253 | case mm_32f_73_op: /* POOL32FXF */ | |
254 | switch (insn.mm_fp1_format.op) { | |
255 | case mm_movf0_op: | |
256 | case mm_movf1_op: | |
257 | case mm_movt0_op: | |
258 | case mm_movt1_op: | |
259 | if ((insn.mm_fp1_format.op & 0x7f) == | |
260 | mm_movf0_op) | |
261 | op = 0; | |
262 | else | |
263 | op = 1; | |
264 | mips32_insn.r_format.opcode = spec_op; | |
265 | mips32_insn.r_format.rs = insn.mm_fp4_format.fs; | |
266 | mips32_insn.r_format.rt = | |
267 | (insn.mm_fp4_format.cc << 2) + op; | |
268 | mips32_insn.r_format.rd = insn.mm_fp4_format.rt; | |
269 | mips32_insn.r_format.re = 0; | |
270 | mips32_insn.r_format.func = movc_op; | |
271 | break; | |
272 | case mm_fcvtd0_op: | |
273 | case mm_fcvtd1_op: | |
274 | case mm_fcvts0_op: | |
275 | case mm_fcvts1_op: | |
276 | if ((insn.mm_fp1_format.op & 0x7f) == | |
277 | mm_fcvtd0_op) { | |
278 | func = fcvtd_op; | |
279 | fmt = swl_format[insn.mm_fp3_format.fmt]; | |
280 | } else { | |
281 | func = fcvts_op; | |
282 | fmt = dwl_format[insn.mm_fp3_format.fmt]; | |
283 | } | |
284 | mips32_insn.fp0_format.opcode = cop1_op; | |
285 | mips32_insn.fp0_format.fmt = fmt; | |
286 | mips32_insn.fp0_format.ft = 0; | |
287 | mips32_insn.fp0_format.fs = | |
288 | insn.mm_fp3_format.fs; | |
289 | mips32_insn.fp0_format.fd = | |
290 | insn.mm_fp3_format.rt; | |
291 | mips32_insn.fp0_format.func = func; | |
292 | break; | |
293 | case mm_fmov0_op: | |
294 | case mm_fmov1_op: | |
295 | case mm_fabs0_op: | |
296 | case mm_fabs1_op: | |
297 | case mm_fneg0_op: | |
298 | case mm_fneg1_op: | |
299 | if ((insn.mm_fp1_format.op & 0x7f) == | |
300 | mm_fmov0_op) | |
301 | func = fmov_op; | |
302 | else if ((insn.mm_fp1_format.op & 0x7f) == | |
303 | mm_fabs0_op) | |
304 | func = fabs_op; | |
305 | else | |
306 | func = fneg_op; | |
307 | mips32_insn.fp0_format.opcode = cop1_op; | |
308 | mips32_insn.fp0_format.fmt = | |
309 | sdps_format[insn.mm_fp3_format.fmt]; | |
310 | mips32_insn.fp0_format.ft = 0; | |
311 | mips32_insn.fp0_format.fs = | |
312 | insn.mm_fp3_format.fs; | |
313 | mips32_insn.fp0_format.fd = | |
314 | insn.mm_fp3_format.rt; | |
315 | mips32_insn.fp0_format.func = func; | |
316 | break; | |
317 | case mm_ffloorl_op: | |
318 | case mm_ffloorw_op: | |
319 | case mm_fceill_op: | |
320 | case mm_fceilw_op: | |
321 | case mm_ftruncl_op: | |
322 | case mm_ftruncw_op: | |
323 | case mm_froundl_op: | |
324 | case mm_froundw_op: | |
325 | case mm_fcvtl_op: | |
326 | case mm_fcvtw_op: | |
327 | if (insn.mm_fp1_format.op == mm_ffloorl_op) | |
328 | func = ffloorl_op; | |
329 | else if (insn.mm_fp1_format.op == mm_ffloorw_op) | |
330 | func = ffloor_op; | |
331 | else if (insn.mm_fp1_format.op == mm_fceill_op) | |
332 | func = fceill_op; | |
333 | else if (insn.mm_fp1_format.op == mm_fceilw_op) | |
334 | func = fceil_op; | |
335 | else if (insn.mm_fp1_format.op == mm_ftruncl_op) | |
336 | func = ftruncl_op; | |
337 | else if (insn.mm_fp1_format.op == mm_ftruncw_op) | |
338 | func = ftrunc_op; | |
339 | else if (insn.mm_fp1_format.op == mm_froundl_op) | |
340 | func = froundl_op; | |
341 | else if (insn.mm_fp1_format.op == mm_froundw_op) | |
342 | func = fround_op; | |
343 | else if (insn.mm_fp1_format.op == mm_fcvtl_op) | |
344 | func = fcvtl_op; | |
345 | else | |
346 | func = fcvtw_op; | |
347 | mips32_insn.fp0_format.opcode = cop1_op; | |
348 | mips32_insn.fp0_format.fmt = | |
349 | sd_format[insn.mm_fp1_format.fmt]; | |
350 | mips32_insn.fp0_format.ft = 0; | |
351 | mips32_insn.fp0_format.fs = | |
352 | insn.mm_fp1_format.fs; | |
353 | mips32_insn.fp0_format.fd = | |
354 | insn.mm_fp1_format.rt; | |
355 | mips32_insn.fp0_format.func = func; | |
356 | break; | |
357 | case mm_frsqrt_op: | |
358 | case mm_fsqrt_op: | |
359 | case mm_frecip_op: | |
360 | if (insn.mm_fp1_format.op == mm_frsqrt_op) | |
361 | func = frsqrt_op; | |
362 | else if (insn.mm_fp1_format.op == mm_fsqrt_op) | |
363 | func = fsqrt_op; | |
364 | else | |
365 | func = frecip_op; | |
366 | mips32_insn.fp0_format.opcode = cop1_op; | |
367 | mips32_insn.fp0_format.fmt = | |
368 | sdps_format[insn.mm_fp1_format.fmt]; | |
369 | mips32_insn.fp0_format.ft = 0; | |
370 | mips32_insn.fp0_format.fs = | |
371 | insn.mm_fp1_format.fs; | |
372 | mips32_insn.fp0_format.fd = | |
373 | insn.mm_fp1_format.rt; | |
374 | mips32_insn.fp0_format.func = func; | |
375 | break; | |
376 | case mm_mfc1_op: | |
377 | case mm_mtc1_op: | |
378 | case mm_cfc1_op: | |
379 | case mm_ctc1_op: | |
9355e59c SH |
380 | case mm_mfhc1_op: |
381 | case mm_mthc1_op: | |
102cedc3 LY |
382 | if (insn.mm_fp1_format.op == mm_mfc1_op) |
383 | op = mfc_op; | |
384 | else if (insn.mm_fp1_format.op == mm_mtc1_op) | |
385 | op = mtc_op; | |
386 | else if (insn.mm_fp1_format.op == mm_cfc1_op) | |
387 | op = cfc_op; | |
9355e59c | 388 | else if (insn.mm_fp1_format.op == mm_ctc1_op) |
102cedc3 | 389 | op = ctc_op; |
9355e59c SH |
390 | else if (insn.mm_fp1_format.op == mm_mfhc1_op) |
391 | op = mfhc_op; | |
392 | else | |
393 | op = mthc_op; | |
102cedc3 LY |
394 | mips32_insn.fp1_format.opcode = cop1_op; |
395 | mips32_insn.fp1_format.op = op; | |
396 | mips32_insn.fp1_format.rt = | |
397 | insn.mm_fp1_format.rt; | |
398 | mips32_insn.fp1_format.fs = | |
399 | insn.mm_fp1_format.fs; | |
400 | mips32_insn.fp1_format.fd = 0; | |
401 | mips32_insn.fp1_format.func = 0; | |
402 | break; | |
403 | default: | |
404 | return SIGILL; | |
102cedc3 LY |
405 | } |
406 | break; | |
407 | case mm_32f_74_op: /* c.cond.fmt */ | |
408 | mips32_insn.fp0_format.opcode = cop1_op; | |
409 | mips32_insn.fp0_format.fmt = | |
410 | sdps_format[insn.mm_fp4_format.fmt]; | |
411 | mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; | |
412 | mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; | |
413 | mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; | |
414 | mips32_insn.fp0_format.func = | |
415 | insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; | |
416 | break; | |
417 | default: | |
418 | return SIGILL; | |
102cedc3 LY |
419 | } |
420 | break; | |
421 | default: | |
422 | return SIGILL; | |
102cedc3 LY |
423 | } |
424 | ||
425 | *insn_ptr = mips32_insn; | |
426 | return 0; | |
427 | } | |
428 | ||
1da177e4 LT |
429 | /* |
430 | * Redundant with logic already in kernel/branch.c, | |
431 | * embedded in compute_return_epc. At some point, | |
432 | * a single subroutine should be used across both | |
433 | * modules. | |
434 | */ | |
102cedc3 LY |
435 | static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, |
436 | unsigned long *contpc) | |
1da177e4 | 437 | { |
102cedc3 LY |
438 | union mips_instruction insn = (union mips_instruction)dec_insn.insn; |
439 | unsigned int fcr31; | |
440 | unsigned int bit = 0; | |
441 | ||
442 | switch (insn.i_format.opcode) { | |
1da177e4 | 443 | case spec_op: |
102cedc3 | 444 | switch (insn.r_format.func) { |
1da177e4 | 445 | case jalr_op: |
102cedc3 LY |
446 | regs->regs[insn.r_format.rd] = |
447 | regs->cp0_epc + dec_insn.pc_inc + | |
448 | dec_insn.next_pc_inc; | |
449 | /* Fall through */ | |
1da177e4 | 450 | case jr_op: |
5f9f41c4 MC |
451 | /* For R6, JR already emulated in jalr_op */ |
452 | if (NO_R6EMU && insn.r_format.opcode == jr_op) | |
453 | break; | |
102cedc3 | 454 | *contpc = regs->regs[insn.r_format.rs]; |
1da177e4 LT |
455 | return 1; |
456 | } | |
457 | break; | |
1da177e4 | 458 | case bcond_op: |
102cedc3 LY |
459 | switch (insn.i_format.rt) { |
460 | case bltzal_op: | |
461 | case bltzall_op: | |
319824ea MC |
462 | if (NO_R6EMU && (insn.i_format.rs || |
463 | insn.i_format.rt == bltzall_op)) | |
464 | break; | |
465 | ||
102cedc3 LY |
466 | regs->regs[31] = regs->cp0_epc + |
467 | dec_insn.pc_inc + | |
468 | dec_insn.next_pc_inc; | |
469 | /* Fall through */ | |
1da177e4 | 470 | case bltzl_op: |
319824ea MC |
471 | if (NO_R6EMU) |
472 | break; | |
473 | case bltz_op: | |
102cedc3 LY |
474 | if ((long)regs->regs[insn.i_format.rs] < 0) |
475 | *contpc = regs->cp0_epc + | |
476 | dec_insn.pc_inc + | |
477 | (insn.i_format.simmediate << 2); | |
478 | else | |
479 | *contpc = regs->cp0_epc + | |
480 | dec_insn.pc_inc + | |
481 | dec_insn.next_pc_inc; | |
482 | return 1; | |
1da177e4 | 483 | case bgezal_op: |
1da177e4 | 484 | case bgezall_op: |
319824ea MC |
485 | if (NO_R6EMU && (insn.i_format.rs || |
486 | insn.i_format.rt == bgezall_op)) | |
487 | break; | |
488 | ||
102cedc3 LY |
489 | regs->regs[31] = regs->cp0_epc + |
490 | dec_insn.pc_inc + | |
491 | dec_insn.next_pc_inc; | |
492 | /* Fall through */ | |
102cedc3 | 493 | case bgezl_op: |
319824ea MC |
494 | if (NO_R6EMU) |
495 | break; | |
496 | case bgez_op: | |
102cedc3 LY |
497 | if ((long)regs->regs[insn.i_format.rs] >= 0) |
498 | *contpc = regs->cp0_epc + | |
499 | dec_insn.pc_inc + | |
500 | (insn.i_format.simmediate << 2); | |
501 | else | |
502 | *contpc = regs->cp0_epc + | |
503 | dec_insn.pc_inc + | |
504 | dec_insn.next_pc_inc; | |
1da177e4 LT |
505 | return 1; |
506 | } | |
507 | break; | |
1da177e4 | 508 | case jalx_op: |
102cedc3 LY |
509 | set_isa16_mode(bit); |
510 | case jal_op: | |
511 | regs->regs[31] = regs->cp0_epc + | |
512 | dec_insn.pc_inc + | |
513 | dec_insn.next_pc_inc; | |
514 | /* Fall through */ | |
515 | case j_op: | |
516 | *contpc = regs->cp0_epc + dec_insn.pc_inc; | |
517 | *contpc >>= 28; | |
518 | *contpc <<= 28; | |
519 | *contpc |= (insn.j_format.target << 2); | |
520 | /* Set microMIPS mode bit: XOR for jalx. */ | |
521 | *contpc ^= bit; | |
522 | return 1; | |
1da177e4 | 523 | case beql_op: |
319824ea MC |
524 | if (NO_R6EMU) |
525 | break; | |
526 | case beq_op: | |
102cedc3 LY |
527 | if (regs->regs[insn.i_format.rs] == |
528 | regs->regs[insn.i_format.rt]) | |
529 | *contpc = regs->cp0_epc + | |
530 | dec_insn.pc_inc + | |
531 | (insn.i_format.simmediate << 2); | |
532 | else | |
533 | *contpc = regs->cp0_epc + | |
534 | dec_insn.pc_inc + | |
535 | dec_insn.next_pc_inc; | |
536 | return 1; | |
1da177e4 | 537 | case bnel_op: |
319824ea MC |
538 | if (NO_R6EMU) |
539 | break; | |
540 | case bne_op: | |
102cedc3 LY |
541 | if (regs->regs[insn.i_format.rs] != |
542 | regs->regs[insn.i_format.rt]) | |
543 | *contpc = regs->cp0_epc + | |
544 | dec_insn.pc_inc + | |
545 | (insn.i_format.simmediate << 2); | |
546 | else | |
547 | *contpc = regs->cp0_epc + | |
548 | dec_insn.pc_inc + | |
549 | dec_insn.next_pc_inc; | |
550 | return 1; | |
1da177e4 | 551 | case blezl_op: |
319824ea MC |
552 | if (NO_R6EMU) |
553 | break; | |
554 | case blez_op: | |
a8ff66f5 MC |
555 | |
556 | /* | |
557 | * Compact branches for R6 for the | |
558 | * blez and blezl opcodes. | |
559 | * BLEZ | rs = 0 | rt != 0 == BLEZALC | |
560 | * BLEZ | rs = rt != 0 == BGEZALC | |
561 | * BLEZ | rs != 0 | rt != 0 == BGEUC | |
562 | * BLEZL | rs = 0 | rt != 0 == BLEZC | |
563 | * BLEZL | rs = rt != 0 == BGEZC | |
564 | * BLEZL | rs != 0 | rt != 0 == BGEC | |
565 | * | |
566 | * For real BLEZ{,L}, rt is always 0. | |
567 | */ | |
568 | if (cpu_has_mips_r6 && insn.i_format.rt) { | |
569 | if ((insn.i_format.opcode == blez_op) && | |
570 | ((!insn.i_format.rs && insn.i_format.rt) || | |
571 | (insn.i_format.rs == insn.i_format.rt))) | |
572 | regs->regs[31] = regs->cp0_epc + | |
573 | dec_insn.pc_inc; | |
574 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
575 | dec_insn.next_pc_inc; | |
576 | ||
577 | return 1; | |
578 | } | |
102cedc3 LY |
579 | if ((long)regs->regs[insn.i_format.rs] <= 0) |
580 | *contpc = regs->cp0_epc + | |
581 | dec_insn.pc_inc + | |
582 | (insn.i_format.simmediate << 2); | |
583 | else | |
584 | *contpc = regs->cp0_epc + | |
585 | dec_insn.pc_inc + | |
586 | dec_insn.next_pc_inc; | |
587 | return 1; | |
1da177e4 | 588 | case bgtzl_op: |
319824ea MC |
589 | if (NO_R6EMU) |
590 | break; | |
591 | case bgtz_op: | |
f1b44067 MC |
592 | /* |
593 | * Compact branches for R6 for the | |
594 | * bgtz and bgtzl opcodes. | |
595 | * BGTZ | rs = 0 | rt != 0 == BGTZALC | |
596 | * BGTZ | rs = rt != 0 == BLTZALC | |
597 | * BGTZ | rs != 0 | rt != 0 == BLTUC | |
598 | * BGTZL | rs = 0 | rt != 0 == BGTZC | |
599 | * BGTZL | rs = rt != 0 == BLTZC | |
600 | * BGTZL | rs != 0 | rt != 0 == BLTC | |
601 | * | |
602 | * *ZALC varint for BGTZ &&& rt != 0 | |
603 | * For real GTZ{,L}, rt is always 0. | |
604 | */ | |
605 | if (cpu_has_mips_r6 && insn.i_format.rt) { | |
606 | if ((insn.i_format.opcode == blez_op) && | |
607 | ((!insn.i_format.rs && insn.i_format.rt) || | |
608 | (insn.i_format.rs == insn.i_format.rt))) | |
609 | regs->regs[31] = regs->cp0_epc + | |
610 | dec_insn.pc_inc; | |
611 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
612 | dec_insn.next_pc_inc; | |
613 | ||
614 | return 1; | |
615 | } | |
616 | ||
102cedc3 LY |
617 | if ((long)regs->regs[insn.i_format.rs] > 0) |
618 | *contpc = regs->cp0_epc + | |
619 | dec_insn.pc_inc + | |
620 | (insn.i_format.simmediate << 2); | |
621 | else | |
622 | *contpc = regs->cp0_epc + | |
623 | dec_insn.pc_inc + | |
624 | dec_insn.next_pc_inc; | |
1da177e4 | 625 | return 1; |
c26d4219 DD |
626 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
627 | case lwc2_op: /* This is bbit0 on Octeon */ | |
628 | if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) | |
629 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
630 | else | |
631 | *contpc = regs->cp0_epc + 8; | |
632 | return 1; | |
633 | case ldc2_op: /* This is bbit032 on Octeon */ | |
634 | if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) | |
635 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
636 | else | |
637 | *contpc = regs->cp0_epc + 8; | |
638 | return 1; | |
639 | case swc2_op: /* This is bbit1 on Octeon */ | |
640 | if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) | |
641 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
642 | else | |
643 | *contpc = regs->cp0_epc + 8; | |
644 | return 1; | |
645 | case sdc2_op: /* This is bbit132 on Octeon */ | |
646 | if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) | |
647 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
648 | else | |
649 | *contpc = regs->cp0_epc + 8; | |
650 | return 1; | |
8467ca01 MC |
651 | #else |
652 | case bc6_op: | |
653 | /* | |
654 | * Only valid for MIPS R6 but we can still end up | |
655 | * here from a broken userland so just tell emulator | |
656 | * this is not a branch and let it break later on. | |
657 | */ | |
658 | if (!cpu_has_mips_r6) | |
659 | break; | |
660 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
661 | dec_insn.next_pc_inc; | |
662 | ||
663 | return 1; | |
c26d4219 | 664 | #endif |
1da177e4 LT |
665 | case cop0_op: |
666 | case cop1_op: | |
c8a34581 MC |
667 | /* Need to check for R6 bc1nez and bc1eqz branches */ |
668 | if (cpu_has_mips_r6 && | |
669 | ((insn.i_format.rs == bc1eqz_op) || | |
670 | (insn.i_format.rs == bc1nez_op))) { | |
671 | bit = 0; | |
672 | switch (insn.i_format.rs) { | |
673 | case bc1eqz_op: | |
674 | if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) | |
675 | bit = 1; | |
676 | break; | |
677 | case bc1nez_op: | |
678 | if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) | |
679 | bit = 1; | |
680 | break; | |
681 | } | |
682 | if (bit) | |
683 | *contpc = regs->cp0_epc + | |
684 | dec_insn.pc_inc + | |
685 | (insn.i_format.simmediate << 2); | |
686 | else | |
687 | *contpc = regs->cp0_epc + | |
688 | dec_insn.pc_inc + | |
689 | dec_insn.next_pc_inc; | |
690 | ||
691 | return 1; | |
692 | } | |
693 | /* R2/R6 compatible cop1 instruction. Fall through */ | |
1da177e4 LT |
694 | case cop2_op: |
695 | case cop1x_op: | |
102cedc3 LY |
696 | if (insn.i_format.rs == bc_op) { |
697 | preempt_disable(); | |
698 | if (is_fpu_owner()) | |
842dfc11 | 699 | fcr31 = read_32bit_cp1_register(CP1_STATUS); |
102cedc3 LY |
700 | else |
701 | fcr31 = current->thread.fpu.fcr31; | |
702 | preempt_enable(); | |
703 | ||
704 | bit = (insn.i_format.rt >> 2); | |
705 | bit += (bit != 0); | |
706 | bit += 23; | |
707 | switch (insn.i_format.rt & 3) { | |
708 | case 0: /* bc1f */ | |
709 | case 2: /* bc1fl */ | |
710 | if (~fcr31 & (1 << bit)) | |
711 | *contpc = regs->cp0_epc + | |
712 | dec_insn.pc_inc + | |
713 | (insn.i_format.simmediate << 2); | |
714 | else | |
715 | *contpc = regs->cp0_epc + | |
716 | dec_insn.pc_inc + | |
717 | dec_insn.next_pc_inc; | |
718 | return 1; | |
102cedc3 LY |
719 | case 1: /* bc1t */ |
720 | case 3: /* bc1tl */ | |
721 | if (fcr31 & (1 << bit)) | |
722 | *contpc = regs->cp0_epc + | |
723 | dec_insn.pc_inc + | |
724 | (insn.i_format.simmediate << 2); | |
725 | else | |
726 | *contpc = regs->cp0_epc + | |
727 | dec_insn.pc_inc + | |
728 | dec_insn.next_pc_inc; | |
729 | return 1; | |
102cedc3 LY |
730 | } |
731 | } | |
1da177e4 LT |
732 | break; |
733 | } | |
1da177e4 LT |
734 | return 0; |
735 | } | |
736 | ||
737 | /* | |
738 | * In the Linux kernel, we support selection of FPR format on the | |
70342287 | 739 | * basis of the Status.FR bit. If an FPU is not present, the FR bit |
da0bac33 | 740 | * is hardwired to zero, which would imply a 32-bit FPU even for |
597ce172 | 741 | * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. |
51d943f0 RB |
742 | * FPU emu is slow and bulky and optimizing this function offers fairly |
743 | * sizeable benefits so we try to be clever and make this function return | |
744 | * a constant whenever possible, that is on 64-bit kernels without O32 | |
597ce172 | 745 | * compatibility enabled and on 32-bit without 64-bit FPU support. |
1da177e4 | 746 | */ |
da0bac33 DD |
747 | static inline int cop1_64bit(struct pt_regs *xcp) |
748 | { | |
08a07904 RB |
749 | if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) |
750 | return 1; | |
751 | else if (config_enabled(CONFIG_32BIT) && | |
752 | !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) | |
753 | return 0; | |
754 | ||
597ce172 | 755 | return !test_thread_flag(TIF_32BIT_FPREGS); |
da0bac33 DD |
756 | } |
757 | ||
4227a2d4 PB |
758 | static inline bool hybrid_fprs(void) |
759 | { | |
760 | return test_thread_flag(TIF_HYBRID_FPREGS); | |
761 | } | |
762 | ||
47fa0c02 RB |
763 | #define SIFROMREG(si, x) \ |
764 | do { \ | |
4227a2d4 | 765 | if (cop1_64bit(xcp) && !hybrid_fprs()) \ |
c8c0da6b | 766 | (si) = (int)get_fpr32(&ctx->fpr[x], 0); \ |
bbd426f5 | 767 | else \ |
c8c0da6b | 768 | (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ |
bbd426f5 | 769 | } while (0) |
1da177e4 | 770 | |
47fa0c02 RB |
771 | #define SITOREG(si, x) \ |
772 | do { \ | |
4227a2d4 | 773 | if (cop1_64bit(xcp) && !hybrid_fprs()) { \ |
ef1c47af | 774 | unsigned i; \ |
bbd426f5 | 775 | set_fpr32(&ctx->fpr[x], 0, si); \ |
ef1c47af PB |
776 | for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ |
777 | set_fpr32(&ctx->fpr[x], i, 0); \ | |
778 | } else { \ | |
bbd426f5 | 779 | set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ |
ef1c47af | 780 | } \ |
bbd426f5 | 781 | } while (0) |
1da177e4 | 782 | |
c8c0da6b | 783 | #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1)) |
ef1c47af | 784 | |
47fa0c02 RB |
785 | #define SITOHREG(si, x) \ |
786 | do { \ | |
ef1c47af PB |
787 | unsigned i; \ |
788 | set_fpr32(&ctx->fpr[x], 1, si); \ | |
789 | for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ | |
790 | set_fpr32(&ctx->fpr[x], i, 0); \ | |
791 | } while (0) | |
1ac94400 | 792 | |
47fa0c02 | 793 | #define DIFROMREG(di, x) \ |
bbd426f5 PB |
794 | ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) |
795 | ||
47fa0c02 RB |
796 | #define DITOREG(di, x) \ |
797 | do { \ | |
ef1c47af PB |
798 | unsigned fpr, i; \ |
799 | fpr = (x) & ~(cop1_64bit(xcp) == 0); \ | |
800 | set_fpr64(&ctx->fpr[fpr], 0, di); \ | |
801 | for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ | |
802 | set_fpr64(&ctx->fpr[fpr], i, 0); \ | |
803 | } while (0) | |
1da177e4 | 804 | |
21a151d8 RB |
805 | #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) |
806 | #define SPTOREG(sp, x) SITOREG((sp).bits, x) | |
807 | #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) | |
808 | #define DPTOREG(dp, x) DITOREG((dp).bits, x) | |
1da177e4 LT |
809 | |
810 | /* | |
811 | * Emulate the single floating point instruction pointed at by EPC. | |
812 | * Two instructions if the instruction is in a branch delay slot. | |
813 | */ | |
814 | ||
515b029d | 815 | static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
102cedc3 | 816 | struct mm_decoded_insn dec_insn, void *__user *fault_addr) |
1da177e4 | 817 | { |
102cedc3 | 818 | unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; |
3f7cac41 RB |
819 | unsigned int cond, cbit; |
820 | mips_instruction ir; | |
821 | int likely, pc_inc; | |
822 | u32 __user *wva; | |
823 | u64 __user *dva; | |
824 | u32 value; | |
825 | u32 wval; | |
826 | u64 dval; | |
827 | int sig; | |
1da177e4 | 828 | |
70e4c234 RB |
829 | /* |
830 | * These are giving gcc a gentle hint about what to expect in | |
831 | * dec_inst in order to do better optimization. | |
832 | */ | |
833 | if (!cpu_has_mmips && dec_insn.micro_mips_mode) | |
834 | unreachable(); | |
835 | ||
1da177e4 | 836 | /* XXX NEC Vr54xx bug workaround */ |
e7e9cae5 | 837 | if (delay_slot(xcp)) { |
102cedc3 LY |
838 | if (dec_insn.micro_mips_mode) { |
839 | if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) | |
e7e9cae5 | 840 | clear_delay_slot(xcp); |
102cedc3 LY |
841 | } else { |
842 | if (!isBranchInstr(xcp, dec_insn, &contpc)) | |
e7e9cae5 | 843 | clear_delay_slot(xcp); |
102cedc3 LY |
844 | } |
845 | } | |
1da177e4 | 846 | |
e7e9cae5 | 847 | if (delay_slot(xcp)) { |
1da177e4 LT |
848 | /* |
849 | * The instruction to be emulated is in a branch delay slot | |
70342287 | 850 | * which means that we have to emulate the branch instruction |
1da177e4 LT |
851 | * BEFORE we do the cop1 instruction. |
852 | * | |
853 | * This branch could be a COP1 branch, but in that case we | |
854 | * would have had a trap for that instruction, and would not | |
855 | * come through this route. | |
856 | * | |
857 | * Linux MIPS branch emulator operates on context, updating the | |
858 | * cp0_epc. | |
859 | */ | |
102cedc3 LY |
860 | ir = dec_insn.next_insn; /* process delay slot instr */ |
861 | pc_inc = dec_insn.next_pc_inc; | |
862 | } else { | |
863 | ir = dec_insn.insn; /* process current instr */ | |
864 | pc_inc = dec_insn.pc_inc; | |
865 | } | |
1da177e4 | 866 | |
102cedc3 LY |
867 | /* |
868 | * Since microMIPS FPU instructios are a subset of MIPS32 FPU | |
869 | * instructions, we want to convert microMIPS FPU instructions | |
870 | * into MIPS32 instructions so that we could reuse all of the | |
871 | * FPU emulation code. | |
872 | * | |
873 | * NOTE: We cannot do this for branch instructions since they | |
874 | * are not a subset. Example: Cannot emulate a 16-bit | |
875 | * aligned target address with a MIPS32 instruction. | |
876 | */ | |
877 | if (dec_insn.micro_mips_mode) { | |
878 | /* | |
879 | * If next instruction is a 16-bit instruction, then it | |
880 | * it cannot be a FPU instruction. This could happen | |
881 | * since we can be called for non-FPU instructions. | |
882 | */ | |
883 | if ((pc_inc == 2) || | |
884 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) | |
885 | == SIGILL)) | |
1da177e4 | 886 | return SIGILL; |
1da177e4 LT |
887 | } |
888 | ||
3f7cac41 | 889 | emul: |
a8b0ca17 | 890 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); |
b6ee75ed | 891 | MIPS_FPU_EMU_INC_STATS(emulated); |
1da177e4 | 892 | switch (MIPSInst_OPCODE(ir)) { |
3f7cac41 RB |
893 | case ldc1_op: |
894 | dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
895 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 896 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 897 | |
3f7cac41 | 898 | if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { |
b6ee75ed | 899 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 900 | *fault_addr = dva; |
1da177e4 LT |
901 | return SIGBUS; |
902 | } | |
3f7cac41 | 903 | if (__get_user(dval, dva)) { |
515b029d | 904 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 905 | *fault_addr = dva; |
515b029d DD |
906 | return SIGSEGV; |
907 | } | |
3f7cac41 | 908 | DITOREG(dval, MIPSInst_RT(ir)); |
1da177e4 | 909 | break; |
1da177e4 | 910 | |
3f7cac41 RB |
911 | case sdc1_op: |
912 | dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
913 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 914 | MIPS_FPU_EMU_INC_STATS(stores); |
3f7cac41 RB |
915 | DIFROMREG(dval, MIPSInst_RT(ir)); |
916 | if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { | |
b6ee75ed | 917 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 918 | *fault_addr = dva; |
1da177e4 LT |
919 | return SIGBUS; |
920 | } | |
3f7cac41 | 921 | if (__put_user(dval, dva)) { |
515b029d | 922 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 923 | *fault_addr = dva; |
515b029d DD |
924 | return SIGSEGV; |
925 | } | |
1da177e4 | 926 | break; |
1da177e4 | 927 | |
3f7cac41 RB |
928 | case lwc1_op: |
929 | wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
930 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 931 | MIPS_FPU_EMU_INC_STATS(loads); |
3f7cac41 | 932 | if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { |
b6ee75ed | 933 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 934 | *fault_addr = wva; |
1da177e4 LT |
935 | return SIGBUS; |
936 | } | |
3f7cac41 | 937 | if (__get_user(wval, wva)) { |
515b029d | 938 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 939 | *fault_addr = wva; |
515b029d DD |
940 | return SIGSEGV; |
941 | } | |
3f7cac41 | 942 | SITOREG(wval, MIPSInst_RT(ir)); |
1da177e4 | 943 | break; |
1da177e4 | 944 | |
3f7cac41 RB |
945 | case swc1_op: |
946 | wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + | |
947 | MIPSInst_SIMM(ir)); | |
b6ee75ed | 948 | MIPS_FPU_EMU_INC_STATS(stores); |
3f7cac41 RB |
949 | SIFROMREG(wval, MIPSInst_RT(ir)); |
950 | if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { | |
b6ee75ed | 951 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 952 | *fault_addr = wva; |
1da177e4 LT |
953 | return SIGBUS; |
954 | } | |
3f7cac41 | 955 | if (__put_user(wval, wva)) { |
515b029d | 956 | MIPS_FPU_EMU_INC_STATS(errors); |
3f7cac41 | 957 | *fault_addr = wva; |
515b029d DD |
958 | return SIGSEGV; |
959 | } | |
1da177e4 | 960 | break; |
1da177e4 LT |
961 | |
962 | case cop1_op: | |
963 | switch (MIPSInst_RS(ir)) { | |
1da177e4 | 964 | case dmfc_op: |
08a07904 RB |
965 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
966 | return SIGILL; | |
967 | ||
1da177e4 LT |
968 | /* copregister fs -> gpr[rt] */ |
969 | if (MIPSInst_RT(ir) != 0) { | |
970 | DIFROMREG(xcp->regs[MIPSInst_RT(ir)], | |
971 | MIPSInst_RD(ir)); | |
972 | } | |
973 | break; | |
974 | ||
975 | case dmtc_op: | |
08a07904 RB |
976 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
977 | return SIGILL; | |
978 | ||
1da177e4 LT |
979 | /* copregister fs <- rt */ |
980 | DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); | |
981 | break; | |
1da177e4 | 982 | |
1ac94400 LY |
983 | case mfhc_op: |
984 | if (!cpu_has_mips_r2) | |
985 | goto sigill; | |
986 | ||
987 | /* copregister rd -> gpr[rt] */ | |
988 | if (MIPSInst_RT(ir) != 0) { | |
989 | SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], | |
990 | MIPSInst_RD(ir)); | |
991 | } | |
992 | break; | |
993 | ||
994 | case mthc_op: | |
995 | if (!cpu_has_mips_r2) | |
996 | goto sigill; | |
997 | ||
998 | /* copregister rd <- gpr[rt] */ | |
999 | SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); | |
1000 | break; | |
1001 | ||
1da177e4 LT |
1002 | case mfc_op: |
1003 | /* copregister rd -> gpr[rt] */ | |
1da177e4 LT |
1004 | if (MIPSInst_RT(ir) != 0) { |
1005 | SIFROMREG(xcp->regs[MIPSInst_RT(ir)], | |
1006 | MIPSInst_RD(ir)); | |
1007 | } | |
1008 | break; | |
1009 | ||
1010 | case mtc_op: | |
1011 | /* copregister rd <- rt */ | |
1da177e4 LT |
1012 | SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); |
1013 | break; | |
1014 | ||
3f7cac41 | 1015 | case cfc_op: |
1da177e4 | 1016 | /* cop control register rd -> gpr[rt] */ |
1da177e4 LT |
1017 | if (MIPSInst_RD(ir) == FPCREG_CSR) { |
1018 | value = ctx->fcr31; | |
56a64733 | 1019 | value = (value & ~FPU_CSR_RM) | modeindex(value); |
92df0f8b RB |
1020 | pr_debug("%p gpr[%d]<-csr=%08x\n", |
1021 | (void *) (xcp->cp0_epc), | |
1022 | MIPSInst_RT(ir), value); | |
1da177e4 LT |
1023 | } |
1024 | else if (MIPSInst_RD(ir) == FPCREG_RID) | |
1025 | value = 0; | |
1026 | else | |
1027 | value = 0; | |
1028 | if (MIPSInst_RT(ir)) | |
1029 | xcp->regs[MIPSInst_RT(ir)] = value; | |
1030 | break; | |
1da177e4 | 1031 | |
3f7cac41 | 1032 | case ctc_op: |
1da177e4 | 1033 | /* copregister rd <- rt */ |
1da177e4 LT |
1034 | if (MIPSInst_RT(ir) == 0) |
1035 | value = 0; | |
1036 | else | |
1037 | value = xcp->regs[MIPSInst_RT(ir)]; | |
1038 | ||
1039 | /* we only have one writable control reg | |
1040 | */ | |
1041 | if (MIPSInst_RD(ir) == FPCREG_CSR) { | |
92df0f8b RB |
1042 | pr_debug("%p gpr[%d]->csr=%08x\n", |
1043 | (void *) (xcp->cp0_epc), | |
1044 | MIPSInst_RT(ir), value); | |
95e8f634 SM |
1045 | |
1046 | /* | |
1047 | * Don't write reserved bits, | |
1048 | * and convert to ieee library modes | |
1049 | */ | |
56a64733 RB |
1050 | ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) | |
1051 | modeindex(value); | |
1da177e4 LT |
1052 | } |
1053 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { | |
1054 | return SIGFPE; | |
1055 | } | |
1056 | break; | |
1da177e4 | 1057 | |
3f7cac41 | 1058 | case bc_op: |
e7e9cae5 | 1059 | if (delay_slot(xcp)) |
1da177e4 LT |
1060 | return SIGILL; |
1061 | ||
08a07904 RB |
1062 | if (cpu_has_mips_4_5_r) |
1063 | cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
1064 | else | |
1065 | cbit = FPU_CSR_COND; | |
1066 | cond = ctx->fcr31 & cbit; | |
1067 | ||
3f7cac41 | 1068 | likely = 0; |
1da177e4 LT |
1069 | switch (MIPSInst_RT(ir) & 3) { |
1070 | case bcfl_op: | |
1071 | likely = 1; | |
1072 | case bcf_op: | |
1073 | cond = !cond; | |
1074 | break; | |
1075 | case bctl_op: | |
1076 | likely = 1; | |
1077 | case bct_op: | |
1078 | break; | |
1079 | default: | |
1080 | /* thats an illegal instruction */ | |
1081 | return SIGILL; | |
1082 | } | |
1083 | ||
e7e9cae5 | 1084 | set_delay_slot(xcp); |
1da177e4 | 1085 | if (cond) { |
3f7cac41 RB |
1086 | /* |
1087 | * Branch taken: emulate dslot instruction | |
1da177e4 | 1088 | */ |
102cedc3 LY |
1089 | xcp->cp0_epc += dec_insn.pc_inc; |
1090 | ||
1091 | contpc = MIPSInst_SIMM(ir); | |
1092 | ir = dec_insn.next_insn; | |
1093 | if (dec_insn.micro_mips_mode) { | |
1094 | contpc = (xcp->cp0_epc + (contpc << 1)); | |
1095 | ||
1096 | /* If 16-bit instruction, not FPU. */ | |
1097 | if ((dec_insn.next_pc_inc == 2) || | |
1098 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { | |
1099 | ||
1100 | /* | |
1101 | * Since this instruction will | |
1102 | * be put on the stack with | |
1103 | * 32-bit words, get around | |
1104 | * this problem by putting a | |
1105 | * NOP16 as the second one. | |
1106 | */ | |
1107 | if (dec_insn.next_pc_inc == 2) | |
1108 | ir = (ir & (~0xffff)) | MM_NOP16; | |
1109 | ||
1110 | /* | |
1111 | * Single step the non-CP1 | |
1112 | * instruction in the dslot. | |
1113 | */ | |
1114 | return mips_dsemul(xcp, ir, contpc); | |
1115 | } | |
1116 | } else | |
1117 | contpc = (xcp->cp0_epc + (contpc << 2)); | |
1da177e4 LT |
1118 | |
1119 | switch (MIPSInst_OPCODE(ir)) { | |
1120 | case lwc1_op: | |
08a07904 | 1121 | goto emul; |
3f7cac41 | 1122 | |
1da177e4 | 1123 | case swc1_op: |
08a07904 | 1124 | goto emul; |
3f7cac41 | 1125 | |
1da177e4 LT |
1126 | case ldc1_op: |
1127 | case sdc1_op: | |
08a07904 RB |
1128 | if (cpu_has_mips_2_3_4_5 || |
1129 | cpu_has_mips64) | |
1130 | goto emul; | |
1131 | ||
1132 | return SIGILL; | |
1133 | goto emul; | |
3f7cac41 | 1134 | |
1da177e4 | 1135 | case cop1_op: |
1da177e4 | 1136 | goto emul; |
3f7cac41 | 1137 | |
08a07904 | 1138 | case cop1x_op: |
a5466d7b | 1139 | if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2) |
08a07904 RB |
1140 | /* its one of ours */ |
1141 | goto emul; | |
1142 | ||
1143 | return SIGILL; | |
3f7cac41 | 1144 | |
1da177e4 | 1145 | case spec_op: |
08a07904 RB |
1146 | if (!cpu_has_mips_4_5_r) |
1147 | return SIGILL; | |
1148 | ||
1da177e4 LT |
1149 | if (MIPSInst_FUNC(ir) == movc_op) |
1150 | goto emul; | |
1151 | break; | |
1da177e4 LT |
1152 | } |
1153 | ||
1154 | /* | |
1155 | * Single step the non-cp1 | |
1156 | * instruction in the dslot | |
1157 | */ | |
e70dfc10 | 1158 | return mips_dsemul(xcp, ir, contpc); |
3f7cac41 | 1159 | } else if (likely) { /* branch not taken */ |
1da177e4 LT |
1160 | /* |
1161 | * branch likely nullifies | |
1162 | * dslot if not taken | |
1163 | */ | |
102cedc3 LY |
1164 | xcp->cp0_epc += dec_insn.pc_inc; |
1165 | contpc += dec_insn.pc_inc; | |
1da177e4 LT |
1166 | /* |
1167 | * else continue & execute | |
1168 | * dslot as normal insn | |
1169 | */ | |
1170 | } | |
1da177e4 | 1171 | break; |
1da177e4 LT |
1172 | |
1173 | default: | |
1174 | if (!(MIPSInst_RS(ir) & 0x10)) | |
1175 | return SIGILL; | |
1da177e4 | 1176 | |
3f7cac41 RB |
1177 | /* a real fpu computation instruction */ |
1178 | if ((sig = fpu_emu(xcp, ctx, ir))) | |
1179 | return sig; | |
1da177e4 LT |
1180 | } |
1181 | break; | |
1182 | ||
3f7cac41 | 1183 | case cop1x_op: |
a5466d7b | 1184 | if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2) |
08a07904 RB |
1185 | return SIGILL; |
1186 | ||
1187 | sig = fpux_emu(xcp, ctx, ir, fault_addr); | |
515b029d | 1188 | if (sig) |
1da177e4 LT |
1189 | return sig; |
1190 | break; | |
1da177e4 | 1191 | |
1da177e4 | 1192 | case spec_op: |
08a07904 RB |
1193 | if (!cpu_has_mips_4_5_r) |
1194 | return SIGILL; | |
1195 | ||
1da177e4 LT |
1196 | if (MIPSInst_FUNC(ir) != movc_op) |
1197 | return SIGILL; | |
1198 | cond = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
1199 | if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) | |
1200 | xcp->regs[MIPSInst_RD(ir)] = | |
1201 | xcp->regs[MIPSInst_RS(ir)]; | |
1202 | break; | |
1da177e4 | 1203 | default: |
1ac94400 | 1204 | sigill: |
1da177e4 LT |
1205 | return SIGILL; |
1206 | } | |
1207 | ||
1208 | /* we did it !! */ | |
e70dfc10 | 1209 | xcp->cp0_epc = contpc; |
e7e9cae5 | 1210 | clear_delay_slot(xcp); |
333d1f67 | 1211 | |
1da177e4 LT |
1212 | return 0; |
1213 | } | |
1214 | ||
1215 | /* | |
1216 | * Conversion table from MIPS compare ops 48-63 | |
1217 | * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); | |
1218 | */ | |
1219 | static const unsigned char cmptab[8] = { | |
1220 | 0, /* cmp_0 (sig) cmp_sf */ | |
1221 | IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ | |
1222 | IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ | |
1223 | IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ | |
1224 | IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ | |
1225 | IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ | |
1226 | IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ | |
1227 | IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ | |
1228 | }; | |
1229 | ||
1230 | ||
1da177e4 LT |
1231 | /* |
1232 | * Additional MIPS4 instructions | |
1233 | */ | |
1234 | ||
47fa0c02 RB |
1235 | #define DEF3OP(name, p, f1, f2, f3) \ |
1236 | static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ | |
1237 | union ieee754##p s, union ieee754##p t) \ | |
1238 | { \ | |
1239 | struct _ieee754_csr ieee754_csr_save; \ | |
1240 | s = f1(s, t); \ | |
1241 | ieee754_csr_save = ieee754_csr; \ | |
1242 | s = f2(s, r); \ | |
1243 | ieee754_csr_save.cx |= ieee754_csr.cx; \ | |
1244 | ieee754_csr_save.sx |= ieee754_csr.sx; \ | |
1245 | s = f3(s); \ | |
1246 | ieee754_csr.cx |= ieee754_csr_save.cx; \ | |
1247 | ieee754_csr.sx |= ieee754_csr_save.sx; \ | |
1248 | return s; \ | |
1da177e4 LT |
1249 | } |
1250 | ||
2209bcb1 | 1251 | static union ieee754dp fpemu_dp_recip(union ieee754dp d) |
1da177e4 LT |
1252 | { |
1253 | return ieee754dp_div(ieee754dp_one(0), d); | |
1254 | } | |
1255 | ||
2209bcb1 | 1256 | static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) |
1da177e4 LT |
1257 | { |
1258 | return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); | |
1259 | } | |
1260 | ||
2209bcb1 | 1261 | static union ieee754sp fpemu_sp_recip(union ieee754sp s) |
1da177e4 LT |
1262 | { |
1263 | return ieee754sp_div(ieee754sp_one(0), s); | |
1264 | } | |
1265 | ||
2209bcb1 | 1266 | static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) |
1da177e4 LT |
1267 | { |
1268 | return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); | |
1269 | } | |
1270 | ||
21a151d8 RB |
1271 | DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); |
1272 | DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); | |
1da177e4 LT |
1273 | DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); |
1274 | DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); | |
21a151d8 RB |
1275 | DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); |
1276 | DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); | |
1da177e4 LT |
1277 | DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); |
1278 | DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); | |
1279 | ||
eae89076 | 1280 | static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
515b029d | 1281 | mips_instruction ir, void *__user *fault_addr) |
1da177e4 LT |
1282 | { |
1283 | unsigned rcsr = 0; /* resulting csr */ | |
1284 | ||
b6ee75ed | 1285 | MIPS_FPU_EMU_INC_STATS(cp1xops); |
1da177e4 LT |
1286 | |
1287 | switch (MIPSInst_FMA_FFMT(ir)) { | |
1288 | case s_fmt:{ /* 0 */ | |
1289 | ||
2209bcb1 RB |
1290 | union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); |
1291 | union ieee754sp fd, fr, fs, ft; | |
3fccc015 | 1292 | u32 __user *va; |
1da177e4 LT |
1293 | u32 val; |
1294 | ||
1295 | switch (MIPSInst_FUNC(ir)) { | |
1296 | case lwxc1_op: | |
3fccc015 | 1297 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1298 | xcp->regs[MIPSInst_FT(ir)]); |
1299 | ||
b6ee75ed | 1300 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1301 | if (!access_ok(VERIFY_READ, va, sizeof(u32))) { |
b6ee75ed | 1302 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1303 | *fault_addr = va; |
1da177e4 LT |
1304 | return SIGBUS; |
1305 | } | |
515b029d DD |
1306 | if (__get_user(val, va)) { |
1307 | MIPS_FPU_EMU_INC_STATS(errors); | |
1308 | *fault_addr = va; | |
1309 | return SIGSEGV; | |
1310 | } | |
1da177e4 LT |
1311 | SITOREG(val, MIPSInst_FD(ir)); |
1312 | break; | |
1313 | ||
1314 | case swxc1_op: | |
3fccc015 | 1315 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1316 | xcp->regs[MIPSInst_FT(ir)]); |
1317 | ||
b6ee75ed | 1318 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 LT |
1319 | |
1320 | SIFROMREG(val, MIPSInst_FS(ir)); | |
515b029d | 1321 | if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { |
b6ee75ed | 1322 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1323 | *fault_addr = va; |
1da177e4 LT |
1324 | return SIGBUS; |
1325 | } | |
515b029d DD |
1326 | if (put_user(val, va)) { |
1327 | MIPS_FPU_EMU_INC_STATS(errors); | |
1328 | *fault_addr = va; | |
1329 | return SIGSEGV; | |
1330 | } | |
1da177e4 LT |
1331 | break; |
1332 | ||
1333 | case madd_s_op: | |
1334 | handler = fpemu_sp_madd; | |
1335 | goto scoptop; | |
1336 | case msub_s_op: | |
1337 | handler = fpemu_sp_msub; | |
1338 | goto scoptop; | |
1339 | case nmadd_s_op: | |
1340 | handler = fpemu_sp_nmadd; | |
1341 | goto scoptop; | |
1342 | case nmsub_s_op: | |
1343 | handler = fpemu_sp_nmsub; | |
1344 | goto scoptop; | |
1345 | ||
1346 | scoptop: | |
1347 | SPFROMREG(fr, MIPSInst_FR(ir)); | |
1348 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1349 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1350 | fd = (*handler) (fr, fs, ft); | |
1351 | SPTOREG(fd, MIPSInst_FD(ir)); | |
1352 | ||
1353 | copcsr: | |
c4103526 DZ |
1354 | if (ieee754_cxtest(IEEE754_INEXACT)) { |
1355 | MIPS_FPU_EMU_INC_STATS(ieee754_inexact); | |
1da177e4 | 1356 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; |
c4103526 DZ |
1357 | } |
1358 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) { | |
1359 | MIPS_FPU_EMU_INC_STATS(ieee754_underflow); | |
1da177e4 | 1360 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; |
c4103526 DZ |
1361 | } |
1362 | if (ieee754_cxtest(IEEE754_OVERFLOW)) { | |
1363 | MIPS_FPU_EMU_INC_STATS(ieee754_overflow); | |
1da177e4 | 1364 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; |
c4103526 DZ |
1365 | } |
1366 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { | |
1367 | MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); | |
1da177e4 | 1368 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; |
c4103526 | 1369 | } |
1da177e4 LT |
1370 | |
1371 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; | |
1da177e4 | 1372 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { |
3f7cac41 | 1373 | /*printk ("SIGFPE: FPU csr = %08x\n", |
1da177e4 LT |
1374 | ctx->fcr31); */ |
1375 | return SIGFPE; | |
1376 | } | |
1377 | ||
1378 | break; | |
1379 | ||
1380 | default: | |
1381 | return SIGILL; | |
1382 | } | |
1383 | break; | |
1384 | } | |
1385 | ||
1da177e4 | 1386 | case d_fmt:{ /* 1 */ |
2209bcb1 RB |
1387 | union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); |
1388 | union ieee754dp fd, fr, fs, ft; | |
3fccc015 | 1389 | u64 __user *va; |
1da177e4 LT |
1390 | u64 val; |
1391 | ||
1392 | switch (MIPSInst_FUNC(ir)) { | |
1393 | case ldxc1_op: | |
3fccc015 | 1394 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1395 | xcp->regs[MIPSInst_FT(ir)]); |
1396 | ||
b6ee75ed | 1397 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1398 | if (!access_ok(VERIFY_READ, va, sizeof(u64))) { |
b6ee75ed | 1399 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1400 | *fault_addr = va; |
1da177e4 LT |
1401 | return SIGBUS; |
1402 | } | |
515b029d DD |
1403 | if (__get_user(val, va)) { |
1404 | MIPS_FPU_EMU_INC_STATS(errors); | |
1405 | *fault_addr = va; | |
1406 | return SIGSEGV; | |
1407 | } | |
1da177e4 LT |
1408 | DITOREG(val, MIPSInst_FD(ir)); |
1409 | break; | |
1410 | ||
1411 | case sdxc1_op: | |
3fccc015 | 1412 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1413 | xcp->regs[MIPSInst_FT(ir)]); |
1414 | ||
b6ee75ed | 1415 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 | 1416 | DIFROMREG(val, MIPSInst_FS(ir)); |
515b029d | 1417 | if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { |
b6ee75ed | 1418 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1419 | *fault_addr = va; |
1da177e4 LT |
1420 | return SIGBUS; |
1421 | } | |
515b029d DD |
1422 | if (__put_user(val, va)) { |
1423 | MIPS_FPU_EMU_INC_STATS(errors); | |
1424 | *fault_addr = va; | |
1425 | return SIGSEGV; | |
1426 | } | |
1da177e4 LT |
1427 | break; |
1428 | ||
1429 | case madd_d_op: | |
1430 | handler = fpemu_dp_madd; | |
1431 | goto dcoptop; | |
1432 | case msub_d_op: | |
1433 | handler = fpemu_dp_msub; | |
1434 | goto dcoptop; | |
1435 | case nmadd_d_op: | |
1436 | handler = fpemu_dp_nmadd; | |
1437 | goto dcoptop; | |
1438 | case nmsub_d_op: | |
1439 | handler = fpemu_dp_nmsub; | |
1440 | goto dcoptop; | |
1441 | ||
1442 | dcoptop: | |
1443 | DPFROMREG(fr, MIPSInst_FR(ir)); | |
1444 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1445 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1446 | fd = (*handler) (fr, fs, ft); | |
1447 | DPTOREG(fd, MIPSInst_FD(ir)); | |
1448 | goto copcsr; | |
1449 | ||
1450 | default: | |
1451 | return SIGILL; | |
1452 | } | |
1453 | break; | |
1454 | } | |
1da177e4 | 1455 | |
51061b88 DZ |
1456 | case 0x3: |
1457 | if (MIPSInst_FUNC(ir) != pfetch_op) | |
1da177e4 | 1458 | return SIGILL; |
51061b88 | 1459 | |
1da177e4 LT |
1460 | /* ignore prefx operation */ |
1461 | break; | |
1462 | ||
1463 | default: | |
1464 | return SIGILL; | |
1465 | } | |
1466 | ||
1467 | return 0; | |
1468 | } | |
1da177e4 LT |
1469 | |
1470 | ||
1471 | ||
1472 | /* | |
1473 | * Emulate a single COP1 arithmetic instruction. | |
1474 | */ | |
eae89076 | 1475 | static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
1da177e4 LT |
1476 | mips_instruction ir) |
1477 | { | |
1478 | int rfmt; /* resulting format */ | |
1479 | unsigned rcsr = 0; /* resulting csr */ | |
3f7cac41 RB |
1480 | unsigned int oldrm; |
1481 | unsigned int cbit; | |
1da177e4 LT |
1482 | unsigned cond; |
1483 | union { | |
2209bcb1 RB |
1484 | union ieee754dp d; |
1485 | union ieee754sp s; | |
1da177e4 | 1486 | int w; |
1da177e4 | 1487 | s64 l; |
1da177e4 | 1488 | } rv; /* resulting value */ |
3f7cac41 | 1489 | u64 bits; |
1da177e4 | 1490 | |
b6ee75ed | 1491 | MIPS_FPU_EMU_INC_STATS(cp1ops); |
1da177e4 | 1492 | switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { |
3f7cac41 | 1493 | case s_fmt: { /* 0 */ |
1da177e4 | 1494 | union { |
2209bcb1 RB |
1495 | union ieee754sp(*b) (union ieee754sp, union ieee754sp); |
1496 | union ieee754sp(*u) (union ieee754sp); | |
1da177e4 | 1497 | } handler; |
3f7cac41 | 1498 | union ieee754sp fs, ft; |
1da177e4 LT |
1499 | |
1500 | switch (MIPSInst_FUNC(ir)) { | |
1501 | /* binary ops */ | |
1502 | case fadd_op: | |
1503 | handler.b = ieee754sp_add; | |
1504 | goto scopbop; | |
1505 | case fsub_op: | |
1506 | handler.b = ieee754sp_sub; | |
1507 | goto scopbop; | |
1508 | case fmul_op: | |
1509 | handler.b = ieee754sp_mul; | |
1510 | goto scopbop; | |
1511 | case fdiv_op: | |
1512 | handler.b = ieee754sp_div; | |
1513 | goto scopbop; | |
1514 | ||
1515 | /* unary ops */ | |
1da177e4 | 1516 | case fsqrt_op: |
08a07904 RB |
1517 | if (!cpu_has_mips_4_5_r) |
1518 | return SIGILL; | |
1519 | ||
1da177e4 LT |
1520 | handler.u = ieee754sp_sqrt; |
1521 | goto scopuop; | |
3f7cac41 | 1522 | |
08a07904 RB |
1523 | /* |
1524 | * Note that on some MIPS IV implementations such as the | |
1525 | * R5000 and R8000 the FSQRT and FRECIP instructions do not | |
1526 | * achieve full IEEE-754 accuracy - however this emulator does. | |
1527 | */ | |
1da177e4 | 1528 | case frsqrt_op: |
08a07904 RB |
1529 | if (!cpu_has_mips_4_5_r2) |
1530 | return SIGILL; | |
1531 | ||
1da177e4 LT |
1532 | handler.u = fpemu_sp_rsqrt; |
1533 | goto scopuop; | |
3f7cac41 | 1534 | |
1da177e4 | 1535 | case frecip_op: |
08a07904 RB |
1536 | if (!cpu_has_mips_4_5_r2) |
1537 | return SIGILL; | |
1538 | ||
1da177e4 LT |
1539 | handler.u = fpemu_sp_recip; |
1540 | goto scopuop; | |
08a07904 | 1541 | |
1da177e4 | 1542 | case fmovc_op: |
08a07904 RB |
1543 | if (!cpu_has_mips_4_5_r) |
1544 | return SIGILL; | |
1545 | ||
1da177e4 LT |
1546 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
1547 | if (((ctx->fcr31 & cond) != 0) != | |
1548 | ((MIPSInst_FT(ir) & 1) != 0)) | |
1549 | return 0; | |
1550 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1551 | break; | |
3f7cac41 | 1552 | |
1da177e4 | 1553 | case fmovz_op: |
08a07904 RB |
1554 | if (!cpu_has_mips_4_5_r) |
1555 | return SIGILL; | |
1556 | ||
1da177e4 LT |
1557 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
1558 | return 0; | |
1559 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1560 | break; | |
3f7cac41 | 1561 | |
1da177e4 | 1562 | case fmovn_op: |
08a07904 RB |
1563 | if (!cpu_has_mips_4_5_r) |
1564 | return SIGILL; | |
1565 | ||
1da177e4 LT |
1566 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
1567 | return 0; | |
1568 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1569 | break; | |
3f7cac41 | 1570 | |
1da177e4 LT |
1571 | case fabs_op: |
1572 | handler.u = ieee754sp_abs; | |
1573 | goto scopuop; | |
3f7cac41 | 1574 | |
1da177e4 LT |
1575 | case fneg_op: |
1576 | handler.u = ieee754sp_neg; | |
1577 | goto scopuop; | |
3f7cac41 | 1578 | |
1da177e4 LT |
1579 | case fmov_op: |
1580 | /* an easy one */ | |
1581 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1582 | goto copcsr; | |
1583 | ||
1584 | /* binary op on handler */ | |
3f7cac41 RB |
1585 | scopbop: |
1586 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1587 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1da177e4 | 1588 | |
3f7cac41 RB |
1589 | rv.s = (*handler.b) (fs, ft); |
1590 | goto copcsr; | |
1591 | scopuop: | |
1592 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1593 | rv.s = (*handler.u) (fs); | |
1594 | goto copcsr; | |
1595 | copcsr: | |
c4103526 DZ |
1596 | if (ieee754_cxtest(IEEE754_INEXACT)) { |
1597 | MIPS_FPU_EMU_INC_STATS(ieee754_inexact); | |
1da177e4 | 1598 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; |
c4103526 DZ |
1599 | } |
1600 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) { | |
1601 | MIPS_FPU_EMU_INC_STATS(ieee754_underflow); | |
1da177e4 | 1602 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; |
c4103526 DZ |
1603 | } |
1604 | if (ieee754_cxtest(IEEE754_OVERFLOW)) { | |
1605 | MIPS_FPU_EMU_INC_STATS(ieee754_overflow); | |
1da177e4 | 1606 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; |
c4103526 DZ |
1607 | } |
1608 | if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) { | |
1609 | MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv); | |
1da177e4 | 1610 | rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; |
c4103526 DZ |
1611 | } |
1612 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { | |
1613 | MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); | |
1da177e4 | 1614 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; |
c4103526 | 1615 | } |
1da177e4 LT |
1616 | break; |
1617 | ||
1618 | /* unary conv ops */ | |
1619 | case fcvts_op: | |
1620 | return SIGILL; /* not defined */ | |
1da177e4 | 1621 | |
3f7cac41 | 1622 | case fcvtd_op: |
1da177e4 LT |
1623 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1624 | rv.d = ieee754dp_fsp(fs); | |
1625 | rfmt = d_fmt; | |
1626 | goto copcsr; | |
1da177e4 | 1627 | |
3f7cac41 | 1628 | case fcvtw_op: |
1da177e4 LT |
1629 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1630 | rv.w = ieee754sp_tint(fs); | |
1631 | rfmt = w_fmt; | |
1632 | goto copcsr; | |
1da177e4 | 1633 | |
1da177e4 LT |
1634 | case fround_op: |
1635 | case ftrunc_op: | |
1636 | case fceil_op: | |
3f7cac41 | 1637 | case ffloor_op: |
08a07904 RB |
1638 | if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64) |
1639 | return SIGILL; | |
1640 | ||
3f7cac41 | 1641 | oldrm = ieee754_csr.rm; |
1da177e4 | 1642 | SPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1643 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1644 | rv.w = ieee754sp_tint(fs); |
1645 | ieee754_csr.rm = oldrm; | |
1646 | rfmt = w_fmt; | |
1647 | goto copcsr; | |
1da177e4 | 1648 | |
3f7cac41 | 1649 | case fcvtl_op: |
08a07904 RB |
1650 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1651 | return SIGILL; | |
1652 | ||
1da177e4 LT |
1653 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1654 | rv.l = ieee754sp_tlong(fs); | |
1655 | rfmt = l_fmt; | |
1656 | goto copcsr; | |
1da177e4 LT |
1657 | |
1658 | case froundl_op: | |
1659 | case ftruncl_op: | |
1660 | case fceill_op: | |
3f7cac41 | 1661 | case ffloorl_op: |
08a07904 RB |
1662 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1663 | return SIGILL; | |
1664 | ||
3f7cac41 | 1665 | oldrm = ieee754_csr.rm; |
1da177e4 | 1666 | SPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1667 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1668 | rv.l = ieee754sp_tlong(fs); |
1669 | ieee754_csr.rm = oldrm; | |
1670 | rfmt = l_fmt; | |
1671 | goto copcsr; | |
1da177e4 LT |
1672 | |
1673 | default: | |
1674 | if (MIPSInst_FUNC(ir) >= fcmp_op) { | |
1675 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; | |
2209bcb1 | 1676 | union ieee754sp fs, ft; |
1da177e4 LT |
1677 | |
1678 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1679 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1680 | rv.w = ieee754sp_cmp(fs, ft, | |
1681 | cmptab[cmpop & 0x7], cmpop & 0x8); | |
1682 | rfmt = -1; | |
1683 | if ((cmpop & 0x8) && ieee754_cxtest | |
1684 | (IEEE754_INVALID_OPERATION)) | |
1685 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1686 | else | |
1687 | goto copcsr; | |
1688 | ||
3f7cac41 | 1689 | } else |
1da177e4 | 1690 | return SIGILL; |
1da177e4 LT |
1691 | break; |
1692 | } | |
1693 | break; | |
1694 | } | |
1695 | ||
3f7cac41 RB |
1696 | case d_fmt: { |
1697 | union ieee754dp fs, ft; | |
1da177e4 | 1698 | union { |
2209bcb1 RB |
1699 | union ieee754dp(*b) (union ieee754dp, union ieee754dp); |
1700 | union ieee754dp(*u) (union ieee754dp); | |
1da177e4 LT |
1701 | } handler; |
1702 | ||
1703 | switch (MIPSInst_FUNC(ir)) { | |
1704 | /* binary ops */ | |
1705 | case fadd_op: | |
1706 | handler.b = ieee754dp_add; | |
1707 | goto dcopbop; | |
1708 | case fsub_op: | |
1709 | handler.b = ieee754dp_sub; | |
1710 | goto dcopbop; | |
1711 | case fmul_op: | |
1712 | handler.b = ieee754dp_mul; | |
1713 | goto dcopbop; | |
1714 | case fdiv_op: | |
1715 | handler.b = ieee754dp_div; | |
1716 | goto dcopbop; | |
1717 | ||
1718 | /* unary ops */ | |
1da177e4 | 1719 | case fsqrt_op: |
08a07904 RB |
1720 | if (!cpu_has_mips_2_3_4_5_r) |
1721 | return SIGILL; | |
1722 | ||
1da177e4 LT |
1723 | handler.u = ieee754dp_sqrt; |
1724 | goto dcopuop; | |
08a07904 RB |
1725 | /* |
1726 | * Note that on some MIPS IV implementations such as the | |
1727 | * R5000 and R8000 the FSQRT and FRECIP instructions do not | |
1728 | * achieve full IEEE-754 accuracy - however this emulator does. | |
1729 | */ | |
1da177e4 | 1730 | case frsqrt_op: |
08a07904 RB |
1731 | if (!cpu_has_mips_4_5_r2) |
1732 | return SIGILL; | |
1733 | ||
1da177e4 LT |
1734 | handler.u = fpemu_dp_rsqrt; |
1735 | goto dcopuop; | |
1736 | case frecip_op: | |
08a07904 RB |
1737 | if (!cpu_has_mips_4_5_r2) |
1738 | return SIGILL; | |
1739 | ||
1da177e4 LT |
1740 | handler.u = fpemu_dp_recip; |
1741 | goto dcopuop; | |
1da177e4 | 1742 | case fmovc_op: |
08a07904 RB |
1743 | if (!cpu_has_mips_4_5_r) |
1744 | return SIGILL; | |
1745 | ||
1da177e4 LT |
1746 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
1747 | if (((ctx->fcr31 & cond) != 0) != | |
1748 | ((MIPSInst_FT(ir) & 1) != 0)) | |
1749 | return 0; | |
1750 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1751 | break; | |
1752 | case fmovz_op: | |
08a07904 RB |
1753 | if (!cpu_has_mips_4_5_r) |
1754 | return SIGILL; | |
1755 | ||
1da177e4 LT |
1756 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
1757 | return 0; | |
1758 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1759 | break; | |
1760 | case fmovn_op: | |
08a07904 RB |
1761 | if (!cpu_has_mips_4_5_r) |
1762 | return SIGILL; | |
1763 | ||
1da177e4 LT |
1764 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
1765 | return 0; | |
1766 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1767 | break; | |
1da177e4 LT |
1768 | case fabs_op: |
1769 | handler.u = ieee754dp_abs; | |
1770 | goto dcopuop; | |
1771 | ||
1772 | case fneg_op: | |
1773 | handler.u = ieee754dp_neg; | |
1774 | goto dcopuop; | |
1775 | ||
1776 | case fmov_op: | |
1777 | /* an easy one */ | |
1778 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1779 | goto copcsr; | |
1780 | ||
1781 | /* binary op on handler */ | |
3f7cac41 RB |
1782 | dcopbop: |
1783 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1784 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1da177e4 | 1785 | |
3f7cac41 RB |
1786 | rv.d = (*handler.b) (fs, ft); |
1787 | goto copcsr; | |
1788 | dcopuop: | |
1789 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1790 | rv.d = (*handler.u) (fs); | |
1791 | goto copcsr; | |
1da177e4 | 1792 | |
3f7cac41 RB |
1793 | /* |
1794 | * unary conv ops | |
1795 | */ | |
1796 | case fcvts_op: | |
1da177e4 LT |
1797 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1798 | rv.s = ieee754sp_fdp(fs); | |
1799 | rfmt = s_fmt; | |
1800 | goto copcsr; | |
3f7cac41 | 1801 | |
1da177e4 LT |
1802 | case fcvtd_op: |
1803 | return SIGILL; /* not defined */ | |
1804 | ||
3f7cac41 | 1805 | case fcvtw_op: |
1da177e4 LT |
1806 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1807 | rv.w = ieee754dp_tint(fs); /* wrong */ | |
1808 | rfmt = w_fmt; | |
1809 | goto copcsr; | |
1da177e4 | 1810 | |
1da177e4 LT |
1811 | case fround_op: |
1812 | case ftrunc_op: | |
1813 | case fceil_op: | |
3f7cac41 | 1814 | case ffloor_op: |
08a07904 RB |
1815 | if (!cpu_has_mips_2_3_4_5_r) |
1816 | return SIGILL; | |
1817 | ||
3f7cac41 | 1818 | oldrm = ieee754_csr.rm; |
1da177e4 | 1819 | DPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1820 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1821 | rv.w = ieee754dp_tint(fs); |
1822 | ieee754_csr.rm = oldrm; | |
1823 | rfmt = w_fmt; | |
1824 | goto copcsr; | |
1da177e4 | 1825 | |
3f7cac41 | 1826 | case fcvtl_op: |
08a07904 RB |
1827 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1828 | return SIGILL; | |
1829 | ||
1da177e4 LT |
1830 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1831 | rv.l = ieee754dp_tlong(fs); | |
1832 | rfmt = l_fmt; | |
1833 | goto copcsr; | |
1da177e4 LT |
1834 | |
1835 | case froundl_op: | |
1836 | case ftruncl_op: | |
1837 | case fceill_op: | |
3f7cac41 | 1838 | case ffloorl_op: |
08a07904 RB |
1839 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1840 | return SIGILL; | |
1841 | ||
3f7cac41 | 1842 | oldrm = ieee754_csr.rm; |
1da177e4 | 1843 | DPFROMREG(fs, MIPSInst_FS(ir)); |
56a64733 | 1844 | ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); |
1da177e4 LT |
1845 | rv.l = ieee754dp_tlong(fs); |
1846 | ieee754_csr.rm = oldrm; | |
1847 | rfmt = l_fmt; | |
1848 | goto copcsr; | |
1da177e4 LT |
1849 | |
1850 | default: | |
1851 | if (MIPSInst_FUNC(ir) >= fcmp_op) { | |
1852 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; | |
2209bcb1 | 1853 | union ieee754dp fs, ft; |
1da177e4 LT |
1854 | |
1855 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1856 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1857 | rv.w = ieee754dp_cmp(fs, ft, | |
1858 | cmptab[cmpop & 0x7], cmpop & 0x8); | |
1859 | rfmt = -1; | |
1860 | if ((cmpop & 0x8) | |
1861 | && | |
1862 | ieee754_cxtest | |
1863 | (IEEE754_INVALID_OPERATION)) | |
1864 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1865 | else | |
1866 | goto copcsr; | |
1867 | ||
1868 | } | |
1869 | else { | |
1870 | return SIGILL; | |
1871 | } | |
1872 | break; | |
1873 | } | |
1874 | break; | |
1da177e4 | 1875 | |
3f7cac41 | 1876 | case w_fmt: |
1da177e4 LT |
1877 | switch (MIPSInst_FUNC(ir)) { |
1878 | case fcvts_op: | |
1879 | /* convert word to single precision real */ | |
1880 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1881 | rv.s = ieee754sp_fint(fs.bits); | |
1882 | rfmt = s_fmt; | |
1883 | goto copcsr; | |
1da177e4 LT |
1884 | case fcvtd_op: |
1885 | /* convert word to double precision real */ | |
1886 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1887 | rv.d = ieee754dp_fint(fs.bits); | |
1888 | rfmt = d_fmt; | |
1889 | goto copcsr; | |
1da177e4 LT |
1890 | default: |
1891 | return SIGILL; | |
1892 | } | |
1893 | break; | |
1894 | } | |
1895 | ||
3f7cac41 | 1896 | case l_fmt: |
08a07904 RB |
1897 | |
1898 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) | |
1899 | return SIGILL; | |
1900 | ||
bbd426f5 PB |
1901 | DIFROMREG(bits, MIPSInst_FS(ir)); |
1902 | ||
1da177e4 LT |
1903 | switch (MIPSInst_FUNC(ir)) { |
1904 | case fcvts_op: | |
1905 | /* convert long to single precision real */ | |
bbd426f5 | 1906 | rv.s = ieee754sp_flong(bits); |
1da177e4 LT |
1907 | rfmt = s_fmt; |
1908 | goto copcsr; | |
1909 | case fcvtd_op: | |
1910 | /* convert long to double precision real */ | |
bbd426f5 | 1911 | rv.d = ieee754dp_flong(bits); |
1da177e4 LT |
1912 | rfmt = d_fmt; |
1913 | goto copcsr; | |
1914 | default: | |
1915 | return SIGILL; | |
1916 | } | |
1917 | break; | |
1da177e4 LT |
1918 | |
1919 | default: | |
1920 | return SIGILL; | |
1921 | } | |
1922 | ||
1923 | /* | |
1924 | * Update the fpu CSR register for this operation. | |
1925 | * If an exception is required, generate a tidy SIGFPE exception, | |
1926 | * without updating the result register. | |
1927 | * Note: cause exception bits do not accumulate, they are rewritten | |
1928 | * for each op; only the flag/sticky bits accumulate. | |
1929 | */ | |
1930 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; | |
1931 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { | |
3f7cac41 | 1932 | /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ |
1da177e4 LT |
1933 | return SIGFPE; |
1934 | } | |
1935 | ||
1936 | /* | |
1937 | * Now we can safely write the result back to the register file. | |
1938 | */ | |
1939 | switch (rfmt) { | |
08a07904 RB |
1940 | case -1: |
1941 | ||
1942 | if (cpu_has_mips_4_5_r) | |
c3b9b945 | 1943 | cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; |
08a07904 RB |
1944 | else |
1945 | cbit = FPU_CSR_COND; | |
1da177e4 | 1946 | if (rv.w) |
08a07904 | 1947 | ctx->fcr31 |= cbit; |
1da177e4 | 1948 | else |
08a07904 | 1949 | ctx->fcr31 &= ~cbit; |
1da177e4 | 1950 | break; |
08a07904 | 1951 | |
1da177e4 LT |
1952 | case d_fmt: |
1953 | DPTOREG(rv.d, MIPSInst_FD(ir)); | |
1954 | break; | |
1da177e4 LT |
1955 | case s_fmt: |
1956 | SPTOREG(rv.s, MIPSInst_FD(ir)); | |
1957 | break; | |
1958 | case w_fmt: | |
1959 | SITOREG(rv.w, MIPSInst_FD(ir)); | |
1960 | break; | |
1da177e4 | 1961 | case l_fmt: |
08a07904 RB |
1962 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1963 | return SIGILL; | |
1964 | ||
1da177e4 LT |
1965 | DITOREG(rv.l, MIPSInst_FD(ir)); |
1966 | break; | |
1da177e4 LT |
1967 | default: |
1968 | return SIGILL; | |
1969 | } | |
1970 | ||
1971 | return 0; | |
1972 | } | |
1973 | ||
e04582b7 | 1974 | int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
515b029d | 1975 | int has_fpu, void *__user *fault_addr) |
1da177e4 | 1976 | { |
333d1f67 | 1977 | unsigned long oldepc, prevepc; |
102cedc3 LY |
1978 | struct mm_decoded_insn dec_insn; |
1979 | u16 instr[4]; | |
1980 | u16 *instr_ptr; | |
1da177e4 LT |
1981 | int sig = 0; |
1982 | ||
1983 | oldepc = xcp->cp0_epc; | |
1984 | do { | |
1985 | prevepc = xcp->cp0_epc; | |
1986 | ||
102cedc3 LY |
1987 | if (get_isa16_mode(prevepc) && cpu_has_mmips) { |
1988 | /* | |
1989 | * Get next 2 microMIPS instructions and convert them | |
1990 | * into 32-bit instructions. | |
1991 | */ | |
1992 | if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || | |
1993 | (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || | |
1994 | (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || | |
1995 | (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { | |
1996 | MIPS_FPU_EMU_INC_STATS(errors); | |
1997 | return SIGBUS; | |
1998 | } | |
1999 | instr_ptr = instr; | |
2000 | ||
2001 | /* Get first instruction. */ | |
2002 | if (mm_insn_16bit(*instr_ptr)) { | |
2003 | /* Duplicate the half-word. */ | |
2004 | dec_insn.insn = (*instr_ptr << 16) | | |
2005 | (*instr_ptr); | |
2006 | /* 16-bit instruction. */ | |
2007 | dec_insn.pc_inc = 2; | |
2008 | instr_ptr += 1; | |
2009 | } else { | |
2010 | dec_insn.insn = (*instr_ptr << 16) | | |
2011 | *(instr_ptr+1); | |
2012 | /* 32-bit instruction. */ | |
2013 | dec_insn.pc_inc = 4; | |
2014 | instr_ptr += 2; | |
2015 | } | |
2016 | /* Get second instruction. */ | |
2017 | if (mm_insn_16bit(*instr_ptr)) { | |
2018 | /* Duplicate the half-word. */ | |
2019 | dec_insn.next_insn = (*instr_ptr << 16) | | |
2020 | (*instr_ptr); | |
2021 | /* 16-bit instruction. */ | |
2022 | dec_insn.next_pc_inc = 2; | |
2023 | } else { | |
2024 | dec_insn.next_insn = (*instr_ptr << 16) | | |
2025 | *(instr_ptr+1); | |
2026 | /* 32-bit instruction. */ | |
2027 | dec_insn.next_pc_inc = 4; | |
2028 | } | |
2029 | dec_insn.micro_mips_mode = 1; | |
2030 | } else { | |
2031 | if ((get_user(dec_insn.insn, | |
2032 | (mips_instruction __user *) xcp->cp0_epc)) || | |
2033 | (get_user(dec_insn.next_insn, | |
2034 | (mips_instruction __user *)(xcp->cp0_epc+4)))) { | |
2035 | MIPS_FPU_EMU_INC_STATS(errors); | |
2036 | return SIGBUS; | |
2037 | } | |
2038 | dec_insn.pc_inc = 4; | |
2039 | dec_insn.next_pc_inc = 4; | |
2040 | dec_insn.micro_mips_mode = 0; | |
515b029d | 2041 | } |
102cedc3 LY |
2042 | |
2043 | if ((dec_insn.insn == 0) || | |
2044 | ((dec_insn.pc_inc == 2) && | |
2045 | ((dec_insn.insn & 0xffff) == MM_NOP16))) | |
2046 | xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ | |
1da177e4 | 2047 | else { |
cd21dfcf RB |
2048 | /* |
2049 | * The 'ieee754_csr' is an alias of | |
70342287 RB |
2050 | * ctx->fcr31. No need to copy ctx->fcr31 to |
2051 | * ieee754_csr. But ieee754_csr.rm is ieee | |
cd21dfcf RB |
2052 | * library modes. (not mips rounding mode) |
2053 | */ | |
102cedc3 | 2054 | sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); |
1da177e4 LT |
2055 | } |
2056 | ||
e04582b7 | 2057 | if (has_fpu) |
1da177e4 LT |
2058 | break; |
2059 | if (sig) | |
2060 | break; | |
2061 | ||
2062 | cond_resched(); | |
2063 | } while (xcp->cp0_epc > prevepc); | |
2064 | ||
2065 | /* SIGILL indicates a non-fpu instruction */ | |
2066 | if (sig == SIGILL && xcp->cp0_epc != oldepc) | |
3f7cac41 | 2067 | /* but if EPC has advanced, then ignore it */ |
1da177e4 LT |
2068 | sig = 0; |
2069 | ||
2070 | return sig; | |
2071 | } |