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1da177e4 LT |
1 | /* |
2 | * Carsten Langgaard, carstenl@mips.com | |
3 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can distribute it and/or modify it | |
6 | * under the terms of the GNU General Public License (Version 2) as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
17 | * | |
18 | * Setting up the clock on the MIPS boards. | |
19 | */ | |
20 | ||
21 | #include <linux/types.h> | |
1da177e4 LT |
22 | #include <linux/init.h> |
23 | #include <linux/kernel_stat.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/time.h> | |
28 | #include <linux/timex.h> | |
29 | #include <linux/mc146818rtc.h> | |
30 | ||
31 | #include <asm/mipsregs.h> | |
41c594ab | 32 | #include <asm/mipsmtregs.h> |
e01402b1 RB |
33 | #include <asm/hardirq.h> |
34 | #include <asm/irq.h> | |
1da177e4 LT |
35 | #include <asm/div64.h> |
36 | #include <asm/cpu.h> | |
37 | #include <asm/time.h> | |
38 | #include <asm/mc146818-time.h> | |
e01402b1 | 39 | #include <asm/msc01_ic.h> |
1da177e4 LT |
40 | |
41 | #include <asm/mips-boards/generic.h> | |
42 | #include <asm/mips-boards/prom.h> | |
fc095a90 MR |
43 | |
44 | #ifdef CONFIG_MIPS_ATLAS | |
45 | #include <asm/mips-boards/atlasint.h> | |
46 | #endif | |
47 | #ifdef CONFIG_MIPS_MALTA | |
e01402b1 | 48 | #include <asm/mips-boards/maltaint.h> |
fc095a90 | 49 | #endif |
1da177e4 LT |
50 | |
51 | unsigned long cpu_khz; | |
52 | ||
1da177e4 LT |
53 | #if defined(CONFIG_MIPS_ATLAS) |
54 | static char display_string[] = " LINUX ON ATLAS "; | |
55 | #endif | |
56 | #if defined(CONFIG_MIPS_MALTA) | |
41c594ab RB |
57 | #if defined(CONFIG_MIPS_MT_SMTC) |
58 | static char display_string[] = " SMTC LINUX ON MALTA "; | |
59 | #else | |
1da177e4 | 60 | static char display_string[] = " LINUX ON MALTA "; |
41c594ab | 61 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 LT |
62 | #endif |
63 | #if defined(CONFIG_MIPS_SEAD) | |
64 | static char display_string[] = " LINUX ON SEAD "; | |
65 | #endif | |
41c594ab | 66 | static unsigned int display_count; |
1da177e4 LT |
67 | #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8) |
68 | ||
41c594ab RB |
69 | #define CPUCTR_IMASKBIT (0x100 << MIPSCPU_INT_CPUCTR) |
70 | ||
71 | static unsigned int timer_tick_count; | |
e01402b1 | 72 | static int mips_cpu_timer_irq; |
41c594ab | 73 | extern void smtc_timer_broadcast(int); |
1da177e4 | 74 | |
340ee4b9 RB |
75 | static inline void scroll_display_message(void) |
76 | { | |
77 | if ((timer_tick_count++ % HZ) == 0) { | |
78 | mips_display_message(&display_string[display_count++]); | |
79 | if (display_count == MAX_DISPLAY_COUNT) | |
80 | display_count = 0; | |
81 | } | |
82 | } | |
83 | ||
937a8015 | 84 | static void mips_timer_dispatch(void) |
1da177e4 | 85 | { |
937a8015 | 86 | do_IRQ(mips_cpu_timer_irq); |
e01402b1 RB |
87 | } |
88 | ||
41c594ab RB |
89 | /* |
90 | * Redeclare until I get around mopping the timer code insanity on MIPS. | |
91 | */ | |
937a8015 | 92 | extern int null_perf_irq(void); |
ba339c03 | 93 | |
937a8015 | 94 | extern int (*perf_irq)(void); |
ba339c03 | 95 | |
937a8015 | 96 | irqreturn_t mips_timer_interrupt(int irq, void *dev_id) |
e01402b1 | 97 | { |
340ee4b9 | 98 | int cpu = smp_processor_id(); |
41c594ab RB |
99 | |
100 | #ifdef CONFIG_MIPS_MT_SMTC | |
846acaa2 | 101 | /* |
41c594ab RB |
102 | * In an SMTC system, one Count/Compare set exists per VPE. |
103 | * Which TC within a VPE gets the interrupt is essentially | |
104 | * random - we only know that it shouldn't be one with | |
105 | * IXMT set. Whichever TC gets the interrupt needs to | |
106 | * send special interprocessor interrupts to the other | |
107 | * TCs to make sure that they schedule, etc. | |
108 | * | |
109 | * That code is specific to the SMTC kernel, not to | |
110 | * the a particular platform, so it's invoked from | |
111 | * the general MIPS timer_interrupt routine. | |
112 | */ | |
113 | ||
846acaa2 KK |
114 | int vpflags; |
115 | ||
41c594ab | 116 | /* |
846acaa2 KK |
117 | * We could be here due to timer interrupt, |
118 | * perf counter overflow, or both. | |
41c594ab | 119 | */ |
846acaa2 | 120 | if (read_c0_cause() & (1 << 26)) |
937a8015 | 121 | perf_irq(); |
340ee4b9 | 122 | |
846acaa2 KK |
123 | if (read_c0_cause() & (1 << 30)) { |
124 | /* If timer interrupt, make it de-assert */ | |
125 | write_c0_compare (read_c0_count() - 1); | |
41c594ab | 126 | /* |
846acaa2 KK |
127 | * DVPE is necessary so long as cross-VPE interrupts |
128 | * are done via read-modify-write of Cause register. | |
41c594ab | 129 | */ |
846acaa2 KK |
130 | vpflags = dvpe(); |
131 | clear_c0_cause(CPUCTR_IMASKBIT); | |
132 | evpe(vpflags); | |
133 | /* | |
134 | * There are things we only want to do once per tick | |
135 | * in an "MP" system. One TC of each VPE will take | |
136 | * the actual timer interrupt. The others will get | |
137 | * timer broadcast IPIs. We use whoever it is that takes | |
138 | * the tick on VPE 0 to run the full timer_interrupt(). | |
139 | */ | |
140 | if (cpu_data[cpu].vpe_id == 0) { | |
937a8015 | 141 | timer_interrupt(irq, NULL); |
846acaa2 KK |
142 | smtc_timer_broadcast(cpu_data[cpu].vpe_id); |
143 | scroll_display_message(); | |
144 | } else { | |
145 | write_c0_compare(read_c0_count() + | |
146 | (mips_hpt_frequency/HZ)); | |
937a8015 | 147 | local_timer_interrupt(irq, dev_id); |
846acaa2 KK |
148 | smtc_timer_broadcast(cpu_data[cpu].vpe_id); |
149 | } | |
150 | } | |
41c594ab | 151 | #else /* CONFIG_MIPS_MT_SMTC */ |
846acaa2 KK |
152 | int r2 = cpu_has_mips_r2; |
153 | ||
340ee4b9 RB |
154 | if (cpu == 0) { |
155 | /* | |
ba339c03 RB |
156 | * CPU 0 handles the global timer interrupt job and process |
157 | * accounting resets count/compare registers to trigger next | |
158 | * timer int. | |
340ee4b9 | 159 | */ |
ba339c03 | 160 | if (!r2 || (read_c0_cause() & (1 << 26))) |
937a8015 | 161 | if (perf_irq()) |
ba339c03 RB |
162 | goto out; |
163 | ||
164 | /* we keep interrupt disabled all the time */ | |
165 | if (!r2 || (read_c0_cause() & (1 << 30))) | |
937a8015 | 166 | timer_interrupt(irq, NULL); |
ba339c03 | 167 | |
340ee4b9 | 168 | scroll_display_message(); |
11e6df65 | 169 | } else { |
340ee4b9 RB |
170 | /* Everyone else needs to reset the timer int here as |
171 | ll_local_timer_interrupt doesn't */ | |
172 | /* | |
173 | * FIXME: need to cope with counter underflow. | |
174 | * More support needs to be added to kernel/time for | |
175 | * counter/timer interrupts on multiple CPU's | |
176 | */ | |
41c594ab RB |
177 | write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); |
178 | ||
340ee4b9 | 179 | /* |
41c594ab | 180 | * Other CPUs should do profiling and process accounting |
340ee4b9 | 181 | */ |
937a8015 | 182 | local_timer_interrupt(irq, dev_id); |
340ee4b9 | 183 | } |
ba339c03 | 184 | out: |
846acaa2 | 185 | #endif /* CONFIG_MIPS_MT_SMTC */ |
340ee4b9 | 186 | return IRQ_HANDLED; |
1da177e4 LT |
187 | } |
188 | ||
189 | /* | |
224dc50e | 190 | * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect |
1da177e4 LT |
191 | */ |
192 | static unsigned int __init estimate_cpu_frequency(void) | |
193 | { | |
194 | unsigned int prid = read_c0_prid() & 0xffff00; | |
195 | unsigned int count; | |
196 | ||
41c594ab | 197 | #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM) |
1da177e4 LT |
198 | /* |
199 | * The SEAD board doesn't have a real time clock, so we can't | |
200 | * really calculate the timer frequency | |
201 | * For now we hardwire the SEAD board frequency to 12MHz. | |
202 | */ | |
42a3b4f2 | 203 | |
1da177e4 LT |
204 | if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || |
205 | (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) | |
206 | count = 12000000; | |
207 | else | |
208 | count = 6000000; | |
209 | #endif | |
210 | #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) | |
e79f55a8 | 211 | unsigned long flags; |
70e46f48 | 212 | unsigned int start; |
1da177e4 LT |
213 | |
214 | local_irq_save(flags); | |
215 | ||
216 | /* Start counter exactly on falling edge of update flag */ | |
217 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); | |
218 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
219 | ||
220 | /* Start r4k counter. */ | |
70e46f48 | 221 | start = read_c0_count(); |
1da177e4 LT |
222 | |
223 | /* Read counter exactly on falling edge of update flag */ | |
224 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); | |
225 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); | |
226 | ||
70e46f48 | 227 | count = read_c0_count() - start; |
1da177e4 LT |
228 | |
229 | /* restore interrupts */ | |
230 | local_irq_restore(flags); | |
231 | #endif | |
232 | ||
233 | mips_hpt_frequency = count; | |
234 | if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && | |
235 | (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) | |
236 | count *= 2; | |
237 | ||
238 | count += 5000; /* round */ | |
239 | count -= count%10000; | |
240 | ||
241 | return count; | |
242 | } | |
243 | ||
244 | unsigned long __init mips_rtc_get_time(void) | |
245 | { | |
246 | return mc146818_get_cmos_time(); | |
247 | } | |
248 | ||
249 | void __init mips_time_init(void) | |
250 | { | |
ece2246e | 251 | unsigned int est_freq; |
1da177e4 | 252 | |
1da177e4 LT |
253 | /* Set Data mode - binary. */ |
254 | CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); | |
1da177e4 LT |
255 | |
256 | est_freq = estimate_cpu_frequency (); | |
257 | ||
258 | printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, | |
259 | (est_freq%1000000)*100/1000000); | |
260 | ||
261 | cpu_khz = est_freq / 1000; | |
1da177e4 LT |
262 | } |
263 | ||
54d0a216 | 264 | void __init plat_timer_setup(struct irqaction *irq) |
1da177e4 | 265 | { |
e01402b1 RB |
266 | if (cpu_has_veic) { |
267 | set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); | |
268 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; | |
269 | } | |
270 | else { | |
271 | if (cpu_has_vint) | |
272 | set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch); | |
273 | mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR; | |
274 | } | |
275 | ||
276 | ||
1da177e4 | 277 | /* we are using the cpu counter for timer interrupts */ |
e01402b1 | 278 | irq->handler = mips_timer_interrupt; /* we use our own handler */ |
41c594ab RB |
279 | #ifdef CONFIG_MIPS_MT_SMTC |
280 | setup_irq_smtc(mips_cpu_timer_irq, irq, CPUCTR_IMASKBIT); | |
281 | #else | |
e01402b1 | 282 | setup_irq(mips_cpu_timer_irq, irq); |
41c594ab | 283 | #endif /* CONFIG_MIPS_MT_SMTC */ |
e01402b1 | 284 | |
340ee4b9 RB |
285 | #ifdef CONFIG_SMP |
286 | /* irq_desc(riptor) is a global resource, when the interrupt overlaps | |
287 | on seperate cpu's the first one tries to handle the second interrupt. | |
288 | The effect is that the int remains disabled on the second cpu. | |
289 | Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ | |
290 | irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; | |
1417836e | 291 | set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); |
340ee4b9 | 292 | #endif |
1da177e4 LT |
293 | |
294 | /* to generate the first timer interrupt */ | |
295 | write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); | |
1da177e4 | 296 | } |