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1da177e4 LT |
1 | /* |
2 | * Carsten Langgaard, carstenl@mips.com | |
3 | * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. | |
4 | * Copyright (C) 2001 Ralf Baechle | |
5 | * | |
6 | * This program is free software; you can distribute it and/or modify it | |
7 | * under the terms of the GNU General Public License (Version 2) as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
13 | * for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, write to the Free Software Foundation, Inc., | |
17 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
18 | * | |
19 | * Routines for generic manipulation of the interrupts found on the MIPS | |
20 | * Malta board. | |
21 | * The interrupt controller is located in the South Bridge a PIIX4 device | |
22 | * with two internal 82C95 interrupt controllers. | |
23 | */ | |
24 | #include <linux/init.h> | |
25 | #include <linux/irq.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/interrupt.h> | |
54bf038e | 29 | #include <linux/io.h> |
1da177e4 | 30 | #include <linux/kernel_stat.h> |
25b8ac3b | 31 | #include <linux/kernel.h> |
1da177e4 LT |
32 | #include <linux/random.h> |
33 | ||
34 | #include <asm/i8259.h> | |
e01402b1 | 35 | #include <asm/irq_cpu.h> |
ba38cdf9 | 36 | #include <asm/irq_regs.h> |
1da177e4 LT |
37 | #include <asm/mips-boards/malta.h> |
38 | #include <asm/mips-boards/maltaint.h> | |
39 | #include <asm/mips-boards/piix4.h> | |
40 | #include <asm/gt64120.h> | |
41 | #include <asm/mips-boards/generic.h> | |
42 | #include <asm/mips-boards/msc01_pci.h> | |
e01402b1 | 43 | #include <asm/msc01_ic.h> |
1da177e4 | 44 | |
1da177e4 LT |
45 | static DEFINE_SPINLOCK(mips_irq_lock); |
46 | ||
47 | static inline int mips_pcibios_iack(void) | |
48 | { | |
49 | int irq; | |
af825586 | 50 | u32 dummy; |
1da177e4 LT |
51 | |
52 | /* | |
53 | * Determine highest priority pending interrupt by performing | |
54 | * a PCI Interrupt Acknowledge cycle. | |
55 | */ | |
b72c0526 CD |
56 | switch (mips_revision_sconid) { |
57 | case MIPS_REVISION_SCON_SOCIT: | |
58 | case MIPS_REVISION_SCON_ROCIT: | |
59 | case MIPS_REVISION_SCON_SOCITSC: | |
60 | case MIPS_REVISION_SCON_SOCITSCP: | |
af825586 | 61 | MSC_READ(MSC01_PCI_IACK, irq); |
1da177e4 LT |
62 | irq &= 0xff; |
63 | break; | |
b72c0526 | 64 | case MIPS_REVISION_SCON_GT64120: |
1da177e4 LT |
65 | irq = GT_READ(GT_PCI0_IACK_OFS); |
66 | irq &= 0xff; | |
67 | break; | |
b72c0526 | 68 | case MIPS_REVISION_SCON_BONITO: |
1da177e4 LT |
69 | /* The following will generate a PCI IACK cycle on the |
70 | * Bonito controller. It's a little bit kludgy, but it | |
71 | * was the easiest way to implement it in hardware at | |
72 | * the given time. | |
73 | */ | |
74 | BONITO_PCIMAP_CFG = 0x20000; | |
75 | ||
76 | /* Flush Bonito register block */ | |
77 | dummy = BONITO_PCIMAP_CFG; | |
78 | iob(); /* sync */ | |
79 | ||
f1974653 | 80 | irq = readl((u32 *)_pcictrl_bonito_pcicfg); |
1da177e4 LT |
81 | iob(); /* sync */ |
82 | irq &= 0xff; | |
83 | BONITO_PCIMAP_CFG = 0; | |
84 | break; | |
85 | default: | |
8216d348 | 86 | printk(KERN_WARNING "Unknown system controller.\n"); |
1da177e4 LT |
87 | return -1; |
88 | } | |
89 | return irq; | |
90 | } | |
91 | ||
e01402b1 | 92 | static inline int get_int(void) |
1da177e4 LT |
93 | { |
94 | unsigned long flags; | |
e01402b1 | 95 | int irq; |
1da177e4 LT |
96 | spin_lock_irqsave(&mips_irq_lock, flags); |
97 | ||
e01402b1 | 98 | irq = mips_pcibios_iack(); |
1da177e4 LT |
99 | |
100 | /* | |
479a0e3e RB |
101 | * The only way we can decide if an interrupt is spurious |
102 | * is by checking the 8259 registers. This needs a spinlock | |
103 | * on an SMP system, so leave it up to the generic code... | |
1da177e4 | 104 | */ |
1da177e4 LT |
105 | |
106 | spin_unlock_irqrestore(&mips_irq_lock, flags); | |
107 | ||
e01402b1 | 108 | return irq; |
1da177e4 LT |
109 | } |
110 | ||
937a8015 | 111 | static void malta_hw0_irqdispatch(void) |
1da177e4 LT |
112 | { |
113 | int irq; | |
114 | ||
e01402b1 | 115 | irq = get_int(); |
41c594ab | 116 | if (irq < 0) { |
cd80d548 DV |
117 | /* interrupt has already been cleared */ |
118 | return; | |
41c594ab | 119 | } |
1da177e4 | 120 | |
937a8015 | 121 | do_IRQ(MALTA_INT_BASE + irq); |
1da177e4 LT |
122 | } |
123 | ||
937a8015 | 124 | static void corehi_irqdispatch(void) |
1da177e4 | 125 | { |
937a8015 | 126 | unsigned int intedge, intsteer, pcicmd, pcibadaddr; |
af825586 | 127 | unsigned int pcimstat, intisr, inten, intpol; |
21a151d8 | 128 | unsigned int intrcause, datalo, datahi; |
ba38cdf9 | 129 | struct pt_regs *regs = get_irq_regs(); |
1da177e4 | 130 | |
8216d348 DV |
131 | printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n"); |
132 | printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n" | |
af825586 DV |
133 | "Cause : %08lx\nbadVaddr : %08lx\n", |
134 | regs->cp0_epc, regs->cp0_status, | |
135 | regs->cp0_cause, regs->cp0_badvaddr); | |
e01402b1 RB |
136 | |
137 | /* Read all the registers and then print them as there is a | |
138 | problem with interspersed printk's upsetting the Bonito controller. | |
139 | Do it for the others too. | |
140 | */ | |
141 | ||
b72c0526 | 142 | switch (mips_revision_sconid) { |
af825586 | 143 | case MIPS_REVISION_SCON_SOCIT: |
b72c0526 CD |
144 | case MIPS_REVISION_SCON_ROCIT: |
145 | case MIPS_REVISION_SCON_SOCITSC: | |
146 | case MIPS_REVISION_SCON_SOCITSCP: | |
af825586 DV |
147 | ll_msc_irq(); |
148 | break; | |
149 | case MIPS_REVISION_SCON_GT64120: | |
150 | intrcause = GT_READ(GT_INTRCAUSE_OFS); | |
151 | datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); | |
152 | datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); | |
8216d348 DV |
153 | printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause); |
154 | printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n", | |
155 | datahi, datalo); | |
af825586 DV |
156 | break; |
157 | case MIPS_REVISION_SCON_BONITO: | |
158 | pcibadaddr = BONITO_PCIBADADDR; | |
159 | pcimstat = BONITO_PCIMSTAT; | |
160 | intisr = BONITO_INTISR; | |
161 | inten = BONITO_INTEN; | |
162 | intpol = BONITO_INTPOL; | |
163 | intedge = BONITO_INTEDGE; | |
164 | intsteer = BONITO_INTSTEER; | |
165 | pcicmd = BONITO_PCICMD; | |
8216d348 DV |
166 | printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr); |
167 | printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten); | |
168 | printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol); | |
169 | printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge); | |
170 | printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer); | |
171 | printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd); | |
172 | printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr); | |
173 | printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat); | |
af825586 DV |
174 | break; |
175 | } | |
1da177e4 | 176 | |
af825586 | 177 | die("CoreHi interrupt", regs); |
1da177e4 LT |
178 | } |
179 | ||
e4ac58af RB |
180 | static inline int clz(unsigned long x) |
181 | { | |
49a89efb | 182 | __asm__( |
e4ac58af RB |
183 | " .set push \n" |
184 | " .set mips32 \n" | |
185 | " clz %0, %1 \n" | |
186 | " .set pop \n" | |
187 | : "=r" (x) | |
188 | : "r" (x)); | |
189 | ||
190 | return x; | |
191 | } | |
192 | ||
193 | /* | |
194 | * Version of ffs that only looks at bits 12..15. | |
195 | */ | |
196 | static inline unsigned int irq_ffs(unsigned int pending) | |
197 | { | |
198 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) | |
199 | return -clz(pending) + 31 - CAUSEB_IP; | |
200 | #else | |
201 | unsigned int a0 = 7; | |
202 | unsigned int t0; | |
203 | ||
0118c3ca | 204 | t0 = pending & 0xf000; |
e4ac58af RB |
205 | t0 = t0 < 1; |
206 | t0 = t0 << 2; | |
207 | a0 = a0 - t0; | |
0118c3ca | 208 | pending = pending << t0; |
e4ac58af | 209 | |
0118c3ca | 210 | t0 = pending & 0xc000; |
e4ac58af RB |
211 | t0 = t0 < 1; |
212 | t0 = t0 << 1; | |
213 | a0 = a0 - t0; | |
0118c3ca | 214 | pending = pending << t0; |
e4ac58af | 215 | |
0118c3ca | 216 | t0 = pending & 0x8000; |
e4ac58af | 217 | t0 = t0 < 1; |
ae9cef0b | 218 | /* t0 = t0 << 2; */ |
e4ac58af | 219 | a0 = a0 - t0; |
ae9cef0b | 220 | /* pending = pending << t0; */ |
e4ac58af RB |
221 | |
222 | return a0; | |
223 | #endif | |
224 | } | |
225 | ||
226 | /* | |
227 | * IRQs on the Malta board look basically (barring software IRQs which we | |
228 | * don't use at all and all external interrupt sources are combined together | |
229 | * on hardware interrupt 0 (MIPS IRQ 2)) like: | |
230 | * | |
231 | * MIPS IRQ Source | |
232 | * -------- ------ | |
233 | * 0 Software (ignored) | |
234 | * 1 Software (ignored) | |
235 | * 2 Combined hardware interrupt (hw0) | |
236 | * 3 Hardware (ignored) | |
237 | * 4 Hardware (ignored) | |
238 | * 5 Hardware (ignored) | |
239 | * 6 Hardware (ignored) | |
240 | * 7 R4k timer (what we use) | |
241 | * | |
242 | * We handle the IRQ according to _our_ priority which is: | |
243 | * | |
244 | * Highest ---- R4k Timer | |
245 | * Lowest ---- Combined hardware interrupt | |
246 | * | |
247 | * then we just return, if multiple IRQs are pending then we will just take | |
248 | * another exception, big deal. | |
249 | */ | |
250 | ||
937a8015 | 251 | asmlinkage void plat_irq_dispatch(void) |
e4ac58af RB |
252 | { |
253 | unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; | |
254 | int irq; | |
255 | ||
256 | irq = irq_ffs(pending); | |
257 | ||
258 | if (irq == MIPSCPU_INT_I8259A) | |
937a8015 | 259 | malta_hw0_irqdispatch(); |
48d480b0 | 260 | else if (irq >= 0) |
3b1d4ed5 | 261 | do_IRQ(MIPS_CPU_IRQ_BASE + irq); |
e4ac58af | 262 | else |
937a8015 | 263 | spurious_interrupt(); |
e4ac58af RB |
264 | } |
265 | ||
e01402b1 RB |
266 | static struct irqaction i8259irq = { |
267 | .handler = no_action, | |
268 | .name = "XT-PIC cascade" | |
269 | }; | |
270 | ||
271 | static struct irqaction corehi_irqaction = { | |
272 | .handler = no_action, | |
273 | .name = "CoreHi" | |
274 | }; | |
275 | ||
276 | msc_irqmap_t __initdata msc_irqmap[] = { | |
277 | {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, | |
278 | {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, | |
279 | }; | |
25b8ac3b | 280 | int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap); |
e01402b1 RB |
281 | |
282 | msc_irqmap_t __initdata msc_eicirqmap[] = { | |
283 | {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, | |
284 | {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, | |
285 | {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, | |
286 | {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0}, | |
287 | {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0}, | |
288 | {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0}, | |
289 | {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, | |
290 | {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, | |
291 | {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, | |
292 | {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} | |
293 | }; | |
25b8ac3b | 294 | int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); |
e01402b1 | 295 | |
1da177e4 LT |
296 | void __init arch_init_irq(void) |
297 | { | |
1da177e4 | 298 | init_i8259_irqs(); |
e01402b1 RB |
299 | |
300 | if (!cpu_has_veic) | |
97dcb82d | 301 | mips_cpu_irq_init(); |
e01402b1 | 302 | |
af825586 DV |
303 | switch (mips_revision_sconid) { |
304 | case MIPS_REVISION_SCON_SOCIT: | |
305 | case MIPS_REVISION_SCON_ROCIT: | |
d725cf38 | 306 | if (cpu_has_veic) |
f8071496 DV |
307 | init_msc_irqs(MIPS_MSC01_IC_REG_BASE, |
308 | MSC01E_INT_BASE, msc_eicirqmap, | |
309 | msc_nr_eicirqs); | |
d725cf38 | 310 | else |
f8071496 DV |
311 | init_msc_irqs(MIPS_MSC01_IC_REG_BASE, |
312 | MSC01C_INT_BASE, msc_irqmap, | |
313 | msc_nr_irqs); | |
d725cf38 CD |
314 | break; |
315 | ||
af825586 DV |
316 | case MIPS_REVISION_SCON_SOCITSC: |
317 | case MIPS_REVISION_SCON_SOCITSCP: | |
e01402b1 | 318 | if (cpu_has_veic) |
f8071496 DV |
319 | init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, |
320 | MSC01E_INT_BASE, msc_eicirqmap, | |
321 | msc_nr_eicirqs); | |
e01402b1 | 322 | else |
f8071496 DV |
323 | init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, |
324 | MSC01C_INT_BASE, msc_irqmap, | |
325 | msc_nr_irqs); | |
e01402b1 RB |
326 | } |
327 | ||
328 | if (cpu_has_veic) { | |
49a89efb RB |
329 | set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch); |
330 | set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); | |
331 | setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); | |
332 | setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); | |
52b3fc04 | 333 | } else if (cpu_has_vint) { |
49a89efb RB |
334 | set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); |
335 | set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch); | |
41c594ab | 336 | #ifdef CONFIG_MIPS_MT_SMTC |
49a89efb | 337 | setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, |
41c594ab | 338 | (0x100 << MIPSCPU_INT_I8259A)); |
49a89efb | 339 | setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, |
41c594ab | 340 | &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); |
c3a005f4 KK |
341 | /* |
342 | * Temporary hack to ensure that the subsidiary device | |
343 | * interrupts coing in via the i8259A, but associated | |
344 | * with low IRQ numbers, will restore the Status.IM | |
345 | * value associated with the i8259A. | |
346 | */ | |
347 | { | |
348 | int i; | |
349 | ||
350 | for (i = 0; i < 16; i++) | |
351 | irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); | |
352 | } | |
41c594ab | 353 | #else /* Not SMTC */ |
49a89efb | 354 | setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); |
f8071496 DV |
355 | setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, |
356 | &corehi_irqaction); | |
41c594ab | 357 | #endif /* CONFIG_MIPS_MT_SMTC */ |
52b3fc04 | 358 | } else { |
49a89efb | 359 | setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); |
f8071496 DV |
360 | setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, |
361 | &corehi_irqaction); | |
e01402b1 | 362 | } |
1da177e4 | 363 | } |