[mirror_ubuntu-zesty-kernel.git] / arch / mips / mips-boards / malta / malta_int.c

/*
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
 * Copyright (C) 2001 Ralf Baechle
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * Routines for generic manipulation of the interrupts found on the MIPS
 * Malta board.
 * The interrupt controller is located in the South Bridge a PIIX4 device
 * with two internal 82C95 interrupt controllers.
 */
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/random.h>

#include <asm/i8259.h>
#include <asm/irq_cpu.h>
#include <asm/io.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/mips-boards/piix4.h>
#include <asm/gt64120.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/msc01_pci.h>
#include <asm/msc01_ic.h>

extern asmlinkage void mipsIRQ(void);
extern void mips_timer_interrupt(void);

static DEFINE_SPINLOCK(mips_irq_lock);

static inline int mips_pcibios_iack(void)
{
	int irq;
        u32 dummy;

	/*
	 * Determine highest priority pending interrupt by performing
	 * a PCI Interrupt Acknowledge cycle.
	 */
	switch(mips_revision_corid) {
	case MIPS_REVISION_CORID_CORE_MSC:
	case MIPS_REVISION_CORID_CORE_FPGA2:
	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	        MSC_READ(MSC01_PCI_IACK, irq);
		irq &= 0xff;
		break;
	case MIPS_REVISION_CORID_QED_RM5261:
	case MIPS_REVISION_CORID_CORE_LV:
	case MIPS_REVISION_CORID_CORE_FPGA:
	case MIPS_REVISION_CORID_CORE_FPGAR2:
		irq = GT_READ(GT_PCI0_IACK_OFS);
		irq &= 0xff;
		break;
	case MIPS_REVISION_CORID_BONITO64:
	case MIPS_REVISION_CORID_CORE_20K:
	case MIPS_REVISION_CORID_CORE_EMUL_BON:
		/* The following will generate a PCI IACK cycle on the
		 * Bonito controller. It's a little bit kludgy, but it
		 * was the easiest way to implement it in hardware at
		 * the given time.
		 */
		BONITO_PCIMAP_CFG = 0x20000;

		/* Flush Bonito register block */
		dummy = BONITO_PCIMAP_CFG;
		iob();    /* sync */

		irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg);
		iob();    /* sync */
		irq &= 0xff;
		BONITO_PCIMAP_CFG = 0;
		break;
	default:
	        printk("Unknown Core card, don't know the system controller.\n");
		return -1;
	}
	return irq;
}

static inline int get_int(void)
{
	unsigned long flags;
	int irq;
	spin_lock_irqsave(&mips_irq_lock, flags);

	irq = mips_pcibios_iack();

	/*
	 * IRQ7 is used to detect spurious interrupts.
	 * The interrupt acknowledge cycle returns IRQ7, if no
	 * interrupts is requested.
	 * We can differentiate between this situation and a
	 * "Normal" IRQ7 by reading the ISR.
	 */
	if (irq == 7)
	{
		outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR,
		     PIIX4_ICTLR1_OCW3);
		if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) {
			irq = -1; /* Spurious interrupt */
			printk("We got a spurious interrupt from PIIX4.\n");
			atomic_inc(&irq_err_count);
		}
	}

	spin_unlock_irqrestore(&mips_irq_lock, flags);

	return irq;
}

void malta_hw0_irqdispatch(struct pt_regs *regs)
{
	int irq;

	irq = get_int();
	if (irq < 0)
		return;  /* interrupt has already been cleared */

	do_IRQ(MALTA_INT_BASE+irq, regs);
}

void corehi_irqdispatch(struct pt_regs *regs)
{
	unsigned int intrcause,datalo,datahi;
        unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr;

        printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
        printk("epc   : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);

	/* Read all the registers and then print them as there is a
	   problem with interspersed printk's upsetting the Bonito controller.
	   Do it for the others too.
	*/

        switch(mips_revision_corid) {
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                ll_msc_irq(regs);
                break;
        case MIPS_REVISION_CORID_QED_RM5261:
        case MIPS_REVISION_CORID_CORE_LV:
        case MIPS_REVISION_CORID_CORE_FPGA:
        case MIPS_REVISION_CORID_CORE_FPGAR2:
                intrcause = GT_READ(GT_INTRCAUSE_OFS);
                datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
                datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
                printk("GT_INTRCAUSE = %08x\n", intrcause);
                printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
                break;
        case MIPS_REVISION_CORID_BONITO64:
        case MIPS_REVISION_CORID_CORE_20K:
        case MIPS_REVISION_CORID_CORE_EMUL_BON:
                pcibadaddr = BONITO_PCIBADADDR;
                pcimstat = BONITO_PCIMSTAT;
                intisr = BONITO_INTISR;
                inten = BONITO_INTEN;
                intpol = BONITO_INTPOL;
                intedge = BONITO_INTEDGE;
                intsteer = BONITO_INTSTEER;
                pcicmd = BONITO_PCICMD;
                printk("BONITO_INTISR = %08x\n", intisr);
                printk("BONITO_INTEN = %08x\n", inten);
                printk("BONITO_INTPOL = %08x\n", intpol);
                printk("BONITO_INTEDGE = %08x\n", intedge);
                printk("BONITO_INTSTEER = %08x\n", intsteer);
                printk("BONITO_PCICMD = %08x\n", pcicmd);
                printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
                printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
                break;
        }

        /* We die here*/
        die("CoreHi interrupt", regs);
}

static struct irqaction i8259irq = {
	.handler = no_action,
	.name = "XT-PIC cascade"
};

static struct irqaction corehi_irqaction = {
	.handler = no_action,
	.name = "CoreHi"
};

msc_irqmap_t __initdata msc_irqmap[] = {
	{MSC01C_INT_TMR,		MSC01_IRQ_EDGE, 0},
	{MSC01C_INT_PCI,		MSC01_IRQ_LEVEL, 0},
};
int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t);

msc_irqmap_t __initdata msc_eicirqmap[] = {
	{MSC01E_INT_SW0,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_SW1,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_I8259A,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_SMI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_COREHI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_CORELO,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_TMR,		MSC01_IRQ_EDGE, 0},
	{MSC01E_INT_PCI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_PERFCTR,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_CPUCTR,		MSC01_IRQ_LEVEL, 0}
};
int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);

void __init arch_init_irq(void)
{
	set_except_vector(0, mipsIRQ);
	init_i8259_irqs();

	if (!cpu_has_veic)
		mips_cpu_irq_init (MIPSCPU_INT_BASE);

        switch(mips_revision_corid) {
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
		if (cpu_has_veic)
			init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
		else
			init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
	}

	if (cpu_has_veic) {
		set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
		set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
		setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
		setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
	}
	else if (cpu_has_vint) {
		set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
		set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);

		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
	}
	else {
		set_except_vector(0, mipsIRQ);
		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
		setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Carsten Langgaard, carstenl@mips.com
	3	* Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
	4	* Copyright (C) 2001 Ralf Baechle
	5	*
	6	* This program is free software; you can distribute it and/or modify it
	7	* under the terms of the GNU General Public License (Version 2) as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	* for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along
	16	* with this program; if not, write to the Free Software Foundation, Inc.,
	17	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	18	*
	19	* Routines for generic manipulation of the interrupts found on the MIPS
	20	* Malta board.
	21	* The interrupt controller is located in the South Bridge a PIIX4 device
	22	* with two internal 82C95 interrupt controllers.
	23	*/
	24	#include <linux/init.h>
	25	#include <linux/irq.h>
	26	#include <linux/sched.h>
	27	#include <linux/slab.h>
	28	#include <linux/interrupt.h>
	29	#include <linux/kernel_stat.h>
	30	#include <linux/random.h>
	31
	32	#include <asm/i8259.h>
e01402b1	33	#include <asm/irq_cpu.h>
1da177e4 LT	34	#include <asm/io.h>
	35	#include <asm/mips-boards/malta.h>
	36	#include <asm/mips-boards/maltaint.h>
	37	#include <asm/mips-boards/piix4.h>
	38	#include <asm/gt64120.h>
	39	#include <asm/mips-boards/generic.h>
	40	#include <asm/mips-boards/msc01_pci.h>
e01402b1	41	#include <asm/msc01_ic.h>
1da177e4 LT	42
1da177e4 LT	43	extern asmlinkage void mipsIRQ(void);
e01402b1	44	extern void mips_timer_interrupt(void);
1da177e4 LT	45
	46	static DEFINE_SPINLOCK(mips_irq_lock);
	47
	48	static inline int mips_pcibios_iack(void)
	49	{
	50	int irq;
	51	u32 dummy;
	52
	53	/*
	54	* Determine highest priority pending interrupt by performing
	55	* a PCI Interrupt Acknowledge cycle.
	56	*/
	57	switch(mips_revision_corid) {
	58	case MIPS_REVISION_CORID_CORE_MSC:
	59	case MIPS_REVISION_CORID_CORE_FPGA2:
	60	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	61	MSC_READ(MSC01_PCI_IACK, irq);
	62	irq &= 0xff;
	63	break;
	64	case MIPS_REVISION_CORID_QED_RM5261:
	65	case MIPS_REVISION_CORID_CORE_LV:
	66	case MIPS_REVISION_CORID_CORE_FPGA:
	67	case MIPS_REVISION_CORID_CORE_FPGAR2:
	68	irq = GT_READ(GT_PCI0_IACK_OFS);
	69	irq &= 0xff;
	70	break;
	71	case MIPS_REVISION_CORID_BONITO64:
	72	case MIPS_REVISION_CORID_CORE_20K:
	73	case MIPS_REVISION_CORID_CORE_EMUL_BON:
	74	/* The following will generate a PCI IACK cycle on the
	75	* Bonito controller. It's a little bit kludgy, but it
	76	* was the easiest way to implement it in hardware at
	77	* the given time.
	78	*/
	79	BONITO_PCIMAP_CFG = 0x20000;
	80
	81	/* Flush Bonito register block */
	82	dummy = BONITO_PCIMAP_CFG;
	83	iob(); /* sync */
	84
	85	irq = (volatile u32 )(_pcictrl_bonito_pcicfg);
	86	iob(); /* sync */
	87	irq &= 0xff;
	88	BONITO_PCIMAP_CFG = 0;
	89	break;
	90	default:
	91	printk("Unknown Core card, don't know the system controller.\n");
	92	return -1;
	93	}
	94	return irq;
	95	}
	96
e01402b1	97	static inline int get_int(void)
1da177e4 LT	98	{
1da177e4 LT	99	unsigned long flags;
e01402b1	100	int irq;
1da177e4 LT	101	spin_lock_irqsave(&mips_irq_lock, flags);
1da177e4 LT	102
e01402b1	103	irq = mips_pcibios_iack();
1da177e4 LT	104
	105	/*
	106	* IRQ7 is used to detect spurious interrupts.
	107	* The interrupt acknowledge cycle returns IRQ7, if no
	108	* interrupts is requested.
	109	* We can differentiate between this situation and a
	110	* "Normal" IRQ7 by reading the ISR.
	111	*/
e01402b1	112	if (irq == 7)
1da177e4 LT	113	{
	114	outb(PIIX4_OCW3_SEL \| PIIX4_OCW3_ISR,
	115	PIIX4_ICTLR1_OCW3);
	116	if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) {
e01402b1	117	irq = -1; /* Spurious interrupt */
1da177e4 LT	118	printk("We got a spurious interrupt from PIIX4.\n");
1da177e4 LT	119	atomic_inc(&irq_err_count);
1da177e4 LT	120	}
	121	}
	122
	123	spin_unlock_irqrestore(&mips_irq_lock, flags);
	124
e01402b1	125	return irq;
1da177e4 LT	126	}
	127
	128	void malta_hw0_irqdispatch(struct pt_regs *regs)
	129	{
	130	int irq;
	131
e01402b1 RB	132	irq = get_int();
	133	if (irq < 0)
	134	return; /* interrupt has already been cleared */
1da177e4	135
e01402b1	136	do_IRQ(MALTA_INT_BASE+irq, regs);
1da177e4 LT	137	}
	138
	139	void corehi_irqdispatch(struct pt_regs *regs)
	140	{
e01402b1 RB	141	unsigned int intrcause,datalo,datahi;
e01402b1 RB	142	unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr;
1da177e4 LT	143
	144	printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
	145	printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
	146	, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
e01402b1 RB	147
	148	/* Read all the registers and then print them as there is a
	149	problem with interspersed printk's upsetting the Bonito controller.
	150	Do it for the others too.
	151	*/
	152
1da177e4 LT	153	switch(mips_revision_corid) {
	154	case MIPS_REVISION_CORID_CORE_MSC:
	155	case MIPS_REVISION_CORID_CORE_FPGA2:
e01402b1 RB	156	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
e01402b1 RB	157	ll_msc_irq(regs);
1da177e4 LT	158	break;
	159	case MIPS_REVISION_CORID_QED_RM5261:
	160	case MIPS_REVISION_CORID_CORE_LV:
	161	case MIPS_REVISION_CORID_CORE_FPGA:
	162	case MIPS_REVISION_CORID_CORE_FPGAR2:
e01402b1 RB	163	intrcause = GT_READ(GT_INTRCAUSE_OFS);
e01402b1 RB	164	datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
1da177e4	165	datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
e01402b1 RB	166	printk("GT_INTRCAUSE = %08x\n", intrcause);
e01402b1 RB	167	printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
1da177e4 LT	168	break;
	169	case MIPS_REVISION_CORID_BONITO64:
	170	case MIPS_REVISION_CORID_CORE_20K:
	171	case MIPS_REVISION_CORID_CORE_EMUL_BON:
e01402b1 RB	172	pcibadaddr = BONITO_PCIBADADDR;
	173	pcimstat = BONITO_PCIMSTAT;
	174	intisr = BONITO_INTISR;
	175	inten = BONITO_INTEN;
	176	intpol = BONITO_INTPOL;
	177	intedge = BONITO_INTEDGE;
	178	intsteer = BONITO_INTSTEER;
	179	pcicmd = BONITO_PCICMD;
	180	printk("BONITO_INTISR = %08x\n", intisr);
	181	printk("BONITO_INTEN = %08x\n", inten);
	182	printk("BONITO_INTPOL = %08x\n", intpol);
	183	printk("BONITO_INTEDGE = %08x\n", intedge);
	184	printk("BONITO_INTSTEER = %08x\n", intsteer);
	185	printk("BONITO_PCICMD = %08x\n", pcicmd);
	186	printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
	187	printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
1da177e4 LT	188	break;
	189	}
	190
	191	/* We die here*/
	192	die("CoreHi interrupt", regs);
	193	}
	194
e01402b1 RB	195	static struct irqaction i8259irq = {
	196	.handler = no_action,
	197	.name = "XT-PIC cascade"
	198	};
	199
	200	static struct irqaction corehi_irqaction = {
	201	.handler = no_action,
	202	.name = "CoreHi"
	203	};
	204
	205	msc_irqmap_t __initdata msc_irqmap[] = {
	206	{MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
	207	{MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
	208	};
	209	int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t);
	210
	211	msc_irqmap_t __initdata msc_eicirqmap[] = {
	212	{MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
	213	{MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
	214	{MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
	215	{MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
	216	{MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
	217	{MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
	218	{MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
	219	{MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
	220	{MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
	221	{MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
	222	};
	223	int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);
	224
1da177e4 LT	225	void __init arch_init_irq(void)
	226	{
	227	set_except_vector(0, mipsIRQ);
	228	init_i8259_irqs();
e01402b1 RB	229
	230	if (!cpu_has_veic)
	231	mips_cpu_irq_init (MIPSCPU_INT_BASE);
	232
	233	switch(mips_revision_corid) {
	234	case MIPS_REVISION_CORID_CORE_MSC:
	235	case MIPS_REVISION_CORID_CORE_FPGA2:
	236	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	237	if (cpu_has_veic)
	238	init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
	239	else
	240	init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
	241	}
	242
	243	if (cpu_has_veic) {
	244	set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
	245	set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
	246	setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
	247	setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
	248	}
	249	else if (cpu_has_vint) {
	250	set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
	251	set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
	252
	253	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
	254	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
	255	}
	256	else {
	257	set_except_vector(0, mipsIRQ);
	258	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
	259	setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
	260	}
1da177e4	261	}