]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
79add627 | 6 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
7 | * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) |
8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | |
9 | */ | |
61d73044 | 10 | #include <linux/cpu_pm.h> |
a754f708 | 11 | #include <linux/hardirq.h> |
1da177e4 | 12 | #include <linux/init.h> |
db813fe5 | 13 | #include <linux/highmem.h> |
1da177e4 | 14 | #include <linux/kernel.h> |
641e97f3 | 15 | #include <linux/linkage.h> |
ff522058 | 16 | #include <linux/preempt.h> |
1da177e4 | 17 | #include <linux/sched.h> |
631330f5 | 18 | #include <linux/smp.h> |
1da177e4 | 19 | #include <linux/mm.h> |
35133692 | 20 | #include <linux/module.h> |
1da177e4 LT |
21 | #include <linux/bitops.h> |
22 | ||
23 | #include <asm/bcache.h> | |
24 | #include <asm/bootinfo.h> | |
ec74e361 | 25 | #include <asm/cache.h> |
1da177e4 LT |
26 | #include <asm/cacheops.h> |
27 | #include <asm/cpu.h> | |
28 | #include <asm/cpu-features.h> | |
69f24d17 | 29 | #include <asm/cpu-type.h> |
1da177e4 LT |
30 | #include <asm/io.h> |
31 | #include <asm/page.h> | |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/r4kcache.h> | |
e001e528 | 34 | #include <asm/sections.h> |
1da177e4 LT |
35 | #include <asm/mmu_context.h> |
36 | #include <asm/war.h> | |
ba5187db | 37 | #include <asm/cacheflush.h> /* for run_uncached() */ |
9cd9669b | 38 | #include <asm/traps.h> |
b6d92b4a | 39 | #include <asm/dma-coherence.h> |
cccf34e9 | 40 | #include <asm/mips-cm.h> |
7f3f1d01 | 41 | |
d374d937 JH |
42 | /* |
43 | * Bits describing what cache ops an SMP callback function may perform. | |
44 | * | |
45 | * R4K_HIT - Virtual user or kernel address based cache operations. The | |
46 | * active_mm must be checked before using user addresses, falling | |
47 | * back to kmap. | |
48 | * R4K_INDEX - Index based cache operations. | |
49 | */ | |
50 | ||
51 | #define R4K_HIT BIT(0) | |
52 | #define R4K_INDEX BIT(1) | |
53 | ||
54 | /** | |
55 | * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core. | |
56 | * @type: Type of cache operations (R4K_HIT or R4K_INDEX). | |
57 | * | |
58 | * Decides whether a cache op needs to be performed on every core in the system. | |
640511ae JH |
59 | * This may change depending on the @type of cache operation, as well as the set |
60 | * of online CPUs, so preemption should be disabled by the caller to prevent CPU | |
61 | * hotplug from changing the result. | |
d374d937 JH |
62 | * |
63 | * Returns: 1 if the cache operation @type should be done on every core in | |
64 | * the system. | |
65 | * 0 if the cache operation @type is globalized and only needs to | |
66 | * be performed on a simple CPU. | |
67 | */ | |
68 | static inline bool r4k_op_needs_ipi(unsigned int type) | |
69 | { | |
70 | /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */ | |
11f76903 | 71 | if (type == R4K_HIT && mips_cm_present()) |
d374d937 JH |
72 | return false; |
73 | ||
74 | /* | |
75 | * Hardware doesn't globalize the required cache ops, so SMP calls may | |
640511ae JH |
76 | * be needed, but only if there are foreign CPUs (non-siblings with |
77 | * separate caches). | |
d374d937 | 78 | */ |
640511ae JH |
79 | /* cpu_foreign_map[] undeclared when !CONFIG_SMP */ |
80 | #ifdef CONFIG_SMP | |
81 | return !cpumask_empty(&cpu_foreign_map[0]); | |
82 | #else | |
83 | return false; | |
84 | #endif | |
d374d937 JH |
85 | } |
86 | ||
7f3f1d01 RB |
87 | /* |
88 | * Special Variant of smp_call_function for use by cache functions: | |
89 | * | |
90 | * o No return value | |
91 | * o collapses to normal function call on UP kernels | |
92 | * o collapses to normal function call on systems with a single shared | |
93 | * primary cache. | |
c8c5f3fd | 94 | * o doesn't disable interrupts on the local CPU |
7f3f1d01 | 95 | */ |
d374d937 JH |
96 | static inline void r4k_on_each_cpu(unsigned int type, |
97 | void (*func)(void *info), void *info) | |
7f3f1d01 RB |
98 | { |
99 | preempt_disable(); | |
d374d937 | 100 | if (r4k_op_needs_ipi(type)) |
640511ae JH |
101 | smp_call_function_many(&cpu_foreign_map[smp_processor_id()], |
102 | func, info, 1); | |
7f3f1d01 RB |
103 | func(info); |
104 | preempt_enable(); | |
105 | } | |
106 | ||
ec74e361 RB |
107 | /* |
108 | * Must die. | |
109 | */ | |
110 | static unsigned long icache_size __read_mostly; | |
111 | static unsigned long dcache_size __read_mostly; | |
b2edcfc8 | 112 | static unsigned long vcache_size __read_mostly; |
ec74e361 | 113 | static unsigned long scache_size __read_mostly; |
1da177e4 LT |
114 | |
115 | /* | |
116 | * Dummy cache handling routines for machines without boardcaches | |
117 | */ | |
73f40352 | 118 | static void cache_noop(void) {} |
1da177e4 LT |
119 | |
120 | static struct bcache_ops no_sc_ops = { | |
73f40352 CD |
121 | .bc_enable = (void *)cache_noop, |
122 | .bc_disable = (void *)cache_noop, | |
123 | .bc_wback_inv = (void *)cache_noop, | |
124 | .bc_inv = (void *)cache_noop | |
1da177e4 LT |
125 | }; |
126 | ||
127 | struct bcache_ops *bcops = &no_sc_ops; | |
128 | ||
330cfe01 TS |
129 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) |
130 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) | |
1da177e4 LT |
131 | |
132 | #define R4600_HIT_CACHEOP_WAR_IMPL \ | |
133 | do { \ | |
134 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ | |
135 | *(volatile unsigned long *)CKSEG1; \ | |
136 | if (R4600_V1_HIT_CACHEOP_WAR) \ | |
137 | __asm__ __volatile__("nop;nop;nop;nop"); \ | |
138 | } while (0) | |
139 | ||
140 | static void (*r4k_blast_dcache_page)(unsigned long addr); | |
141 | ||
142 | static inline void r4k_blast_dcache_page_dc32(unsigned long addr) | |
143 | { | |
144 | R4600_HIT_CACHEOP_WAR_IMPL; | |
145 | blast_dcache32_page(addr); | |
146 | } | |
147 | ||
605b7ef7 KC |
148 | static inline void r4k_blast_dcache_page_dc64(unsigned long addr) |
149 | { | |
605b7ef7 KC |
150 | blast_dcache64_page(addr); |
151 | } | |
152 | ||
18a8cd63 DD |
153 | static inline void r4k_blast_dcache_page_dc128(unsigned long addr) |
154 | { | |
155 | blast_dcache128_page(addr); | |
156 | } | |
157 | ||
078a55fc | 158 | static void r4k_blast_dcache_page_setup(void) |
1da177e4 LT |
159 | { |
160 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
161 | ||
18a8cd63 DD |
162 | switch (dc_lsize) { |
163 | case 0: | |
73f40352 | 164 | r4k_blast_dcache_page = (void *)cache_noop; |
18a8cd63 DD |
165 | break; |
166 | case 16: | |
1da177e4 | 167 | r4k_blast_dcache_page = blast_dcache16_page; |
18a8cd63 DD |
168 | break; |
169 | case 32: | |
1da177e4 | 170 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; |
18a8cd63 DD |
171 | break; |
172 | case 64: | |
605b7ef7 | 173 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; |
18a8cd63 DD |
174 | break; |
175 | case 128: | |
176 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc128; | |
177 | break; | |
178 | default: | |
179 | break; | |
180 | } | |
1da177e4 LT |
181 | } |
182 | ||
4caa906e LY |
183 | #ifndef CONFIG_EVA |
184 | #define r4k_blast_dcache_user_page r4k_blast_dcache_page | |
185 | #else | |
186 | ||
187 | static void (*r4k_blast_dcache_user_page)(unsigned long addr); | |
188 | ||
189 | static void r4k_blast_dcache_user_page_setup(void) | |
190 | { | |
191 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
192 | ||
193 | if (dc_lsize == 0) | |
194 | r4k_blast_dcache_user_page = (void *)cache_noop; | |
195 | else if (dc_lsize == 16) | |
196 | r4k_blast_dcache_user_page = blast_dcache16_user_page; | |
197 | else if (dc_lsize == 32) | |
198 | r4k_blast_dcache_user_page = blast_dcache32_user_page; | |
199 | else if (dc_lsize == 64) | |
200 | r4k_blast_dcache_user_page = blast_dcache64_user_page; | |
201 | } | |
202 | ||
203 | #endif | |
204 | ||
1da177e4 LT |
205 | static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); |
206 | ||
078a55fc | 207 | static void r4k_blast_dcache_page_indexed_setup(void) |
1da177e4 LT |
208 | { |
209 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
210 | ||
73f40352 CD |
211 | if (dc_lsize == 0) |
212 | r4k_blast_dcache_page_indexed = (void *)cache_noop; | |
213 | else if (dc_lsize == 16) | |
1da177e4 LT |
214 | r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; |
215 | else if (dc_lsize == 32) | |
216 | r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; | |
605b7ef7 KC |
217 | else if (dc_lsize == 64) |
218 | r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; | |
18a8cd63 DD |
219 | else if (dc_lsize == 128) |
220 | r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed; | |
1da177e4 LT |
221 | } |
222 | ||
f2e3656d SL |
223 | void (* r4k_blast_dcache)(void); |
224 | EXPORT_SYMBOL(r4k_blast_dcache); | |
1da177e4 | 225 | |
078a55fc | 226 | static void r4k_blast_dcache_setup(void) |
1da177e4 LT |
227 | { |
228 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
229 | ||
73f40352 CD |
230 | if (dc_lsize == 0) |
231 | r4k_blast_dcache = (void *)cache_noop; | |
232 | else if (dc_lsize == 16) | |
1da177e4 LT |
233 | r4k_blast_dcache = blast_dcache16; |
234 | else if (dc_lsize == 32) | |
235 | r4k_blast_dcache = blast_dcache32; | |
605b7ef7 KC |
236 | else if (dc_lsize == 64) |
237 | r4k_blast_dcache = blast_dcache64; | |
18a8cd63 DD |
238 | else if (dc_lsize == 128) |
239 | r4k_blast_dcache = blast_dcache128; | |
1da177e4 LT |
240 | } |
241 | ||
242 | /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ | |
243 | #define JUMP_TO_ALIGN(order) \ | |
244 | __asm__ __volatile__( \ | |
245 | "b\t1f\n\t" \ | |
246 | ".align\t" #order "\n\t" \ | |
247 | "1:\n\t" \ | |
248 | ) | |
249 | #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ | |
70342287 | 250 | #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) |
1da177e4 LT |
251 | |
252 | static inline void blast_r4600_v1_icache32(void) | |
253 | { | |
254 | unsigned long flags; | |
255 | ||
256 | local_irq_save(flags); | |
257 | blast_icache32(); | |
258 | local_irq_restore(flags); | |
259 | } | |
260 | ||
261 | static inline void tx49_blast_icache32(void) | |
262 | { | |
263 | unsigned long start = INDEX_BASE; | |
264 | unsigned long end = start + current_cpu_data.icache.waysize; | |
265 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
266 | unsigned long ws_end = current_cpu_data.icache.ways << | |
70342287 | 267 | current_cpu_data.icache.waybit; |
1da177e4 LT |
268 | unsigned long ws, addr; |
269 | ||
270 | CACHE32_UNROLL32_ALIGN2; | |
271 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
272 | for (ws = 0; ws < ws_end; ws += ws_inc) |
273 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 274 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
275 | CACHE32_UNROLL32_ALIGN; |
276 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
277 | for (ws = 0; ws < ws_end; ws += ws_inc) |
278 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 279 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
280 | } |
281 | ||
282 | static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) | |
283 | { | |
284 | unsigned long flags; | |
285 | ||
286 | local_irq_save(flags); | |
287 | blast_icache32_page_indexed(page); | |
288 | local_irq_restore(flags); | |
289 | } | |
290 | ||
291 | static inline void tx49_blast_icache32_page_indexed(unsigned long page) | |
292 | { | |
67a3f6de AN |
293 | unsigned long indexmask = current_cpu_data.icache.waysize - 1; |
294 | unsigned long start = INDEX_BASE + (page & indexmask); | |
1da177e4 LT |
295 | unsigned long end = start + PAGE_SIZE; |
296 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
297 | unsigned long ws_end = current_cpu_data.icache.ways << | |
70342287 | 298 | current_cpu_data.icache.waybit; |
1da177e4 LT |
299 | unsigned long ws, addr; |
300 | ||
301 | CACHE32_UNROLL32_ALIGN2; | |
302 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
303 | for (ws = 0; ws < ws_end; ws += ws_inc) |
304 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 305 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
306 | CACHE32_UNROLL32_ALIGN; |
307 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
308 | for (ws = 0; ws < ws_end; ws += ws_inc) |
309 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 310 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
311 | } |
312 | ||
313 | static void (* r4k_blast_icache_page)(unsigned long addr); | |
314 | ||
078a55fc | 315 | static void r4k_blast_icache_page_setup(void) |
1da177e4 LT |
316 | { |
317 | unsigned long ic_lsize = cpu_icache_line_size(); | |
318 | ||
73f40352 CD |
319 | if (ic_lsize == 0) |
320 | r4k_blast_icache_page = (void *)cache_noop; | |
321 | else if (ic_lsize == 16) | |
1da177e4 | 322 | r4k_blast_icache_page = blast_icache16_page; |
43a06847 AK |
323 | else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2) |
324 | r4k_blast_icache_page = loongson2_blast_icache32_page; | |
1da177e4 LT |
325 | else if (ic_lsize == 32) |
326 | r4k_blast_icache_page = blast_icache32_page; | |
327 | else if (ic_lsize == 64) | |
328 | r4k_blast_icache_page = blast_icache64_page; | |
18a8cd63 DD |
329 | else if (ic_lsize == 128) |
330 | r4k_blast_icache_page = blast_icache128_page; | |
1da177e4 LT |
331 | } |
332 | ||
4caa906e LY |
333 | #ifndef CONFIG_EVA |
334 | #define r4k_blast_icache_user_page r4k_blast_icache_page | |
335 | #else | |
336 | ||
337 | static void (*r4k_blast_icache_user_page)(unsigned long addr); | |
338 | ||
9a8f4ea0 | 339 | static void r4k_blast_icache_user_page_setup(void) |
4caa906e LY |
340 | { |
341 | unsigned long ic_lsize = cpu_icache_line_size(); | |
342 | ||
343 | if (ic_lsize == 0) | |
344 | r4k_blast_icache_user_page = (void *)cache_noop; | |
345 | else if (ic_lsize == 16) | |
346 | r4k_blast_icache_user_page = blast_icache16_user_page; | |
347 | else if (ic_lsize == 32) | |
348 | r4k_blast_icache_user_page = blast_icache32_user_page; | |
349 | else if (ic_lsize == 64) | |
350 | r4k_blast_icache_user_page = blast_icache64_user_page; | |
351 | } | |
352 | ||
353 | #endif | |
1da177e4 LT |
354 | |
355 | static void (* r4k_blast_icache_page_indexed)(unsigned long addr); | |
356 | ||
078a55fc | 357 | static void r4k_blast_icache_page_indexed_setup(void) |
1da177e4 LT |
358 | { |
359 | unsigned long ic_lsize = cpu_icache_line_size(); | |
360 | ||
73f40352 CD |
361 | if (ic_lsize == 0) |
362 | r4k_blast_icache_page_indexed = (void *)cache_noop; | |
363 | else if (ic_lsize == 16) | |
1da177e4 LT |
364 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; |
365 | else if (ic_lsize == 32) { | |
02fe2c9c | 366 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
1da177e4 LT |
367 | r4k_blast_icache_page_indexed = |
368 | blast_icache32_r4600_v1_page_indexed; | |
02fe2c9c TS |
369 | else if (TX49XX_ICACHE_INDEX_INV_WAR) |
370 | r4k_blast_icache_page_indexed = | |
371 | tx49_blast_icache32_page_indexed; | |
43a06847 AK |
372 | else if (current_cpu_type() == CPU_LOONGSON2) |
373 | r4k_blast_icache_page_indexed = | |
374 | loongson2_blast_icache32_page_indexed; | |
1da177e4 LT |
375 | else |
376 | r4k_blast_icache_page_indexed = | |
377 | blast_icache32_page_indexed; | |
378 | } else if (ic_lsize == 64) | |
379 | r4k_blast_icache_page_indexed = blast_icache64_page_indexed; | |
380 | } | |
381 | ||
f2e3656d SL |
382 | void (* r4k_blast_icache)(void); |
383 | EXPORT_SYMBOL(r4k_blast_icache); | |
1da177e4 | 384 | |
078a55fc | 385 | static void r4k_blast_icache_setup(void) |
1da177e4 LT |
386 | { |
387 | unsigned long ic_lsize = cpu_icache_line_size(); | |
388 | ||
73f40352 CD |
389 | if (ic_lsize == 0) |
390 | r4k_blast_icache = (void *)cache_noop; | |
391 | else if (ic_lsize == 16) | |
1da177e4 LT |
392 | r4k_blast_icache = blast_icache16; |
393 | else if (ic_lsize == 32) { | |
394 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) | |
395 | r4k_blast_icache = blast_r4600_v1_icache32; | |
396 | else if (TX49XX_ICACHE_INDEX_INV_WAR) | |
397 | r4k_blast_icache = tx49_blast_icache32; | |
43a06847 AK |
398 | else if (current_cpu_type() == CPU_LOONGSON2) |
399 | r4k_blast_icache = loongson2_blast_icache32; | |
1da177e4 LT |
400 | else |
401 | r4k_blast_icache = blast_icache32; | |
402 | } else if (ic_lsize == 64) | |
403 | r4k_blast_icache = blast_icache64; | |
18a8cd63 DD |
404 | else if (ic_lsize == 128) |
405 | r4k_blast_icache = blast_icache128; | |
1da177e4 LT |
406 | } |
407 | ||
408 | static void (* r4k_blast_scache_page)(unsigned long addr); | |
409 | ||
078a55fc | 410 | static void r4k_blast_scache_page_setup(void) |
1da177e4 LT |
411 | { |
412 | unsigned long sc_lsize = cpu_scache_line_size(); | |
413 | ||
4debe4f9 | 414 | if (scache_size == 0) |
73f40352 | 415 | r4k_blast_scache_page = (void *)cache_noop; |
4debe4f9 | 416 | else if (sc_lsize == 16) |
1da177e4 LT |
417 | r4k_blast_scache_page = blast_scache16_page; |
418 | else if (sc_lsize == 32) | |
419 | r4k_blast_scache_page = blast_scache32_page; | |
420 | else if (sc_lsize == 64) | |
421 | r4k_blast_scache_page = blast_scache64_page; | |
422 | else if (sc_lsize == 128) | |
423 | r4k_blast_scache_page = blast_scache128_page; | |
424 | } | |
425 | ||
426 | static void (* r4k_blast_scache_page_indexed)(unsigned long addr); | |
427 | ||
078a55fc | 428 | static void r4k_blast_scache_page_indexed_setup(void) |
1da177e4 LT |
429 | { |
430 | unsigned long sc_lsize = cpu_scache_line_size(); | |
431 | ||
4debe4f9 | 432 | if (scache_size == 0) |
73f40352 | 433 | r4k_blast_scache_page_indexed = (void *)cache_noop; |
4debe4f9 | 434 | else if (sc_lsize == 16) |
1da177e4 LT |
435 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; |
436 | else if (sc_lsize == 32) | |
437 | r4k_blast_scache_page_indexed = blast_scache32_page_indexed; | |
438 | else if (sc_lsize == 64) | |
439 | r4k_blast_scache_page_indexed = blast_scache64_page_indexed; | |
440 | else if (sc_lsize == 128) | |
441 | r4k_blast_scache_page_indexed = blast_scache128_page_indexed; | |
442 | } | |
443 | ||
444 | static void (* r4k_blast_scache)(void); | |
445 | ||
078a55fc | 446 | static void r4k_blast_scache_setup(void) |
1da177e4 LT |
447 | { |
448 | unsigned long sc_lsize = cpu_scache_line_size(); | |
449 | ||
4debe4f9 | 450 | if (scache_size == 0) |
73f40352 | 451 | r4k_blast_scache = (void *)cache_noop; |
4debe4f9 | 452 | else if (sc_lsize == 16) |
1da177e4 LT |
453 | r4k_blast_scache = blast_scache16; |
454 | else if (sc_lsize == 32) | |
455 | r4k_blast_scache = blast_scache32; | |
456 | else if (sc_lsize == 64) | |
457 | r4k_blast_scache = blast_scache64; | |
458 | else if (sc_lsize == 128) | |
459 | r4k_blast_scache = blast_scache128; | |
460 | } | |
461 | ||
1da177e4 LT |
462 | static inline void local_r4k___flush_cache_all(void * args) |
463 | { | |
10cc3529 | 464 | switch (current_cpu_type()) { |
14bd8c08 | 465 | case CPU_LOONGSON2: |
c579d310 | 466 | case CPU_LOONGSON3: |
1da177e4 LT |
467 | case CPU_R4000SC: |
468 | case CPU_R4000MC: | |
469 | case CPU_R4400SC: | |
470 | case CPU_R4400MC: | |
471 | case CPU_R10000: | |
472 | case CPU_R12000: | |
44d921b2 | 473 | case CPU_R14000: |
30577391 | 474 | case CPU_R16000: |
14bd8c08 RB |
475 | /* |
476 | * These caches are inclusive caches, that is, if something | |
477 | * is not cached in the S-cache, we know it also won't be | |
478 | * in one of the primary caches. | |
479 | */ | |
1da177e4 | 480 | r4k_blast_scache(); |
14bd8c08 RB |
481 | break; |
482 | ||
f675843d FF |
483 | case CPU_BMIPS5000: |
484 | r4k_blast_scache(); | |
485 | __sync(); | |
486 | break; | |
487 | ||
14bd8c08 RB |
488 | default: |
489 | r4k_blast_dcache(); | |
490 | r4k_blast_icache(); | |
491 | break; | |
1da177e4 LT |
492 | } |
493 | } | |
494 | ||
495 | static void r4k___flush_cache_all(void) | |
496 | { | |
d374d937 | 497 | r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL); |
1da177e4 LT |
498 | } |
499 | ||
6d758bfc JH |
500 | /** |
501 | * has_valid_asid() - Determine if an mm already has an ASID. | |
502 | * @mm: Memory map. | |
503 | * @type: R4K_HIT or R4K_INDEX, type of cache op. | |
504 | * | |
505 | * Determines whether @mm already has an ASID on any of the CPUs which cache ops | |
506 | * of type @type within an r4k_on_each_cpu() call will affect. If | |
507 | * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the | |
508 | * scope of the operation is confined to sibling CPUs, otherwise all online CPUs | |
509 | * will need to be checked. | |
510 | * | |
511 | * Must be called in non-preemptive context. | |
512 | * | |
513 | * Returns: 1 if the CPUs affected by @type cache ops have an ASID for @mm. | |
514 | * 0 otherwise. | |
515 | */ | |
516 | static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type) | |
a76ab5c1 | 517 | { |
6d758bfc JH |
518 | unsigned int i; |
519 | const cpumask_t *mask = cpu_present_mask; | |
a76ab5c1 | 520 | |
6d758bfc JH |
521 | /* cpu_sibling_map[] undeclared when !CONFIG_SMP */ |
522 | #ifdef CONFIG_SMP | |
523 | /* | |
524 | * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in | |
525 | * each foreign core, so we only need to worry about siblings. | |
526 | * Otherwise we need to worry about all present CPUs. | |
527 | */ | |
528 | if (r4k_op_needs_ipi(type)) | |
529 | mask = &cpu_sibling_map[smp_processor_id()]; | |
530 | #endif | |
531 | for_each_cpu(i, mask) | |
a76ab5c1 RB |
532 | if (cpu_context(i, mm)) |
533 | return 1; | |
a76ab5c1 | 534 | return 0; |
a76ab5c1 RB |
535 | } |
536 | ||
9c5a3d72 RB |
537 | static void r4k__flush_cache_vmap(void) |
538 | { | |
539 | r4k_blast_dcache(); | |
540 | } | |
541 | ||
542 | static void r4k__flush_cache_vunmap(void) | |
543 | { | |
544 | r4k_blast_dcache(); | |
545 | } | |
546 | ||
a05c3920 JH |
547 | /* |
548 | * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes | |
549 | * whole caches when vma is executable. | |
550 | */ | |
1da177e4 LT |
551 | static inline void local_r4k_flush_cache_range(void * args) |
552 | { | |
553 | struct vm_area_struct *vma = args; | |
2eaa7ec2 | 554 | int exec = vma->vm_flags & VM_EXEC; |
1da177e4 | 555 | |
6d758bfc | 556 | if (!has_valid_asid(vma->vm_mm, R4K_INDEX)) |
1da177e4 LT |
557 | return; |
558 | ||
b2a3c5be JH |
559 | /* |
560 | * If dcache can alias, we must blast it since mapping is changing. | |
561 | * If executable, we must ensure any dirty lines are written back far | |
562 | * enough to be visible to icache. | |
563 | */ | |
564 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) | |
565 | r4k_blast_dcache(); | |
566 | /* If executable, blast stale lines from icache */ | |
2eaa7ec2 RB |
567 | if (exec) |
568 | r4k_blast_icache(); | |
1da177e4 LT |
569 | } |
570 | ||
571 | static void r4k_flush_cache_range(struct vm_area_struct *vma, | |
572 | unsigned long start, unsigned long end) | |
573 | { | |
2eaa7ec2 | 574 | int exec = vma->vm_flags & VM_EXEC; |
0550d9d1 | 575 | |
b2a3c5be | 576 | if (cpu_has_dc_aliases || exec) |
d374d937 | 577 | r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma); |
1da177e4 LT |
578 | } |
579 | ||
580 | static inline void local_r4k_flush_cache_mm(void * args) | |
581 | { | |
582 | struct mm_struct *mm = args; | |
583 | ||
6d758bfc | 584 | if (!has_valid_asid(mm, R4K_INDEX)) |
1da177e4 LT |
585 | return; |
586 | ||
1da177e4 LT |
587 | /* |
588 | * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we | |
30577391 | 589 | * only flush the primary caches but R1x000 behave sane ... |
617667ba RB |
590 | * R4000SC and R4400SC indexed S-cache ops also invalidate primary |
591 | * caches, so we can bail out early. | |
1da177e4 | 592 | */ |
10cc3529 RB |
593 | if (current_cpu_type() == CPU_R4000SC || |
594 | current_cpu_type() == CPU_R4000MC || | |
595 | current_cpu_type() == CPU_R4400SC || | |
596 | current_cpu_type() == CPU_R4400MC) { | |
1da177e4 | 597 | r4k_blast_scache(); |
617667ba RB |
598 | return; |
599 | } | |
600 | ||
601 | r4k_blast_dcache(); | |
1da177e4 LT |
602 | } |
603 | ||
604 | static void r4k_flush_cache_mm(struct mm_struct *mm) | |
605 | { | |
606 | if (!cpu_has_dc_aliases) | |
607 | return; | |
608 | ||
d374d937 | 609 | r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm); |
1da177e4 LT |
610 | } |
611 | ||
612 | struct flush_cache_page_args { | |
613 | struct vm_area_struct *vma; | |
6ec25809 | 614 | unsigned long addr; |
de62893b | 615 | unsigned long pfn; |
1da177e4 LT |
616 | }; |
617 | ||
618 | static inline void local_r4k_flush_cache_page(void *args) | |
619 | { | |
620 | struct flush_cache_page_args *fcp_args = args; | |
621 | struct vm_area_struct *vma = fcp_args->vma; | |
6ec25809 | 622 | unsigned long addr = fcp_args->addr; |
db813fe5 | 623 | struct page *page = pfn_to_page(fcp_args->pfn); |
1da177e4 LT |
624 | int exec = vma->vm_flags & VM_EXEC; |
625 | struct mm_struct *mm = vma->vm_mm; | |
c9c5023d | 626 | int map_coherent = 0; |
1da177e4 | 627 | pgd_t *pgdp; |
c6e8b587 | 628 | pud_t *pudp; |
1da177e4 LT |
629 | pmd_t *pmdp; |
630 | pte_t *ptep; | |
db813fe5 | 631 | void *vaddr; |
1da177e4 | 632 | |
79acf83e | 633 | /* |
6d758bfc | 634 | * If owns no valid ASID yet, cannot possibly have gotten |
79acf83e RB |
635 | * this page into the cache. |
636 | */ | |
6d758bfc | 637 | if (!has_valid_asid(mm, R4K_HIT)) |
79acf83e RB |
638 | return; |
639 | ||
6ec25809 RB |
640 | addr &= PAGE_MASK; |
641 | pgdp = pgd_offset(mm, addr); | |
642 | pudp = pud_offset(pgdp, addr); | |
643 | pmdp = pmd_offset(pudp, addr); | |
644 | ptep = pte_offset(pmdp, addr); | |
1da177e4 LT |
645 | |
646 | /* | |
647 | * If the page isn't marked valid, the page cannot possibly be | |
648 | * in the cache. | |
649 | */ | |
526af35e | 650 | if (!(pte_present(*ptep))) |
1da177e4 LT |
651 | return; |
652 | ||
db813fe5 RB |
653 | if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) |
654 | vaddr = NULL; | |
655 | else { | |
656 | /* | |
657 | * Use kmap_coherent or kmap_atomic to do flushes for | |
658 | * another ASID than the current one. | |
659 | */ | |
c9c5023d | 660 | map_coherent = (cpu_has_dc_aliases && |
e1534ae9 KS |
661 | page_mapcount(page) && |
662 | !Page_dcache_dirty(page)); | |
c9c5023d | 663 | if (map_coherent) |
db813fe5 RB |
664 | vaddr = kmap_coherent(page, addr); |
665 | else | |
9c02048f | 666 | vaddr = kmap_atomic(page); |
db813fe5 | 667 | addr = (unsigned long)vaddr; |
1da177e4 LT |
668 | } |
669 | ||
1da177e4 | 670 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { |
80ca69f4 MC |
671 | vaddr ? r4k_blast_dcache_page(addr) : |
672 | r4k_blast_dcache_user_page(addr); | |
39b8d525 RB |
673 | if (exec && !cpu_icache_snoops_remote_store) |
674 | r4k_blast_scache_page(addr); | |
1da177e4 LT |
675 | } |
676 | if (exec) { | |
db813fe5 | 677 | if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { |
1da177e4 LT |
678 | int cpu = smp_processor_id(); |
679 | ||
26a51b27 TS |
680 | if (cpu_context(cpu, mm) != 0) |
681 | drop_mmu_context(mm, cpu); | |
1da177e4 | 682 | } else |
80ca69f4 MC |
683 | vaddr ? r4k_blast_icache_page(addr) : |
684 | r4k_blast_icache_user_page(addr); | |
db813fe5 RB |
685 | } |
686 | ||
687 | if (vaddr) { | |
c9c5023d | 688 | if (map_coherent) |
db813fe5 RB |
689 | kunmap_coherent(); |
690 | else | |
9c02048f | 691 | kunmap_atomic(vaddr); |
1da177e4 LT |
692 | } |
693 | } | |
694 | ||
6ec25809 RB |
695 | static void r4k_flush_cache_page(struct vm_area_struct *vma, |
696 | unsigned long addr, unsigned long pfn) | |
1da177e4 LT |
697 | { |
698 | struct flush_cache_page_args args; | |
699 | ||
1da177e4 | 700 | args.vma = vma; |
6ec25809 | 701 | args.addr = addr; |
de62893b | 702 | args.pfn = pfn; |
1da177e4 | 703 | |
d374d937 | 704 | r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args); |
1da177e4 LT |
705 | } |
706 | ||
707 | static inline void local_r4k_flush_data_cache_page(void * addr) | |
708 | { | |
709 | r4k_blast_dcache_page((unsigned long) addr); | |
710 | } | |
711 | ||
712 | static void r4k_flush_data_cache_page(unsigned long addr) | |
713 | { | |
a754f708 RB |
714 | if (in_atomic()) |
715 | local_r4k_flush_data_cache_page((void *)addr); | |
716 | else | |
d374d937 JH |
717 | r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page, |
718 | (void *) addr); | |
1da177e4 LT |
719 | } |
720 | ||
721 | struct flush_icache_range_args { | |
d4264f18 AN |
722 | unsigned long start; |
723 | unsigned long end; | |
27b93d9c | 724 | unsigned int type; |
1da177e4 LT |
725 | }; |
726 | ||
27b93d9c JH |
727 | static inline void __local_r4k_flush_icache_range(unsigned long start, |
728 | unsigned long end, | |
729 | unsigned int type) | |
1da177e4 | 730 | { |
1da177e4 | 731 | if (!cpu_has_ic_fills_f_dc) { |
27b93d9c JH |
732 | if (type == R4K_INDEX || |
733 | (type & R4K_INDEX && end - start >= dcache_size)) { | |
1da177e4 LT |
734 | r4k_blast_dcache(); |
735 | } else { | |
10a3dabd | 736 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 737 | protected_blast_dcache_range(start, end); |
1da177e4 | 738 | } |
1da177e4 LT |
739 | } |
740 | ||
27b93d9c JH |
741 | if (type == R4K_INDEX || |
742 | (type & R4K_INDEX && end - start > icache_size)) | |
1da177e4 | 743 | r4k_blast_icache(); |
14bd8c08 RB |
744 | else { |
745 | switch (boot_cpu_type()) { | |
746 | case CPU_LOONGSON2: | |
bad009fe | 747 | protected_loongson2_blast_icache_range(start, end); |
14bd8c08 RB |
748 | break; |
749 | ||
750 | default: | |
bad009fe | 751 | protected_blast_icache_range(start, end); |
14bd8c08 RB |
752 | break; |
753 | } | |
754 | } | |
4676f935 LY |
755 | #ifdef CONFIG_EVA |
756 | /* | |
757 | * Due to all possible segment mappings, there might cache aliases | |
758 | * caused by the bootloader being in non-EVA mode, and the CPU switching | |
759 | * to EVA during early kernel init. It's best to flush the scache | |
760 | * to avoid having secondary cores fetching stale data and lead to | |
761 | * kernel crashes. | |
762 | */ | |
763 | bc_wback_inv(start, (end - start)); | |
764 | __sync(); | |
765 | #endif | |
1da177e4 LT |
766 | } |
767 | ||
27b93d9c JH |
768 | static inline void local_r4k_flush_icache_range(unsigned long start, |
769 | unsigned long end) | |
770 | { | |
771 | __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX); | |
772 | } | |
773 | ||
e0cee3ee TB |
774 | static inline void local_r4k_flush_icache_range_ipi(void *args) |
775 | { | |
776 | struct flush_icache_range_args *fir_args = args; | |
777 | unsigned long start = fir_args->start; | |
778 | unsigned long end = fir_args->end; | |
27b93d9c | 779 | unsigned int type = fir_args->type; |
e0cee3ee | 780 | |
27b93d9c | 781 | __local_r4k_flush_icache_range(start, end, type); |
e0cee3ee TB |
782 | } |
783 | ||
d4264f18 | 784 | static void r4k_flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 LT |
785 | { |
786 | struct flush_icache_range_args args; | |
f70ddc07 | 787 | unsigned long size, cache_size; |
1da177e4 LT |
788 | |
789 | args.start = start; | |
790 | args.end = end; | |
27b93d9c | 791 | args.type = R4K_HIT | R4K_INDEX; |
1da177e4 | 792 | |
f70ddc07 JH |
793 | /* |
794 | * Indexed cache ops require an SMP call. | |
795 | * Consider if that can or should be avoided. | |
796 | */ | |
797 | preempt_disable(); | |
798 | if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) { | |
799 | /* | |
800 | * If address-based cache ops don't require an SMP call, then | |
801 | * use them exclusively for small flushes. | |
802 | */ | |
801f823d | 803 | size = end - start; |
f70ddc07 JH |
804 | cache_size = icache_size; |
805 | if (!cpu_has_ic_fills_f_dc) { | |
806 | size *= 2; | |
807 | cache_size += dcache_size; | |
808 | } | |
809 | if (size <= cache_size) | |
810 | args.type &= ~R4K_INDEX; | |
811 | } | |
27b93d9c | 812 | r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args); |
f70ddc07 | 813 | preempt_enable(); |
cc61c1fe | 814 | instruction_hazard(); |
1da177e4 LT |
815 | } |
816 | ||
8005711c | 817 | #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) |
1da177e4 LT |
818 | |
819 | static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) | |
820 | { | |
1da177e4 LT |
821 | /* Catch bad driver code */ |
822 | BUG_ON(size == 0); | |
823 | ||
ff522058 | 824 | preempt_disable(); |
fc5d2d27 | 825 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 826 | if (size >= scache_size) |
1da177e4 | 827 | r4k_blast_scache(); |
41700e73 AN |
828 | else |
829 | blast_scache_range(addr, addr + size); | |
5596b0b2 | 830 | preempt_enable(); |
d0023c4a | 831 | __sync(); |
1da177e4 LT |
832 | return; |
833 | } | |
834 | ||
835 | /* | |
836 | * Either no secondary cache or the available caches don't have the | |
837 | * subset property so we have to flush the primary caches | |
838 | * explicitly | |
839 | */ | |
c00ab489 | 840 | if (size >= dcache_size) { |
1da177e4 LT |
841 | r4k_blast_dcache(); |
842 | } else { | |
1da177e4 | 843 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 844 | blast_dcache_range(addr, addr + size); |
1da177e4 | 845 | } |
ff522058 | 846 | preempt_enable(); |
1da177e4 LT |
847 | |
848 | bc_wback_inv(addr, size); | |
d0023c4a | 849 | __sync(); |
1da177e4 LT |
850 | } |
851 | ||
852 | static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) | |
853 | { | |
1da177e4 LT |
854 | /* Catch bad driver code */ |
855 | BUG_ON(size == 0); | |
856 | ||
ff522058 | 857 | preempt_disable(); |
fc5d2d27 | 858 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 859 | if (size >= scache_size) |
1da177e4 | 860 | r4k_blast_scache(); |
a8ca8b64 | 861 | else { |
a8ca8b64 RB |
862 | /* |
863 | * There is no clearly documented alignment requirement | |
864 | * for the cache instruction on MIPS processors and | |
865 | * some processors, among them the RM5200 and RM7000 | |
866 | * QED processors will throw an address error for cache | |
70342287 | 867 | * hit ops with insufficient alignment. Solved by |
a8ca8b64 RB |
868 | * aligning the address to cache line size. |
869 | */ | |
e9c33572 | 870 | blast_inv_scache_range(addr, addr + size); |
a8ca8b64 | 871 | } |
5596b0b2 | 872 | preempt_enable(); |
d0023c4a | 873 | __sync(); |
1da177e4 LT |
874 | return; |
875 | } | |
876 | ||
c00ab489 | 877 | if (size >= dcache_size) { |
1da177e4 LT |
878 | r4k_blast_dcache(); |
879 | } else { | |
1da177e4 | 880 | R4600_HIT_CACHEOP_WAR_IMPL; |
e9c33572 | 881 | blast_inv_dcache_range(addr, addr + size); |
1da177e4 | 882 | } |
ff522058 | 883 | preempt_enable(); |
1da177e4 LT |
884 | |
885 | bc_inv(addr, size); | |
d0023c4a | 886 | __sync(); |
1da177e4 | 887 | } |
8005711c | 888 | #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ |
1da177e4 | 889 | |
e523f289 JH |
890 | struct flush_cache_sigtramp_args { |
891 | struct mm_struct *mm; | |
892 | struct page *page; | |
893 | unsigned long addr; | |
894 | }; | |
895 | ||
1da177e4 LT |
896 | /* |
897 | * While we're protected against bad userland addresses we don't care | |
898 | * very much about what happens in that case. Usually a segmentation | |
899 | * fault will dump the process later on anyway ... | |
900 | */ | |
e523f289 | 901 | static void local_r4k_flush_cache_sigtramp(void *args) |
1da177e4 | 902 | { |
e523f289 JH |
903 | struct flush_cache_sigtramp_args *fcs_args = args; |
904 | unsigned long addr = fcs_args->addr; | |
905 | struct page *page = fcs_args->page; | |
906 | struct mm_struct *mm = fcs_args->mm; | |
907 | int map_coherent = 0; | |
908 | void *vaddr; | |
909 | ||
02fe2c9c TS |
910 | unsigned long ic_lsize = cpu_icache_line_size(); |
911 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
912 | unsigned long sc_lsize = cpu_scache_line_size(); | |
e523f289 JH |
913 | |
914 | /* | |
915 | * If owns no valid ASID yet, cannot possibly have gotten | |
916 | * this page into the cache. | |
917 | */ | |
6d758bfc | 918 | if (!has_valid_asid(mm, R4K_HIT)) |
e523f289 JH |
919 | return; |
920 | ||
921 | if (mm == current->active_mm) { | |
922 | vaddr = NULL; | |
923 | } else { | |
924 | /* | |
925 | * Use kmap_coherent or kmap_atomic to do flushes for | |
926 | * another ASID than the current one. | |
927 | */ | |
928 | map_coherent = (cpu_has_dc_aliases && | |
929 | page_mapcount(page) && | |
930 | !Page_dcache_dirty(page)); | |
931 | if (map_coherent) | |
932 | vaddr = kmap_coherent(page, addr); | |
933 | else | |
934 | vaddr = kmap_atomic(page); | |
935 | addr = (unsigned long)vaddr + (addr & ~PAGE_MASK); | |
936 | } | |
1da177e4 LT |
937 | |
938 | R4600_HIT_CACHEOP_WAR_IMPL; | |
8bd646e9 JH |
939 | if (!cpu_has_ic_fills_f_dc) { |
940 | if (dc_lsize) | |
941 | vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1)) | |
942 | : protected_writeback_dcache_line( | |
943 | addr & ~(dc_lsize - 1)); | |
944 | if (!cpu_icache_snoops_remote_store && scache_size) | |
945 | vaddr ? flush_scache_line(addr & ~(sc_lsize - 1)) | |
946 | : protected_writeback_scache_line( | |
947 | addr & ~(sc_lsize - 1)); | |
948 | } | |
73f40352 | 949 | if (ic_lsize) |
e523f289 JH |
950 | vaddr ? flush_icache_line(addr & ~(ic_lsize - 1)) |
951 | : protected_flush_icache_line(addr & ~(ic_lsize - 1)); | |
952 | ||
953 | if (vaddr) { | |
954 | if (map_coherent) | |
955 | kunmap_coherent(); | |
956 | else | |
957 | kunmap_atomic(vaddr); | |
958 | } | |
959 | ||
1da177e4 LT |
960 | if (MIPS4K_ICACHE_REFILL_WAR) { |
961 | __asm__ __volatile__ ( | |
962 | ".set push\n\t" | |
963 | ".set noat\n\t" | |
4ee48627 | 964 | ".set "MIPS_ISA_LEVEL"\n\t" |
875d43e7 | 965 | #ifdef CONFIG_32BIT |
1da177e4 LT |
966 | "la $at,1f\n\t" |
967 | #endif | |
875d43e7 | 968 | #ifdef CONFIG_64BIT |
1da177e4 LT |
969 | "dla $at,1f\n\t" |
970 | #endif | |
971 | "cache %0,($at)\n\t" | |
972 | "nop; nop; nop\n" | |
973 | "1:\n\t" | |
974 | ".set pop" | |
975 | : | |
976 | : "i" (Hit_Invalidate_I)); | |
977 | } | |
978 | if (MIPS_CACHE_SYNC_WAR) | |
979 | __asm__ __volatile__ ("sync"); | |
980 | } | |
981 | ||
982 | static void r4k_flush_cache_sigtramp(unsigned long addr) | |
983 | { | |
e523f289 JH |
984 | struct flush_cache_sigtramp_args args; |
985 | int npages; | |
986 | ||
987 | down_read(¤t->mm->mmap_sem); | |
988 | ||
989 | npages = get_user_pages_fast(addr, 1, 0, &args.page); | |
990 | if (npages < 1) | |
991 | goto out; | |
992 | ||
993 | args.mm = current->mm; | |
994 | args.addr = addr; | |
995 | ||
d374d937 | 996 | r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_sigtramp, &args); |
e523f289 JH |
997 | |
998 | put_page(args.page); | |
999 | out: | |
1000 | up_read(¤t->mm->mmap_sem); | |
1da177e4 LT |
1001 | } |
1002 | ||
1003 | static void r4k_flush_icache_all(void) | |
1004 | { | |
1005 | if (cpu_has_vtag_icache) | |
1006 | r4k_blast_icache(); | |
1007 | } | |
1008 | ||
d9cdc901 RB |
1009 | struct flush_kernel_vmap_range_args { |
1010 | unsigned long vaddr; | |
1011 | int size; | |
1012 | }; | |
1013 | ||
a9341ae2 JH |
1014 | static inline void local_r4k_flush_kernel_vmap_range_index(void *args) |
1015 | { | |
1016 | /* | |
1017 | * Aliases only affect the primary caches so don't bother with | |
1018 | * S-caches or T-caches. | |
1019 | */ | |
1020 | r4k_blast_dcache(); | |
1021 | } | |
1022 | ||
d9cdc901 RB |
1023 | static inline void local_r4k_flush_kernel_vmap_range(void *args) |
1024 | { | |
1025 | struct flush_kernel_vmap_range_args *vmra = args; | |
1026 | unsigned long vaddr = vmra->vaddr; | |
1027 | int size = vmra->size; | |
1028 | ||
1029 | /* | |
1030 | * Aliases only affect the primary caches so don't bother with | |
1031 | * S-caches or T-caches. | |
1032 | */ | |
a9341ae2 JH |
1033 | R4600_HIT_CACHEOP_WAR_IMPL; |
1034 | blast_dcache_range(vaddr, vaddr + size); | |
d9cdc901 RB |
1035 | } |
1036 | ||
1037 | static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) | |
1038 | { | |
1039 | struct flush_kernel_vmap_range_args args; | |
1040 | ||
1041 | args.vaddr = (unsigned long) vaddr; | |
1042 | args.size = size; | |
1043 | ||
a9341ae2 JH |
1044 | if (size >= dcache_size) |
1045 | r4k_on_each_cpu(R4K_INDEX, | |
1046 | local_r4k_flush_kernel_vmap_range_index, NULL); | |
1047 | else | |
1048 | r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range, | |
1049 | &args); | |
d9cdc901 RB |
1050 | } |
1051 | ||
1da177e4 LT |
1052 | static inline void rm7k_erratum31(void) |
1053 | { | |
1054 | const unsigned long ic_lsize = 32; | |
1055 | unsigned long addr; | |
1056 | ||
1057 | /* RM7000 erratum #31. The icache is screwed at startup. */ | |
1058 | write_c0_taglo(0); | |
1059 | write_c0_taghi(0); | |
1060 | ||
1061 | for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { | |
1062 | __asm__ __volatile__ ( | |
d8748a3a | 1063 | ".set push\n\t" |
1da177e4 LT |
1064 | ".set noreorder\n\t" |
1065 | ".set mips3\n\t" | |
1066 | "cache\t%1, 0(%0)\n\t" | |
1067 | "cache\t%1, 0x1000(%0)\n\t" | |
1068 | "cache\t%1, 0x2000(%0)\n\t" | |
1069 | "cache\t%1, 0x3000(%0)\n\t" | |
1070 | "cache\t%2, 0(%0)\n\t" | |
1071 | "cache\t%2, 0x1000(%0)\n\t" | |
1072 | "cache\t%2, 0x2000(%0)\n\t" | |
1073 | "cache\t%2, 0x3000(%0)\n\t" | |
1074 | "cache\t%1, 0(%0)\n\t" | |
1075 | "cache\t%1, 0x1000(%0)\n\t" | |
1076 | "cache\t%1, 0x2000(%0)\n\t" | |
1077 | "cache\t%1, 0x3000(%0)\n\t" | |
d8748a3a | 1078 | ".set pop\n" |
1da177e4 LT |
1079 | : |
1080 | : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); | |
1081 | } | |
1082 | } | |
1083 | ||
e2e7f29a | 1084 | static inline int alias_74k_erratum(struct cpuinfo_mips *c) |
006a851b | 1085 | { |
9213ad77 MR |
1086 | unsigned int imp = c->processor_id & PRID_IMP_MASK; |
1087 | unsigned int rev = c->processor_id & PRID_REV_MASK; | |
e2e7f29a | 1088 | int present = 0; |
9213ad77 | 1089 | |
006a851b SH |
1090 | /* |
1091 | * Early versions of the 74K do not update the cache tags on a | |
1092 | * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG | |
e2e7f29a MR |
1093 | * aliases. In this case it is better to treat the cache as always |
1094 | * having aliases. Also disable the synonym tag update feature | |
1095 | * where available. In this case no opportunistic tag update will | |
1096 | * happen where a load causes a virtual address miss but a physical | |
1097 | * address hit during a D-cache look-up. | |
006a851b | 1098 | */ |
9213ad77 MR |
1099 | switch (imp) { |
1100 | case PRID_IMP_74K: | |
1101 | if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) | |
e2e7f29a | 1102 | present = 1; |
9213ad77 MR |
1103 | if (rev == PRID_REV_ENCODE_332(2, 4, 0)) |
1104 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); | |
1105 | break; | |
1106 | case PRID_IMP_1074K: | |
1107 | if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { | |
e2e7f29a | 1108 | present = 1; |
9213ad77 MR |
1109 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); |
1110 | } | |
1111 | break; | |
1112 | default: | |
1113 | BUG(); | |
006a851b | 1114 | } |
e2e7f29a MR |
1115 | |
1116 | return present; | |
006a851b SH |
1117 | } |
1118 | ||
d74b0172 KC |
1119 | static void b5k_instruction_hazard(void) |
1120 | { | |
1121 | __sync(); | |
1122 | __sync(); | |
1123 | __asm__ __volatile__( | |
1124 | " nop; nop; nop; nop; nop; nop; nop; nop\n" | |
1125 | " nop; nop; nop; nop; nop; nop; nop; nop\n" | |
1126 | " nop; nop; nop; nop; nop; nop; nop; nop\n" | |
1127 | " nop; nop; nop; nop; nop; nop; nop; nop\n" | |
1128 | : : : "memory"); | |
1129 | } | |
1130 | ||
078a55fc | 1131 | static char *way_string[] = { NULL, "direct mapped", "2-way", |
1e18ac7a PB |
1132 | "3-way", "4-way", "5-way", "6-way", "7-way", "8-way", |
1133 | "9-way", "10-way", "11-way", "12-way", | |
1134 | "13-way", "14-way", "15-way", "16-way", | |
1da177e4 LT |
1135 | }; |
1136 | ||
078a55fc | 1137 | static void probe_pcache(void) |
1da177e4 LT |
1138 | { |
1139 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1140 | unsigned int config = read_c0_config(); | |
1141 | unsigned int prid = read_c0_prid(); | |
e2e7f29a | 1142 | int has_74k_erratum = 0; |
1da177e4 LT |
1143 | unsigned long config1; |
1144 | unsigned int lsize; | |
1145 | ||
69f24d17 | 1146 | switch (current_cpu_type()) { |
1da177e4 LT |
1147 | case CPU_R4600: /* QED style two way caches? */ |
1148 | case CPU_R4700: | |
1149 | case CPU_R5000: | |
1150 | case CPU_NEVADA: | |
1151 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
1152 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1153 | c->icache.ways = 2; | |
3c68da79 | 1154 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
1155 | |
1156 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1157 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1158 | c->dcache.ways = 2; | |
3c68da79 | 1159 | c->dcache.waybit= __ffs(dcache_size/2); |
1da177e4 LT |
1160 | |
1161 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
1162 | break; | |
1163 | ||
1164 | case CPU_R5432: | |
1165 | case CPU_R5500: | |
1166 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
1167 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1168 | c->icache.ways = 2; | |
1169 | c->icache.waybit= 0; | |
1170 | ||
1171 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1172 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1173 | c->dcache.ways = 2; | |
1174 | c->dcache.waybit = 0; | |
1175 | ||
5864810b | 1176 | c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; |
1da177e4 LT |
1177 | break; |
1178 | ||
1179 | case CPU_TX49XX: | |
1180 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
1181 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1182 | c->icache.ways = 4; | |
1183 | c->icache.waybit= 0; | |
1184 | ||
1185 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1186 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1187 | c->dcache.ways = 4; | |
1188 | c->dcache.waybit = 0; | |
1189 | ||
1190 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
de862b48 | 1191 | c->options |= MIPS_CPU_PREFETCH; |
1da177e4 LT |
1192 | break; |
1193 | ||
1194 | case CPU_R4000PC: | |
1195 | case CPU_R4000SC: | |
1196 | case CPU_R4000MC: | |
1197 | case CPU_R4400PC: | |
1198 | case CPU_R4400SC: | |
1199 | case CPU_R4400MC: | |
1200 | case CPU_R4300: | |
1201 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
1202 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1203 | c->icache.ways = 1; | |
70342287 | 1204 | c->icache.waybit = 0; /* doesn't matter */ |
1da177e4 LT |
1205 | |
1206 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1207 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1208 | c->dcache.ways = 1; | |
1209 | c->dcache.waybit = 0; /* does not matter */ | |
1210 | ||
1211 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
1212 | break; | |
1213 | ||
1214 | case CPU_R10000: | |
1215 | case CPU_R12000: | |
44d921b2 | 1216 | case CPU_R14000: |
30577391 | 1217 | case CPU_R16000: |
1da177e4 LT |
1218 | icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); |
1219 | c->icache.linesz = 64; | |
1220 | c->icache.ways = 2; | |
1221 | c->icache.waybit = 0; | |
1222 | ||
1223 | dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); | |
1224 | c->dcache.linesz = 32; | |
1225 | c->dcache.ways = 2; | |
1226 | c->dcache.waybit = 0; | |
1227 | ||
1228 | c->options |= MIPS_CPU_PREFETCH; | |
1229 | break; | |
1230 | ||
1231 | case CPU_VR4133: | |
2874fe55 | 1232 | write_c0_config(config & ~VR41_CONF_P4K); |
1da177e4 LT |
1233 | case CPU_VR4131: |
1234 | /* Workaround for cache instruction bug of VR4131 */ | |
1235 | if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || | |
1236 | c->processor_id == 0x0c82U) { | |
4e8ab361 YY |
1237 | config |= 0x00400000U; |
1238 | if (c->processor_id == 0x0c80U) | |
1239 | config |= VR41_CONF_BP; | |
1da177e4 | 1240 | write_c0_config(config); |
1058ecda YY |
1241 | } else |
1242 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
1243 | ||
1da177e4 LT |
1244 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); |
1245 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1246 | c->icache.ways = 2; | |
3c68da79 | 1247 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
1248 | |
1249 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
1250 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1251 | c->dcache.ways = 2; | |
3c68da79 | 1252 | c->dcache.waybit = __ffs(dcache_size/2); |
1da177e4 LT |
1253 | break; |
1254 | ||
1255 | case CPU_VR41XX: | |
1256 | case CPU_VR4111: | |
1257 | case CPU_VR4121: | |
1258 | case CPU_VR4122: | |
1259 | case CPU_VR4181: | |
1260 | case CPU_VR4181A: | |
1261 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); | |
1262 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1263 | c->icache.ways = 1; | |
70342287 | 1264 | c->icache.waybit = 0; /* doesn't matter */ |
1da177e4 LT |
1265 | |
1266 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
1267 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1268 | c->dcache.ways = 1; | |
1269 | c->dcache.waybit = 0; /* does not matter */ | |
1270 | ||
1271 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
1272 | break; | |
1273 | ||
1274 | case CPU_RM7000: | |
1275 | rm7k_erratum31(); | |
1276 | ||
1da177e4 LT |
1277 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
1278 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1279 | c->icache.ways = 4; | |
3c68da79 | 1280 | c->icache.waybit = __ffs(icache_size / c->icache.ways); |
1da177e4 LT |
1281 | |
1282 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1283 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1284 | c->dcache.ways = 4; | |
3c68da79 | 1285 | c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); |
1da177e4 | 1286 | |
1da177e4 | 1287 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
1da177e4 LT |
1288 | c->options |= MIPS_CPU_PREFETCH; |
1289 | break; | |
1290 | ||
2a21c730 FZ |
1291 | case CPU_LOONGSON2: |
1292 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
1293 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1294 | if (prid & 0x3) | |
1295 | c->icache.ways = 4; | |
1296 | else | |
1297 | c->icache.ways = 2; | |
1298 | c->icache.waybit = 0; | |
1299 | ||
1300 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1301 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1302 | if (prid & 0x3) | |
1303 | c->dcache.ways = 4; | |
1304 | else | |
1305 | c->dcache.ways = 2; | |
1306 | c->dcache.waybit = 0; | |
1307 | break; | |
1308 | ||
c579d310 HC |
1309 | case CPU_LOONGSON3: |
1310 | config1 = read_c0_config1(); | |
1311 | lsize = (config1 >> 19) & 7; | |
1312 | if (lsize) | |
1313 | c->icache.linesz = 2 << lsize; | |
1314 | else | |
1315 | c->icache.linesz = 0; | |
1316 | c->icache.sets = 64 << ((config1 >> 22) & 7); | |
1317 | c->icache.ways = 1 + ((config1 >> 16) & 7); | |
1318 | icache_size = c->icache.sets * | |
1319 | c->icache.ways * | |
1320 | c->icache.linesz; | |
1321 | c->icache.waybit = 0; | |
1322 | ||
1323 | lsize = (config1 >> 10) & 7; | |
1324 | if (lsize) | |
1325 | c->dcache.linesz = 2 << lsize; | |
1326 | else | |
1327 | c->dcache.linesz = 0; | |
1328 | c->dcache.sets = 64 << ((config1 >> 13) & 7); | |
1329 | c->dcache.ways = 1 + ((config1 >> 7) & 7); | |
1330 | dcache_size = c->dcache.sets * | |
1331 | c->dcache.ways * | |
1332 | c->dcache.linesz; | |
1333 | c->dcache.waybit = 0; | |
1e820da3 HC |
1334 | if ((prid & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2) |
1335 | c->options |= MIPS_CPU_PREFETCH; | |
c579d310 HC |
1336 | break; |
1337 | ||
18a8cd63 DD |
1338 | case CPU_CAVIUM_OCTEON3: |
1339 | /* For now lie about the number of ways. */ | |
1340 | c->icache.linesz = 128; | |
1341 | c->icache.sets = 16; | |
1342 | c->icache.ways = 8; | |
1343 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1344 | icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; | |
1345 | ||
1346 | c->dcache.linesz = 128; | |
1347 | c->dcache.ways = 8; | |
1348 | c->dcache.sets = 8; | |
1349 | dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; | |
1350 | c->options |= MIPS_CPU_PREFETCH; | |
1351 | break; | |
1352 | ||
1da177e4 LT |
1353 | default: |
1354 | if (!(config & MIPS_CONF_M)) | |
1355 | panic("Don't know how to probe P-caches on this cpu."); | |
1356 | ||
1357 | /* | |
1358 | * So we seem to be a MIPS32 or MIPS64 CPU | |
1359 | * So let's probe the I-cache ... | |
1360 | */ | |
1361 | config1 = read_c0_config1(); | |
1362 | ||
175cba8c MC |
1363 | lsize = (config1 >> 19) & 7; |
1364 | ||
1365 | /* IL == 7 is reserved */ | |
1366 | if (lsize == 7) | |
1367 | panic("Invalid icache line size"); | |
1368 | ||
1369 | c->icache.linesz = lsize ? 2 << lsize : 0; | |
1370 | ||
dc34b05f | 1371 | c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); |
1da177e4 LT |
1372 | c->icache.ways = 1 + ((config1 >> 16) & 7); |
1373 | ||
1374 | icache_size = c->icache.sets * | |
70342287 RB |
1375 | c->icache.ways * |
1376 | c->icache.linesz; | |
3c68da79 | 1377 | c->icache.waybit = __ffs(icache_size/c->icache.ways); |
1da177e4 | 1378 | |
4b34bca0 | 1379 | if (config & MIPS_CONF_VI) |
1da177e4 LT |
1380 | c->icache.flags |= MIPS_CACHE_VTAG; |
1381 | ||
1382 | /* | |
1383 | * Now probe the MIPS32 / MIPS64 data cache. | |
1384 | */ | |
1385 | c->dcache.flags = 0; | |
1386 | ||
175cba8c MC |
1387 | lsize = (config1 >> 10) & 7; |
1388 | ||
1389 | /* DL == 7 is reserved */ | |
1390 | if (lsize == 7) | |
1391 | panic("Invalid dcache line size"); | |
1392 | ||
1393 | c->dcache.linesz = lsize ? 2 << lsize : 0; | |
1394 | ||
dc34b05f | 1395 | c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); |
1da177e4 LT |
1396 | c->dcache.ways = 1 + ((config1 >> 7) & 7); |
1397 | ||
1398 | dcache_size = c->dcache.sets * | |
70342287 RB |
1399 | c->dcache.ways * |
1400 | c->dcache.linesz; | |
3c68da79 | 1401 | c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); |
1da177e4 LT |
1402 | |
1403 | c->options |= MIPS_CPU_PREFETCH; | |
1404 | break; | |
1405 | } | |
1406 | ||
1407 | /* | |
1408 | * Processor configuration sanity check for the R4000SC erratum | |
70342287 | 1409 | * #5. With page sizes larger than 32kB there is no possibility |
1da177e4 LT |
1410 | * to get a VCE exception anymore so we don't care about this |
1411 | * misconfiguration. The case is rather theoretical anyway; | |
1412 | * presumably no vendor is shipping his hardware in the "bad" | |
1413 | * configuration. | |
1414 | */ | |
8ff374b9 MR |
1415 | if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 && |
1416 | (prid & PRID_REV_MASK) < PRID_REV_R4400 && | |
1da177e4 LT |
1417 | !(config & CONF_SC) && c->icache.linesz != 16 && |
1418 | PAGE_SIZE <= 0x8000) | |
1419 | panic("Improper R4000SC processor configuration detected"); | |
1420 | ||
1421 | /* compute a couple of other cache variables */ | |
1422 | c->icache.waysize = icache_size / c->icache.ways; | |
1423 | c->dcache.waysize = dcache_size / c->dcache.ways; | |
1424 | ||
73f40352 CD |
1425 | c->icache.sets = c->icache.linesz ? |
1426 | icache_size / (c->icache.linesz * c->icache.ways) : 0; | |
1427 | c->dcache.sets = c->dcache.linesz ? | |
1428 | dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; | |
1da177e4 LT |
1429 | |
1430 | /* | |
30577391 JK |
1431 | * R1x000 P-caches are odd in a positive way. They're 32kB 2-way |
1432 | * virtually indexed so normally would suffer from aliases. So | |
1da177e4 LT |
1433 | * normally they'd suffer from aliases but magic in the hardware deals |
1434 | * with that for us so we don't need to take care ourselves. | |
1435 | */ | |
69f24d17 | 1436 | switch (current_cpu_type()) { |
a95970f3 | 1437 | case CPU_20KC: |
505403b6 | 1438 | case CPU_25KF: |
641e97f3 RB |
1439 | case CPU_SB1: |
1440 | case CPU_SB1A: | |
efa0f81c | 1441 | case CPU_XLR: |
de62893b | 1442 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
641e97f3 RB |
1443 | break; |
1444 | ||
d1e344e5 RB |
1445 | case CPU_R10000: |
1446 | case CPU_R12000: | |
44d921b2 | 1447 | case CPU_R14000: |
30577391 | 1448 | case CPU_R16000: |
d1e344e5 | 1449 | break; |
641e97f3 | 1450 | |
bf4aac07 MR |
1451 | case CPU_74K: |
1452 | case CPU_1074K: | |
e2e7f29a | 1453 | has_74k_erratum = alias_74k_erratum(c); |
bf4aac07 | 1454 | /* Fall through. */ |
113c62d9 | 1455 | case CPU_M14KC: |
f8fa4811 | 1456 | case CPU_M14KEC: |
d1e344e5 | 1457 | case CPU_24K: |
98a41de9 | 1458 | case CPU_34K: |
39b8d525 | 1459 | case CPU_1004K: |
26ab96df | 1460 | case CPU_INTERAPTIV: |
aced4cbd | 1461 | case CPU_P5600: |
708ac4b8 | 1462 | case CPU_PROAPTIV: |
f36c4720 | 1463 | case CPU_M5150: |
4695089f | 1464 | case CPU_QEMU_GENERIC: |
4e88a862 | 1465 | case CPU_I6400: |
1091bfa2 | 1466 | case CPU_P6600: |
1dbf6a81 | 1467 | case CPU_M6250: |
02dc6bfb MC |
1468 | if (!(read_c0_config7() & MIPS_CONF7_IAR) && |
1469 | (c->icache.waysize > PAGE_SIZE)) | |
1470 | c->icache.flags |= MIPS_CACHE_ALIASES; | |
e2e7f29a | 1471 | if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) { |
02dc6bfb MC |
1472 | /* |
1473 | * Effectively physically indexed dcache, | |
1474 | * thus no virtual aliases. | |
1475 | */ | |
beab375a RB |
1476 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
1477 | break; | |
1478 | } | |
d1e344e5 | 1479 | default: |
e2e7f29a | 1480 | if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) |
beab375a | 1481 | c->dcache.flags |= MIPS_CACHE_ALIASES; |
d1e344e5 | 1482 | } |
1da177e4 | 1483 | |
69f24d17 | 1484 | switch (current_cpu_type()) { |
1da177e4 LT |
1485 | case CPU_20KC: |
1486 | /* | |
1487 | * Some older 20Kc chips doesn't have the 'VI' bit in | |
1488 | * the config register. | |
1489 | */ | |
1490 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1491 | break; | |
1492 | ||
270717a8 | 1493 | case CPU_ALCHEMY: |
47f2ac50 | 1494 | case CPU_I6400: |
1da177e4 LT |
1495 | c->icache.flags |= MIPS_CACHE_IC_F_DC; |
1496 | break; | |
1da177e4 | 1497 | |
c130d2fd FF |
1498 | case CPU_BMIPS5000: |
1499 | c->icache.flags |= MIPS_CACHE_IC_F_DC; | |
73c4ca04 FF |
1500 | /* Cache aliases are handled in hardware; allow HIGHMEM */ |
1501 | c->dcache.flags &= ~MIPS_CACHE_ALIASES; | |
c130d2fd FF |
1502 | break; |
1503 | ||
14bd8c08 RB |
1504 | case CPU_LOONGSON2: |
1505 | /* | |
1506 | * LOONGSON2 has 4 way icache, but when using indexed cache op, | |
1507 | * one op will act on all 4 ways | |
1508 | */ | |
1509 | c->icache.ways = 1; | |
1510 | } | |
2a21c730 | 1511 | |
1da177e4 LT |
1512 | printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", |
1513 | icache_size >> 10, | |
7fc7316a | 1514 | c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", |
1da177e4 LT |
1515 | way_string[c->icache.ways], c->icache.linesz); |
1516 | ||
64bfca5c RB |
1517 | printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", |
1518 | dcache_size >> 10, way_string[c->dcache.ways], | |
1519 | (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", | |
1520 | (c->dcache.flags & MIPS_CACHE_ALIASES) ? | |
1521 | "cache aliases" : "no aliases", | |
1522 | c->dcache.linesz); | |
1da177e4 LT |
1523 | } |
1524 | ||
b2edcfc8 HC |
1525 | static void probe_vcache(void) |
1526 | { | |
1527 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1528 | unsigned int config2, lsize; | |
1529 | ||
1530 | if (current_cpu_type() != CPU_LOONGSON3) | |
1531 | return; | |
1532 | ||
1533 | config2 = read_c0_config2(); | |
1534 | if ((lsize = ((config2 >> 20) & 15))) | |
1535 | c->vcache.linesz = 2 << lsize; | |
1536 | else | |
1537 | c->vcache.linesz = lsize; | |
1538 | ||
1539 | c->vcache.sets = 64 << ((config2 >> 24) & 15); | |
1540 | c->vcache.ways = 1 + ((config2 >> 16) & 15); | |
1541 | ||
1542 | vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz; | |
1543 | ||
1544 | c->vcache.waybit = 0; | |
1545 | ||
1546 | pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n", | |
1547 | vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz); | |
1548 | } | |
1549 | ||
1da177e4 LT |
1550 | /* |
1551 | * If you even _breathe_ on this function, look at the gcc output and make sure | |
1552 | * it does not pop things on and off the stack for the cache sizing loop that | |
1553 | * executes in KSEG1 space or else you will crash and burn badly. You have | |
1554 | * been warned. | |
1555 | */ | |
078a55fc | 1556 | static int probe_scache(void) |
1da177e4 | 1557 | { |
1da177e4 LT |
1558 | unsigned long flags, addr, begin, end, pow2; |
1559 | unsigned int config = read_c0_config(); | |
1560 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1da177e4 LT |
1561 | |
1562 | if (config & CONF_SC) | |
1563 | return 0; | |
1564 | ||
e001e528 | 1565 | begin = (unsigned long) &_stext; |
1da177e4 LT |
1566 | begin &= ~((4 * 1024 * 1024) - 1); |
1567 | end = begin + (4 * 1024 * 1024); | |
1568 | ||
1569 | /* | |
1570 | * This is such a bitch, you'd think they would make it easy to do | |
1571 | * this. Away you daemons of stupidity! | |
1572 | */ | |
1573 | local_irq_save(flags); | |
1574 | ||
1575 | /* Fill each size-multiple cache line with a valid tag. */ | |
1576 | pow2 = (64 * 1024); | |
1577 | for (addr = begin; addr < end; addr = (begin + pow2)) { | |
1578 | unsigned long *p = (unsigned long *) addr; | |
1579 | __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ | |
1580 | pow2 <<= 1; | |
1581 | } | |
1582 | ||
1583 | /* Load first line with zero (therefore invalid) tag. */ | |
1584 | write_c0_taglo(0); | |
1585 | write_c0_taghi(0); | |
1586 | __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ | |
1587 | cache_op(Index_Store_Tag_I, begin); | |
1588 | cache_op(Index_Store_Tag_D, begin); | |
1589 | cache_op(Index_Store_Tag_SD, begin); | |
1590 | ||
1591 | /* Now search for the wrap around point. */ | |
1592 | pow2 = (128 * 1024); | |
1da177e4 LT |
1593 | for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { |
1594 | cache_op(Index_Load_Tag_SD, addr); | |
1595 | __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ | |
1596 | if (!read_c0_taglo()) | |
1597 | break; | |
1598 | pow2 <<= 1; | |
1599 | } | |
1600 | local_irq_restore(flags); | |
1601 | addr -= begin; | |
1602 | ||
1603 | scache_size = addr; | |
1604 | c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); | |
1605 | c->scache.ways = 1; | |
755af33b | 1606 | c->scache.waybit = 0; /* does not matter */ |
1da177e4 LT |
1607 | |
1608 | return 1; | |
1609 | } | |
1610 | ||
2a21c730 FZ |
1611 | static void __init loongson2_sc_init(void) |
1612 | { | |
1613 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1614 | ||
1615 | scache_size = 512*1024; | |
1616 | c->scache.linesz = 32; | |
1617 | c->scache.ways = 4; | |
1618 | c->scache.waybit = 0; | |
1619 | c->scache.waysize = scache_size / (c->scache.ways); | |
1620 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1621 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1622 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1623 | ||
1624 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1625 | } | |
2a21c730 | 1626 | |
c579d310 HC |
1627 | static void __init loongson3_sc_init(void) |
1628 | { | |
1629 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1630 | unsigned int config2, lsize; | |
1631 | ||
1632 | config2 = read_c0_config2(); | |
1633 | lsize = (config2 >> 4) & 15; | |
1634 | if (lsize) | |
1635 | c->scache.linesz = 2 << lsize; | |
1636 | else | |
1637 | c->scache.linesz = 0; | |
1638 | c->scache.sets = 64 << ((config2 >> 8) & 15); | |
1639 | c->scache.ways = 1 + (config2 & 15); | |
1640 | ||
1641 | scache_size = c->scache.sets * | |
1642 | c->scache.ways * | |
1643 | c->scache.linesz; | |
1644 | /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */ | |
1645 | scache_size *= 4; | |
1646 | c->scache.waybit = 0; | |
1647 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1648 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1649 | if (scache_size) | |
1650 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1651 | return; | |
1652 | } | |
1653 | ||
1da177e4 LT |
1654 | extern int r5k_sc_init(void); |
1655 | extern int rm7k_sc_init(void); | |
9318c51a | 1656 | extern int mips_sc_init(void); |
1da177e4 | 1657 | |
078a55fc | 1658 | static void setup_scache(void) |
1da177e4 LT |
1659 | { |
1660 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1661 | unsigned int config = read_c0_config(); | |
1da177e4 LT |
1662 | int sc_present = 0; |
1663 | ||
1664 | /* | |
1665 | * Do the probing thing on R4000SC and R4400SC processors. Other | |
1666 | * processors don't have a S-cache that would be relevant to the | |
603e82ed | 1667 | * Linux memory management. |
1da177e4 | 1668 | */ |
69f24d17 | 1669 | switch (current_cpu_type()) { |
1da177e4 LT |
1670 | case CPU_R4000SC: |
1671 | case CPU_R4000MC: | |
1672 | case CPU_R4400SC: | |
1673 | case CPU_R4400MC: | |
ba5187db | 1674 | sc_present = run_uncached(probe_scache); |
1da177e4 LT |
1675 | if (sc_present) |
1676 | c->options |= MIPS_CPU_CACHE_CDEX_S; | |
1677 | break; | |
1678 | ||
1679 | case CPU_R10000: | |
1680 | case CPU_R12000: | |
44d921b2 | 1681 | case CPU_R14000: |
30577391 | 1682 | case CPU_R16000: |
1da177e4 LT |
1683 | scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); |
1684 | c->scache.linesz = 64 << ((config >> 13) & 1); | |
1685 | c->scache.ways = 2; | |
1686 | c->scache.waybit= 0; | |
1687 | sc_present = 1; | |
1688 | break; | |
1689 | ||
1690 | case CPU_R5000: | |
1691 | case CPU_NEVADA: | |
1692 | #ifdef CONFIG_R5000_CPU_SCACHE | |
1693 | r5k_sc_init(); | |
1694 | #endif | |
70342287 | 1695 | return; |
1da177e4 LT |
1696 | |
1697 | case CPU_RM7000: | |
1da177e4 LT |
1698 | #ifdef CONFIG_RM7000_CPU_SCACHE |
1699 | rm7k_sc_init(); | |
1700 | #endif | |
1701 | return; | |
1702 | ||
2a21c730 FZ |
1703 | case CPU_LOONGSON2: |
1704 | loongson2_sc_init(); | |
1705 | return; | |
14bd8c08 | 1706 | |
c579d310 HC |
1707 | case CPU_LOONGSON3: |
1708 | loongson3_sc_init(); | |
1709 | return; | |
1710 | ||
18a8cd63 | 1711 | case CPU_CAVIUM_OCTEON3: |
a3d4fb2d J |
1712 | case CPU_XLP: |
1713 | /* don't need to worry about L2, fully coherent */ | |
1714 | return; | |
2a21c730 | 1715 | |
1da177e4 | 1716 | default: |
adb37892 | 1717 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | |
b5ad2c21 MC |
1718 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 | |
1719 | MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) { | |
9318c51a CD |
1720 | #ifdef CONFIG_MIPS_CPU_SCACHE |
1721 | if (mips_sc_init ()) { | |
1722 | scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; | |
1723 | printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", | |
1724 | scache_size >> 10, | |
1725 | way_string[c->scache.ways], c->scache.linesz); | |
1726 | } | |
1727 | #else | |
1728 | if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) | |
1729 | panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); | |
1730 | #endif | |
1731 | return; | |
1732 | } | |
1da177e4 LT |
1733 | sc_present = 0; |
1734 | } | |
1735 | ||
1736 | if (!sc_present) | |
1737 | return; | |
1738 | ||
1da177e4 LT |
1739 | /* compute a couple of other cache variables */ |
1740 | c->scache.waysize = scache_size / c->scache.ways; | |
1741 | ||
1742 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1743 | ||
1744 | printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1745 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1746 | ||
fc5d2d27 | 1747 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
1da177e4 LT |
1748 | } |
1749 | ||
9370b351 SS |
1750 | void au1x00_fixup_config_od(void) |
1751 | { | |
1752 | /* | |
1753 | * c0_config.od (bit 19) was write only (and read as 0) | |
1754 | * on the early revisions of Alchemy SOCs. It disables the bus | |
1755 | * transaction overlapping and needs to be set to fix various errata. | |
1756 | */ | |
1757 | switch (read_c0_prid()) { | |
1758 | case 0x00030100: /* Au1000 DA */ | |
1759 | case 0x00030201: /* Au1000 HA */ | |
1760 | case 0x00030202: /* Au1000 HB */ | |
1761 | case 0x01030200: /* Au1500 AB */ | |
1762 | /* | |
1763 | * Au1100 errata actually keeps silence about this bit, so we set it | |
1764 | * just in case for those revisions that require it to be set according | |
270717a8 | 1765 | * to the (now gone) cpu table. |
9370b351 SS |
1766 | */ |
1767 | case 0x02030200: /* Au1100 AB */ | |
1768 | case 0x02030201: /* Au1100 BA */ | |
1769 | case 0x02030202: /* Au1100 BC */ | |
1770 | set_c0_config(1 << 19); | |
1771 | break; | |
1772 | } | |
1773 | } | |
1774 | ||
89052bd7 RB |
1775 | /* CP0 hazard avoidance. */ |
1776 | #define NXP_BARRIER() \ | |
1777 | __asm__ __volatile__( \ | |
1778 | ".set noreorder\n\t" \ | |
1779 | "nop; nop; nop; nop; nop; nop;\n\t" \ | |
1780 | ".set reorder\n\t") | |
1781 | ||
1782 | static void nxp_pr4450_fixup_config(void) | |
1783 | { | |
1784 | unsigned long config0; | |
1785 | ||
1786 | config0 = read_c0_config(); | |
1787 | ||
1788 | /* clear all three cache coherency fields */ | |
1789 | config0 &= ~(0x7 | (7 << 25) | (7 << 28)); | |
1790 | config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | | |
1791 | ((_page_cachable_default >> _CACHE_SHIFT) << 25) | | |
1792 | ((_page_cachable_default >> _CACHE_SHIFT) << 28)); | |
1793 | write_c0_config(config0); | |
1794 | NXP_BARRIER(); | |
1795 | } | |
1796 | ||
078a55fc | 1797 | static int cca = -1; |
35133692 CD |
1798 | |
1799 | static int __init cca_setup(char *str) | |
1800 | { | |
1801 | get_option(&str, &cca); | |
1802 | ||
b5b64f2b | 1803 | return 0; |
35133692 CD |
1804 | } |
1805 | ||
b5b64f2b | 1806 | early_param("cca", cca_setup); |
35133692 | 1807 | |
078a55fc | 1808 | static void coherency_setup(void) |
1da177e4 | 1809 | { |
35133692 CD |
1810 | if (cca < 0 || cca > 7) |
1811 | cca = read_c0_config() & CONF_CM_CMASK; | |
1812 | _page_cachable_default = cca << _CACHE_SHIFT; | |
1813 | ||
1814 | pr_debug("Using cache attribute %d\n", cca); | |
1815 | change_c0_config(CONF_CM_CMASK, cca); | |
1da177e4 LT |
1816 | |
1817 | /* | |
1818 | * c0_status.cu=0 specifies that updates by the sc instruction use | |
1819 | * the coherency mode specified by the TLB; 1 means cachable | |
1820 | * coherent update on write will be used. Not all processors have | |
1821 | * this bit and; some wire it to zero, others like Toshiba had the | |
1822 | * silly idea of putting something else there ... | |
1823 | */ | |
10cc3529 | 1824 | switch (current_cpu_type()) { |
1da177e4 LT |
1825 | case CPU_R4000PC: |
1826 | case CPU_R4000SC: | |
1827 | case CPU_R4000MC: | |
1828 | case CPU_R4400PC: | |
1829 | case CPU_R4400SC: | |
1830 | case CPU_R4400MC: | |
1831 | clear_c0_config(CONF_CU); | |
1832 | break; | |
9370b351 | 1833 | /* |
df586d59 | 1834 | * We need to catch the early Alchemy SOCs with |
270717a8 ML |
1835 | * the write-only co_config.od bit and set it back to one on: |
1836 | * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB | |
9370b351 | 1837 | */ |
270717a8 | 1838 | case CPU_ALCHEMY: |
9370b351 SS |
1839 | au1x00_fixup_config_od(); |
1840 | break; | |
89052bd7 RB |
1841 | |
1842 | case PRID_IMP_PR4450: | |
1843 | nxp_pr4450_fixup_config(); | |
1844 | break; | |
1da177e4 LT |
1845 | } |
1846 | } | |
1847 | ||
078a55fc | 1848 | static void r4k_cache_error_setup(void) |
1da177e4 | 1849 | { |
641e97f3 RB |
1850 | extern char __weak except_vec2_generic; |
1851 | extern char __weak except_vec2_sb1; | |
1da177e4 | 1852 | |
69f24d17 | 1853 | switch (current_cpu_type()) { |
641e97f3 RB |
1854 | case CPU_SB1: |
1855 | case CPU_SB1A: | |
1856 | set_uncached_handler(0x100, &except_vec2_sb1, 0x80); | |
1857 | break; | |
1858 | ||
1859 | default: | |
1860 | set_uncached_handler(0x100, &except_vec2_generic, 0x80); | |
1861 | break; | |
1862 | } | |
9cd9669b DD |
1863 | } |
1864 | ||
078a55fc | 1865 | void r4k_cache_init(void) |
9cd9669b DD |
1866 | { |
1867 | extern void build_clear_page(void); | |
1868 | extern void build_copy_page(void); | |
1869 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1da177e4 LT |
1870 | |
1871 | probe_pcache(); | |
b2edcfc8 | 1872 | probe_vcache(); |
1da177e4 LT |
1873 | setup_scache(); |
1874 | ||
1da177e4 LT |
1875 | r4k_blast_dcache_page_setup(); |
1876 | r4k_blast_dcache_page_indexed_setup(); | |
1877 | r4k_blast_dcache_setup(); | |
1878 | r4k_blast_icache_page_setup(); | |
1879 | r4k_blast_icache_page_indexed_setup(); | |
1880 | r4k_blast_icache_setup(); | |
1881 | r4k_blast_scache_page_setup(); | |
1882 | r4k_blast_scache_page_indexed_setup(); | |
1883 | r4k_blast_scache_setup(); | |
4caa906e LY |
1884 | #ifdef CONFIG_EVA |
1885 | r4k_blast_dcache_user_page_setup(); | |
1886 | r4k_blast_icache_user_page_setup(); | |
1887 | #endif | |
1da177e4 LT |
1888 | |
1889 | /* | |
1890 | * Some MIPS32 and MIPS64 processors have physically indexed caches. | |
1891 | * This code supports virtually indexed processors and will be | |
1892 | * unnecessarily inefficient on physically indexed processors. | |
1893 | */ | |
cb80b2a3 | 1894 | if (c->dcache.linesz && cpu_has_dc_aliases) |
73f40352 CD |
1895 | shm_align_mask = max_t( unsigned long, |
1896 | c->dcache.sets * c->dcache.linesz - 1, | |
1897 | PAGE_SIZE - 1); | |
1898 | else | |
1899 | shm_align_mask = PAGE_SIZE-1; | |
9c5a3d72 RB |
1900 | |
1901 | __flush_cache_vmap = r4k__flush_cache_vmap; | |
1902 | __flush_cache_vunmap = r4k__flush_cache_vunmap; | |
1903 | ||
db813fe5 | 1904 | flush_cache_all = cache_noop; |
1da177e4 LT |
1905 | __flush_cache_all = r4k___flush_cache_all; |
1906 | flush_cache_mm = r4k_flush_cache_mm; | |
1907 | flush_cache_page = r4k_flush_cache_page; | |
1da177e4 LT |
1908 | flush_cache_range = r4k_flush_cache_range; |
1909 | ||
d9cdc901 RB |
1910 | __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; |
1911 | ||
1da177e4 LT |
1912 | flush_cache_sigtramp = r4k_flush_cache_sigtramp; |
1913 | flush_icache_all = r4k_flush_icache_all; | |
7e3bfc7c | 1914 | local_flush_data_cache_page = local_r4k_flush_data_cache_page; |
1da177e4 LT |
1915 | flush_data_cache_page = r4k_flush_data_cache_page; |
1916 | flush_icache_range = r4k_flush_icache_range; | |
e0cee3ee | 1917 | local_flush_icache_range = local_r4k_flush_icache_range; |
1da177e4 | 1918 | |
8005711c | 1919 | #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) |
39b8d525 RB |
1920 | if (coherentio) { |
1921 | _dma_cache_wback_inv = (void *)cache_noop; | |
1922 | _dma_cache_wback = (void *)cache_noop; | |
1923 | _dma_cache_inv = (void *)cache_noop; | |
1924 | } else { | |
1925 | _dma_cache_wback_inv = r4k_dma_cache_wback_inv; | |
1926 | _dma_cache_wback = r4k_dma_cache_wback_inv; | |
1927 | _dma_cache_inv = r4k_dma_cache_inv; | |
1928 | } | |
1da177e4 LT |
1929 | #endif |
1930 | ||
1da177e4 LT |
1931 | build_clear_page(); |
1932 | build_copy_page(); | |
b6d92b4a SH |
1933 | |
1934 | /* | |
1935 | * We want to run CMP kernels on core with and without coherent | |
1936 | * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether | |
1937 | * or not to flush caches. | |
1938 | */ | |
1d40cfcd | 1939 | local_r4k___flush_cache_all(NULL); |
b6d92b4a | 1940 | |
1d40cfcd | 1941 | coherency_setup(); |
9cd9669b | 1942 | board_cache_error_setup = r4k_cache_error_setup; |
d74b0172 KC |
1943 | |
1944 | /* | |
1945 | * Per-CPU overrides | |
1946 | */ | |
1947 | switch (current_cpu_type()) { | |
1948 | case CPU_BMIPS4350: | |
1949 | case CPU_BMIPS4380: | |
1950 | /* No IPI is needed because all CPUs share the same D$ */ | |
1951 | flush_data_cache_page = r4k_blast_dcache_page; | |
1952 | break; | |
1953 | case CPU_BMIPS5000: | |
1954 | /* We lose our superpowers if L2 is disabled */ | |
1955 | if (c->scache.flags & MIPS_CACHE_NOT_PRESENT) | |
1956 | break; | |
1957 | ||
1958 | /* I$ fills from D$ just by emptying the write buffers */ | |
1959 | flush_cache_page = (void *)b5k_instruction_hazard; | |
1960 | flush_cache_range = (void *)b5k_instruction_hazard; | |
1961 | flush_cache_sigtramp = (void *)b5k_instruction_hazard; | |
1962 | local_flush_data_cache_page = (void *)b5k_instruction_hazard; | |
1963 | flush_data_cache_page = (void *)b5k_instruction_hazard; | |
1964 | flush_icache_range = (void *)b5k_instruction_hazard; | |
1965 | local_flush_icache_range = (void *)b5k_instruction_hazard; | |
1966 | ||
d74b0172 KC |
1967 | |
1968 | /* Optimization: an L2 flush implicitly flushes the L1 */ | |
1969 | current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1970 | break; | |
37fbe8fa HC |
1971 | case CPU_LOONGSON3: |
1972 | /* Loongson-3 maintains cache coherency by hardware */ | |
1973 | __flush_cache_all = cache_noop; | |
1974 | __flush_cache_vmap = cache_noop; | |
1975 | __flush_cache_vunmap = cache_noop; | |
1976 | __flush_kernel_vmap_range = (void *)cache_noop; | |
1977 | flush_cache_mm = (void *)cache_noop; | |
1978 | flush_cache_page = (void *)cache_noop; | |
1979 | flush_cache_range = (void *)cache_noop; | |
1980 | flush_cache_sigtramp = (void *)cache_noop; | |
1981 | flush_icache_all = (void *)cache_noop; | |
1982 | flush_data_cache_page = (void *)cache_noop; | |
1983 | local_flush_data_cache_page = (void *)cache_noop; | |
1984 | break; | |
d74b0172 | 1985 | } |
1da177e4 | 1986 | } |
61d73044 JH |
1987 | |
1988 | static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd, | |
1989 | void *v) | |
1990 | { | |
1991 | switch (cmd) { | |
1992 | case CPU_PM_ENTER_FAILED: | |
1993 | case CPU_PM_EXIT: | |
1994 | coherency_setup(); | |
1995 | break; | |
1996 | } | |
1997 | ||
1998 | return NOTIFY_OK; | |
1999 | } | |
2000 | ||
2001 | static struct notifier_block r4k_cache_pm_notifier_block = { | |
2002 | .notifier_call = r4k_cache_pm_notifier, | |
2003 | }; | |
2004 | ||
2005 | int __init r4k_cache_init_pm(void) | |
2006 | { | |
2007 | return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block); | |
2008 | } | |
2009 | arch_initcall(r4k_cache_init_pm); |