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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
79add627 | 6 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
7 | * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) |
8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | |
9 | */ | |
a754f708 | 10 | #include <linux/hardirq.h> |
1da177e4 | 11 | #include <linux/init.h> |
db813fe5 | 12 | #include <linux/highmem.h> |
1da177e4 | 13 | #include <linux/kernel.h> |
641e97f3 | 14 | #include <linux/linkage.h> |
ff522058 | 15 | #include <linux/preempt.h> |
1da177e4 | 16 | #include <linux/sched.h> |
631330f5 | 17 | #include <linux/smp.h> |
1da177e4 | 18 | #include <linux/mm.h> |
35133692 | 19 | #include <linux/module.h> |
1da177e4 LT |
20 | #include <linux/bitops.h> |
21 | ||
22 | #include <asm/bcache.h> | |
23 | #include <asm/bootinfo.h> | |
ec74e361 | 24 | #include <asm/cache.h> |
1da177e4 LT |
25 | #include <asm/cacheops.h> |
26 | #include <asm/cpu.h> | |
27 | #include <asm/cpu-features.h> | |
69f24d17 | 28 | #include <asm/cpu-type.h> |
1da177e4 LT |
29 | #include <asm/io.h> |
30 | #include <asm/page.h> | |
31 | #include <asm/pgtable.h> | |
32 | #include <asm/r4kcache.h> | |
e001e528 | 33 | #include <asm/sections.h> |
1da177e4 LT |
34 | #include <asm/mmu_context.h> |
35 | #include <asm/war.h> | |
ba5187db | 36 | #include <asm/cacheflush.h> /* for run_uncached() */ |
9cd9669b | 37 | #include <asm/traps.h> |
b6d92b4a | 38 | #include <asm/dma-coherence.h> |
7f3f1d01 RB |
39 | |
40 | /* | |
41 | * Special Variant of smp_call_function for use by cache functions: | |
42 | * | |
43 | * o No return value | |
44 | * o collapses to normal function call on UP kernels | |
45 | * o collapses to normal function call on systems with a single shared | |
46 | * primary cache. | |
c8c5f3fd | 47 | * o doesn't disable interrupts on the local CPU |
7f3f1d01 | 48 | */ |
48a26e60 | 49 | static inline void r4k_on_each_cpu(void (*func) (void *info), void *info) |
7f3f1d01 RB |
50 | { |
51 | preempt_disable(); | |
52 | ||
b633648c | 53 | #ifndef CONFIG_MIPS_MT_SMP |
48a26e60 | 54 | smp_call_function(func, info, 1); |
7f3f1d01 RB |
55 | #endif |
56 | func(info); | |
57 | preempt_enable(); | |
58 | } | |
59 | ||
0ee958e1 | 60 | #if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS) |
39b8d525 RB |
61 | #define cpu_has_safe_index_cacheops 0 |
62 | #else | |
63 | #define cpu_has_safe_index_cacheops 1 | |
64 | #endif | |
65 | ||
ec74e361 RB |
66 | /* |
67 | * Must die. | |
68 | */ | |
69 | static unsigned long icache_size __read_mostly; | |
70 | static unsigned long dcache_size __read_mostly; | |
71 | static unsigned long scache_size __read_mostly; | |
1da177e4 LT |
72 | |
73 | /* | |
74 | * Dummy cache handling routines for machines without boardcaches | |
75 | */ | |
73f40352 | 76 | static void cache_noop(void) {} |
1da177e4 LT |
77 | |
78 | static struct bcache_ops no_sc_ops = { | |
73f40352 CD |
79 | .bc_enable = (void *)cache_noop, |
80 | .bc_disable = (void *)cache_noop, | |
81 | .bc_wback_inv = (void *)cache_noop, | |
82 | .bc_inv = (void *)cache_noop | |
1da177e4 LT |
83 | }; |
84 | ||
85 | struct bcache_ops *bcops = &no_sc_ops; | |
86 | ||
330cfe01 TS |
87 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) |
88 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) | |
1da177e4 LT |
89 | |
90 | #define R4600_HIT_CACHEOP_WAR_IMPL \ | |
91 | do { \ | |
92 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ | |
93 | *(volatile unsigned long *)CKSEG1; \ | |
94 | if (R4600_V1_HIT_CACHEOP_WAR) \ | |
95 | __asm__ __volatile__("nop;nop;nop;nop"); \ | |
96 | } while (0) | |
97 | ||
98 | static void (*r4k_blast_dcache_page)(unsigned long addr); | |
99 | ||
100 | static inline void r4k_blast_dcache_page_dc32(unsigned long addr) | |
101 | { | |
102 | R4600_HIT_CACHEOP_WAR_IMPL; | |
103 | blast_dcache32_page(addr); | |
104 | } | |
105 | ||
605b7ef7 KC |
106 | static inline void r4k_blast_dcache_page_dc64(unsigned long addr) |
107 | { | |
605b7ef7 KC |
108 | blast_dcache64_page(addr); |
109 | } | |
110 | ||
078a55fc | 111 | static void r4k_blast_dcache_page_setup(void) |
1da177e4 LT |
112 | { |
113 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
114 | ||
73f40352 CD |
115 | if (dc_lsize == 0) |
116 | r4k_blast_dcache_page = (void *)cache_noop; | |
117 | else if (dc_lsize == 16) | |
1da177e4 LT |
118 | r4k_blast_dcache_page = blast_dcache16_page; |
119 | else if (dc_lsize == 32) | |
120 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; | |
605b7ef7 KC |
121 | else if (dc_lsize == 64) |
122 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc64; | |
1da177e4 LT |
123 | } |
124 | ||
4caa906e LY |
125 | #ifndef CONFIG_EVA |
126 | #define r4k_blast_dcache_user_page r4k_blast_dcache_page | |
127 | #else | |
128 | ||
129 | static void (*r4k_blast_dcache_user_page)(unsigned long addr); | |
130 | ||
131 | static void r4k_blast_dcache_user_page_setup(void) | |
132 | { | |
133 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
134 | ||
135 | if (dc_lsize == 0) | |
136 | r4k_blast_dcache_user_page = (void *)cache_noop; | |
137 | else if (dc_lsize == 16) | |
138 | r4k_blast_dcache_user_page = blast_dcache16_user_page; | |
139 | else if (dc_lsize == 32) | |
140 | r4k_blast_dcache_user_page = blast_dcache32_user_page; | |
141 | else if (dc_lsize == 64) | |
142 | r4k_blast_dcache_user_page = blast_dcache64_user_page; | |
143 | } | |
144 | ||
145 | #endif | |
146 | ||
1da177e4 LT |
147 | static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); |
148 | ||
078a55fc | 149 | static void r4k_blast_dcache_page_indexed_setup(void) |
1da177e4 LT |
150 | { |
151 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
152 | ||
73f40352 CD |
153 | if (dc_lsize == 0) |
154 | r4k_blast_dcache_page_indexed = (void *)cache_noop; | |
155 | else if (dc_lsize == 16) | |
1da177e4 LT |
156 | r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; |
157 | else if (dc_lsize == 32) | |
158 | r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; | |
605b7ef7 KC |
159 | else if (dc_lsize == 64) |
160 | r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; | |
1da177e4 LT |
161 | } |
162 | ||
f2e3656d SL |
163 | void (* r4k_blast_dcache)(void); |
164 | EXPORT_SYMBOL(r4k_blast_dcache); | |
1da177e4 | 165 | |
078a55fc | 166 | static void r4k_blast_dcache_setup(void) |
1da177e4 LT |
167 | { |
168 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
169 | ||
73f40352 CD |
170 | if (dc_lsize == 0) |
171 | r4k_blast_dcache = (void *)cache_noop; | |
172 | else if (dc_lsize == 16) | |
1da177e4 LT |
173 | r4k_blast_dcache = blast_dcache16; |
174 | else if (dc_lsize == 32) | |
175 | r4k_blast_dcache = blast_dcache32; | |
605b7ef7 KC |
176 | else if (dc_lsize == 64) |
177 | r4k_blast_dcache = blast_dcache64; | |
1da177e4 LT |
178 | } |
179 | ||
180 | /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ | |
181 | #define JUMP_TO_ALIGN(order) \ | |
182 | __asm__ __volatile__( \ | |
183 | "b\t1f\n\t" \ | |
184 | ".align\t" #order "\n\t" \ | |
185 | "1:\n\t" \ | |
186 | ) | |
187 | #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ | |
70342287 | 188 | #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) |
1da177e4 LT |
189 | |
190 | static inline void blast_r4600_v1_icache32(void) | |
191 | { | |
192 | unsigned long flags; | |
193 | ||
194 | local_irq_save(flags); | |
195 | blast_icache32(); | |
196 | local_irq_restore(flags); | |
197 | } | |
198 | ||
199 | static inline void tx49_blast_icache32(void) | |
200 | { | |
201 | unsigned long start = INDEX_BASE; | |
202 | unsigned long end = start + current_cpu_data.icache.waysize; | |
203 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
204 | unsigned long ws_end = current_cpu_data.icache.ways << | |
70342287 | 205 | current_cpu_data.icache.waybit; |
1da177e4 LT |
206 | unsigned long ws, addr; |
207 | ||
208 | CACHE32_UNROLL32_ALIGN2; | |
209 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
210 | for (ws = 0; ws < ws_end; ws += ws_inc) |
211 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 212 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
213 | CACHE32_UNROLL32_ALIGN; |
214 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
215 | for (ws = 0; ws < ws_end; ws += ws_inc) |
216 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 217 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
218 | } |
219 | ||
220 | static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) | |
221 | { | |
222 | unsigned long flags; | |
223 | ||
224 | local_irq_save(flags); | |
225 | blast_icache32_page_indexed(page); | |
226 | local_irq_restore(flags); | |
227 | } | |
228 | ||
229 | static inline void tx49_blast_icache32_page_indexed(unsigned long page) | |
230 | { | |
67a3f6de AN |
231 | unsigned long indexmask = current_cpu_data.icache.waysize - 1; |
232 | unsigned long start = INDEX_BASE + (page & indexmask); | |
1da177e4 LT |
233 | unsigned long end = start + PAGE_SIZE; |
234 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
235 | unsigned long ws_end = current_cpu_data.icache.ways << | |
70342287 | 236 | current_cpu_data.icache.waybit; |
1da177e4 LT |
237 | unsigned long ws, addr; |
238 | ||
239 | CACHE32_UNROLL32_ALIGN2; | |
240 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
241 | for (ws = 0; ws < ws_end; ws += ws_inc) |
242 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 243 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
244 | CACHE32_UNROLL32_ALIGN; |
245 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
246 | for (ws = 0; ws < ws_end; ws += ws_inc) |
247 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 248 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
249 | } |
250 | ||
251 | static void (* r4k_blast_icache_page)(unsigned long addr); | |
252 | ||
078a55fc | 253 | static void r4k_blast_icache_page_setup(void) |
1da177e4 LT |
254 | { |
255 | unsigned long ic_lsize = cpu_icache_line_size(); | |
256 | ||
73f40352 CD |
257 | if (ic_lsize == 0) |
258 | r4k_blast_icache_page = (void *)cache_noop; | |
259 | else if (ic_lsize == 16) | |
1da177e4 | 260 | r4k_blast_icache_page = blast_icache16_page; |
43a06847 AK |
261 | else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2) |
262 | r4k_blast_icache_page = loongson2_blast_icache32_page; | |
1da177e4 LT |
263 | else if (ic_lsize == 32) |
264 | r4k_blast_icache_page = blast_icache32_page; | |
265 | else if (ic_lsize == 64) | |
266 | r4k_blast_icache_page = blast_icache64_page; | |
267 | } | |
268 | ||
4caa906e LY |
269 | #ifndef CONFIG_EVA |
270 | #define r4k_blast_icache_user_page r4k_blast_icache_page | |
271 | #else | |
272 | ||
273 | static void (*r4k_blast_icache_user_page)(unsigned long addr); | |
274 | ||
275 | static void __cpuinit r4k_blast_icache_user_page_setup(void) | |
276 | { | |
277 | unsigned long ic_lsize = cpu_icache_line_size(); | |
278 | ||
279 | if (ic_lsize == 0) | |
280 | r4k_blast_icache_user_page = (void *)cache_noop; | |
281 | else if (ic_lsize == 16) | |
282 | r4k_blast_icache_user_page = blast_icache16_user_page; | |
283 | else if (ic_lsize == 32) | |
284 | r4k_blast_icache_user_page = blast_icache32_user_page; | |
285 | else if (ic_lsize == 64) | |
286 | r4k_blast_icache_user_page = blast_icache64_user_page; | |
287 | } | |
288 | ||
289 | #endif | |
1da177e4 LT |
290 | |
291 | static void (* r4k_blast_icache_page_indexed)(unsigned long addr); | |
292 | ||
078a55fc | 293 | static void r4k_blast_icache_page_indexed_setup(void) |
1da177e4 LT |
294 | { |
295 | unsigned long ic_lsize = cpu_icache_line_size(); | |
296 | ||
73f40352 CD |
297 | if (ic_lsize == 0) |
298 | r4k_blast_icache_page_indexed = (void *)cache_noop; | |
299 | else if (ic_lsize == 16) | |
1da177e4 LT |
300 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; |
301 | else if (ic_lsize == 32) { | |
02fe2c9c | 302 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
1da177e4 LT |
303 | r4k_blast_icache_page_indexed = |
304 | blast_icache32_r4600_v1_page_indexed; | |
02fe2c9c TS |
305 | else if (TX49XX_ICACHE_INDEX_INV_WAR) |
306 | r4k_blast_icache_page_indexed = | |
307 | tx49_blast_icache32_page_indexed; | |
43a06847 AK |
308 | else if (current_cpu_type() == CPU_LOONGSON2) |
309 | r4k_blast_icache_page_indexed = | |
310 | loongson2_blast_icache32_page_indexed; | |
1da177e4 LT |
311 | else |
312 | r4k_blast_icache_page_indexed = | |
313 | blast_icache32_page_indexed; | |
314 | } else if (ic_lsize == 64) | |
315 | r4k_blast_icache_page_indexed = blast_icache64_page_indexed; | |
316 | } | |
317 | ||
f2e3656d SL |
318 | void (* r4k_blast_icache)(void); |
319 | EXPORT_SYMBOL(r4k_blast_icache); | |
1da177e4 | 320 | |
078a55fc | 321 | static void r4k_blast_icache_setup(void) |
1da177e4 LT |
322 | { |
323 | unsigned long ic_lsize = cpu_icache_line_size(); | |
324 | ||
73f40352 CD |
325 | if (ic_lsize == 0) |
326 | r4k_blast_icache = (void *)cache_noop; | |
327 | else if (ic_lsize == 16) | |
1da177e4 LT |
328 | r4k_blast_icache = blast_icache16; |
329 | else if (ic_lsize == 32) { | |
330 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) | |
331 | r4k_blast_icache = blast_r4600_v1_icache32; | |
332 | else if (TX49XX_ICACHE_INDEX_INV_WAR) | |
333 | r4k_blast_icache = tx49_blast_icache32; | |
43a06847 AK |
334 | else if (current_cpu_type() == CPU_LOONGSON2) |
335 | r4k_blast_icache = loongson2_blast_icache32; | |
1da177e4 LT |
336 | else |
337 | r4k_blast_icache = blast_icache32; | |
338 | } else if (ic_lsize == 64) | |
339 | r4k_blast_icache = blast_icache64; | |
340 | } | |
341 | ||
342 | static void (* r4k_blast_scache_page)(unsigned long addr); | |
343 | ||
078a55fc | 344 | static void r4k_blast_scache_page_setup(void) |
1da177e4 LT |
345 | { |
346 | unsigned long sc_lsize = cpu_scache_line_size(); | |
347 | ||
4debe4f9 | 348 | if (scache_size == 0) |
73f40352 | 349 | r4k_blast_scache_page = (void *)cache_noop; |
4debe4f9 | 350 | else if (sc_lsize == 16) |
1da177e4 LT |
351 | r4k_blast_scache_page = blast_scache16_page; |
352 | else if (sc_lsize == 32) | |
353 | r4k_blast_scache_page = blast_scache32_page; | |
354 | else if (sc_lsize == 64) | |
355 | r4k_blast_scache_page = blast_scache64_page; | |
356 | else if (sc_lsize == 128) | |
357 | r4k_blast_scache_page = blast_scache128_page; | |
358 | } | |
359 | ||
360 | static void (* r4k_blast_scache_page_indexed)(unsigned long addr); | |
361 | ||
078a55fc | 362 | static void r4k_blast_scache_page_indexed_setup(void) |
1da177e4 LT |
363 | { |
364 | unsigned long sc_lsize = cpu_scache_line_size(); | |
365 | ||
4debe4f9 | 366 | if (scache_size == 0) |
73f40352 | 367 | r4k_blast_scache_page_indexed = (void *)cache_noop; |
4debe4f9 | 368 | else if (sc_lsize == 16) |
1da177e4 LT |
369 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; |
370 | else if (sc_lsize == 32) | |
371 | r4k_blast_scache_page_indexed = blast_scache32_page_indexed; | |
372 | else if (sc_lsize == 64) | |
373 | r4k_blast_scache_page_indexed = blast_scache64_page_indexed; | |
374 | else if (sc_lsize == 128) | |
375 | r4k_blast_scache_page_indexed = blast_scache128_page_indexed; | |
376 | } | |
377 | ||
378 | static void (* r4k_blast_scache)(void); | |
379 | ||
078a55fc | 380 | static void r4k_blast_scache_setup(void) |
1da177e4 LT |
381 | { |
382 | unsigned long sc_lsize = cpu_scache_line_size(); | |
383 | ||
4debe4f9 | 384 | if (scache_size == 0) |
73f40352 | 385 | r4k_blast_scache = (void *)cache_noop; |
4debe4f9 | 386 | else if (sc_lsize == 16) |
1da177e4 LT |
387 | r4k_blast_scache = blast_scache16; |
388 | else if (sc_lsize == 32) | |
389 | r4k_blast_scache = blast_scache32; | |
390 | else if (sc_lsize == 64) | |
391 | r4k_blast_scache = blast_scache64; | |
392 | else if (sc_lsize == 128) | |
393 | r4k_blast_scache = blast_scache128; | |
394 | } | |
395 | ||
1da177e4 LT |
396 | static inline void local_r4k___flush_cache_all(void * args) |
397 | { | |
10cc3529 | 398 | switch (current_cpu_type()) { |
14bd8c08 | 399 | case CPU_LOONGSON2: |
c579d310 | 400 | case CPU_LOONGSON3: |
1da177e4 LT |
401 | case CPU_R4000SC: |
402 | case CPU_R4000MC: | |
403 | case CPU_R4400SC: | |
404 | case CPU_R4400MC: | |
405 | case CPU_R10000: | |
406 | case CPU_R12000: | |
44d921b2 | 407 | case CPU_R14000: |
14bd8c08 RB |
408 | /* |
409 | * These caches are inclusive caches, that is, if something | |
410 | * is not cached in the S-cache, we know it also won't be | |
411 | * in one of the primary caches. | |
412 | */ | |
1da177e4 | 413 | r4k_blast_scache(); |
14bd8c08 RB |
414 | break; |
415 | ||
416 | default: | |
417 | r4k_blast_dcache(); | |
418 | r4k_blast_icache(); | |
419 | break; | |
1da177e4 LT |
420 | } |
421 | } | |
422 | ||
423 | static void r4k___flush_cache_all(void) | |
424 | { | |
48a26e60 | 425 | r4k_on_each_cpu(local_r4k___flush_cache_all, NULL); |
1da177e4 LT |
426 | } |
427 | ||
a76ab5c1 RB |
428 | static inline int has_valid_asid(const struct mm_struct *mm) |
429 | { | |
b633648c | 430 | #ifdef CONFIG_MIPS_MT_SMP |
a76ab5c1 RB |
431 | int i; |
432 | ||
433 | for_each_online_cpu(i) | |
434 | if (cpu_context(i, mm)) | |
435 | return 1; | |
436 | ||
437 | return 0; | |
438 | #else | |
439 | return cpu_context(smp_processor_id(), mm); | |
440 | #endif | |
441 | } | |
442 | ||
9c5a3d72 RB |
443 | static void r4k__flush_cache_vmap(void) |
444 | { | |
445 | r4k_blast_dcache(); | |
446 | } | |
447 | ||
448 | static void r4k__flush_cache_vunmap(void) | |
449 | { | |
450 | r4k_blast_dcache(); | |
451 | } | |
452 | ||
1da177e4 LT |
453 | static inline void local_r4k_flush_cache_range(void * args) |
454 | { | |
455 | struct vm_area_struct *vma = args; | |
2eaa7ec2 | 456 | int exec = vma->vm_flags & VM_EXEC; |
1da177e4 | 457 | |
a76ab5c1 | 458 | if (!(has_valid_asid(vma->vm_mm))) |
1da177e4 LT |
459 | return; |
460 | ||
0550d9d1 | 461 | r4k_blast_dcache(); |
2eaa7ec2 RB |
462 | if (exec) |
463 | r4k_blast_icache(); | |
1da177e4 LT |
464 | } |
465 | ||
466 | static void r4k_flush_cache_range(struct vm_area_struct *vma, | |
467 | unsigned long start, unsigned long end) | |
468 | { | |
2eaa7ec2 | 469 | int exec = vma->vm_flags & VM_EXEC; |
0550d9d1 | 470 | |
2eaa7ec2 | 471 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) |
48a26e60 | 472 | r4k_on_each_cpu(local_r4k_flush_cache_range, vma); |
1da177e4 LT |
473 | } |
474 | ||
475 | static inline void local_r4k_flush_cache_mm(void * args) | |
476 | { | |
477 | struct mm_struct *mm = args; | |
478 | ||
a76ab5c1 | 479 | if (!has_valid_asid(mm)) |
1da177e4 LT |
480 | return; |
481 | ||
1da177e4 LT |
482 | /* |
483 | * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we | |
484 | * only flush the primary caches but R10000 and R12000 behave sane ... | |
617667ba RB |
485 | * R4000SC and R4400SC indexed S-cache ops also invalidate primary |
486 | * caches, so we can bail out early. | |
1da177e4 | 487 | */ |
10cc3529 RB |
488 | if (current_cpu_type() == CPU_R4000SC || |
489 | current_cpu_type() == CPU_R4000MC || | |
490 | current_cpu_type() == CPU_R4400SC || | |
491 | current_cpu_type() == CPU_R4400MC) { | |
1da177e4 | 492 | r4k_blast_scache(); |
617667ba RB |
493 | return; |
494 | } | |
495 | ||
496 | r4k_blast_dcache(); | |
1da177e4 LT |
497 | } |
498 | ||
499 | static void r4k_flush_cache_mm(struct mm_struct *mm) | |
500 | { | |
501 | if (!cpu_has_dc_aliases) | |
502 | return; | |
503 | ||
48a26e60 | 504 | r4k_on_each_cpu(local_r4k_flush_cache_mm, mm); |
1da177e4 LT |
505 | } |
506 | ||
507 | struct flush_cache_page_args { | |
508 | struct vm_area_struct *vma; | |
6ec25809 | 509 | unsigned long addr; |
de62893b | 510 | unsigned long pfn; |
1da177e4 LT |
511 | }; |
512 | ||
513 | static inline void local_r4k_flush_cache_page(void *args) | |
514 | { | |
515 | struct flush_cache_page_args *fcp_args = args; | |
516 | struct vm_area_struct *vma = fcp_args->vma; | |
6ec25809 | 517 | unsigned long addr = fcp_args->addr; |
db813fe5 | 518 | struct page *page = pfn_to_page(fcp_args->pfn); |
1da177e4 LT |
519 | int exec = vma->vm_flags & VM_EXEC; |
520 | struct mm_struct *mm = vma->vm_mm; | |
c9c5023d | 521 | int map_coherent = 0; |
1da177e4 | 522 | pgd_t *pgdp; |
c6e8b587 | 523 | pud_t *pudp; |
1da177e4 LT |
524 | pmd_t *pmdp; |
525 | pte_t *ptep; | |
db813fe5 | 526 | void *vaddr; |
1da177e4 | 527 | |
79acf83e RB |
528 | /* |
529 | * If ownes no valid ASID yet, cannot possibly have gotten | |
530 | * this page into the cache. | |
531 | */ | |
a76ab5c1 | 532 | if (!has_valid_asid(mm)) |
79acf83e RB |
533 | return; |
534 | ||
6ec25809 RB |
535 | addr &= PAGE_MASK; |
536 | pgdp = pgd_offset(mm, addr); | |
537 | pudp = pud_offset(pgdp, addr); | |
538 | pmdp = pmd_offset(pudp, addr); | |
539 | ptep = pte_offset(pmdp, addr); | |
1da177e4 LT |
540 | |
541 | /* | |
542 | * If the page isn't marked valid, the page cannot possibly be | |
543 | * in the cache. | |
544 | */ | |
526af35e | 545 | if (!(pte_present(*ptep))) |
1da177e4 LT |
546 | return; |
547 | ||
db813fe5 RB |
548 | if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) |
549 | vaddr = NULL; | |
550 | else { | |
551 | /* | |
552 | * Use kmap_coherent or kmap_atomic to do flushes for | |
553 | * another ASID than the current one. | |
554 | */ | |
c9c5023d RB |
555 | map_coherent = (cpu_has_dc_aliases && |
556 | page_mapped(page) && !Page_dcache_dirty(page)); | |
557 | if (map_coherent) | |
db813fe5 RB |
558 | vaddr = kmap_coherent(page, addr); |
559 | else | |
9c02048f | 560 | vaddr = kmap_atomic(page); |
db813fe5 | 561 | addr = (unsigned long)vaddr; |
1da177e4 LT |
562 | } |
563 | ||
1da177e4 | 564 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { |
80ca69f4 MC |
565 | vaddr ? r4k_blast_dcache_page(addr) : |
566 | r4k_blast_dcache_user_page(addr); | |
39b8d525 RB |
567 | if (exec && !cpu_icache_snoops_remote_store) |
568 | r4k_blast_scache_page(addr); | |
1da177e4 LT |
569 | } |
570 | if (exec) { | |
db813fe5 | 571 | if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { |
1da177e4 LT |
572 | int cpu = smp_processor_id(); |
573 | ||
26a51b27 TS |
574 | if (cpu_context(cpu, mm) != 0) |
575 | drop_mmu_context(mm, cpu); | |
1da177e4 | 576 | } else |
80ca69f4 MC |
577 | vaddr ? r4k_blast_icache_page(addr) : |
578 | r4k_blast_icache_user_page(addr); | |
db813fe5 RB |
579 | } |
580 | ||
581 | if (vaddr) { | |
c9c5023d | 582 | if (map_coherent) |
db813fe5 RB |
583 | kunmap_coherent(); |
584 | else | |
9c02048f | 585 | kunmap_atomic(vaddr); |
1da177e4 LT |
586 | } |
587 | } | |
588 | ||
6ec25809 RB |
589 | static void r4k_flush_cache_page(struct vm_area_struct *vma, |
590 | unsigned long addr, unsigned long pfn) | |
1da177e4 LT |
591 | { |
592 | struct flush_cache_page_args args; | |
593 | ||
1da177e4 | 594 | args.vma = vma; |
6ec25809 | 595 | args.addr = addr; |
de62893b | 596 | args.pfn = pfn; |
1da177e4 | 597 | |
48a26e60 | 598 | r4k_on_each_cpu(local_r4k_flush_cache_page, &args); |
1da177e4 LT |
599 | } |
600 | ||
601 | static inline void local_r4k_flush_data_cache_page(void * addr) | |
602 | { | |
603 | r4k_blast_dcache_page((unsigned long) addr); | |
604 | } | |
605 | ||
606 | static void r4k_flush_data_cache_page(unsigned long addr) | |
607 | { | |
a754f708 RB |
608 | if (in_atomic()) |
609 | local_r4k_flush_data_cache_page((void *)addr); | |
610 | else | |
48a26e60 | 611 | r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr); |
1da177e4 LT |
612 | } |
613 | ||
614 | struct flush_icache_range_args { | |
d4264f18 AN |
615 | unsigned long start; |
616 | unsigned long end; | |
1da177e4 LT |
617 | }; |
618 | ||
e0cee3ee | 619 | static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 | 620 | { |
1da177e4 | 621 | if (!cpu_has_ic_fills_f_dc) { |
73f40352 | 622 | if (end - start >= dcache_size) { |
1da177e4 LT |
623 | r4k_blast_dcache(); |
624 | } else { | |
10a3dabd | 625 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 626 | protected_blast_dcache_range(start, end); |
1da177e4 | 627 | } |
1da177e4 LT |
628 | } |
629 | ||
630 | if (end - start > icache_size) | |
631 | r4k_blast_icache(); | |
14bd8c08 RB |
632 | else { |
633 | switch (boot_cpu_type()) { | |
634 | case CPU_LOONGSON2: | |
bad009fe | 635 | protected_loongson2_blast_icache_range(start, end); |
14bd8c08 RB |
636 | break; |
637 | ||
638 | default: | |
bad009fe | 639 | protected_blast_icache_range(start, end); |
14bd8c08 RB |
640 | break; |
641 | } | |
642 | } | |
4676f935 LY |
643 | #ifdef CONFIG_EVA |
644 | /* | |
645 | * Due to all possible segment mappings, there might cache aliases | |
646 | * caused by the bootloader being in non-EVA mode, and the CPU switching | |
647 | * to EVA during early kernel init. It's best to flush the scache | |
648 | * to avoid having secondary cores fetching stale data and lead to | |
649 | * kernel crashes. | |
650 | */ | |
651 | bc_wback_inv(start, (end - start)); | |
652 | __sync(); | |
653 | #endif | |
1da177e4 LT |
654 | } |
655 | ||
e0cee3ee TB |
656 | static inline void local_r4k_flush_icache_range_ipi(void *args) |
657 | { | |
658 | struct flush_icache_range_args *fir_args = args; | |
659 | unsigned long start = fir_args->start; | |
660 | unsigned long end = fir_args->end; | |
661 | ||
662 | local_r4k_flush_icache_range(start, end); | |
663 | } | |
664 | ||
d4264f18 | 665 | static void r4k_flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 LT |
666 | { |
667 | struct flush_icache_range_args args; | |
668 | ||
669 | args.start = start; | |
670 | args.end = end; | |
671 | ||
48a26e60 | 672 | r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args); |
cc61c1fe | 673 | instruction_hazard(); |
1da177e4 LT |
674 | } |
675 | ||
8005711c | 676 | #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) |
1da177e4 LT |
677 | |
678 | static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) | |
679 | { | |
1da177e4 LT |
680 | /* Catch bad driver code */ |
681 | BUG_ON(size == 0); | |
682 | ||
ff522058 | 683 | preempt_disable(); |
fc5d2d27 | 684 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 685 | if (size >= scache_size) |
1da177e4 | 686 | r4k_blast_scache(); |
41700e73 AN |
687 | else |
688 | blast_scache_range(addr, addr + size); | |
5596b0b2 | 689 | preempt_enable(); |
d0023c4a | 690 | __sync(); |
1da177e4 LT |
691 | return; |
692 | } | |
693 | ||
694 | /* | |
695 | * Either no secondary cache or the available caches don't have the | |
696 | * subset property so we have to flush the primary caches | |
697 | * explicitly | |
698 | */ | |
39b8d525 | 699 | if (cpu_has_safe_index_cacheops && size >= dcache_size) { |
1da177e4 LT |
700 | r4k_blast_dcache(); |
701 | } else { | |
1da177e4 | 702 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 703 | blast_dcache_range(addr, addr + size); |
1da177e4 | 704 | } |
ff522058 | 705 | preempt_enable(); |
1da177e4 LT |
706 | |
707 | bc_wback_inv(addr, size); | |
d0023c4a | 708 | __sync(); |
1da177e4 LT |
709 | } |
710 | ||
711 | static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) | |
712 | { | |
1da177e4 LT |
713 | /* Catch bad driver code */ |
714 | BUG_ON(size == 0); | |
715 | ||
ff522058 | 716 | preempt_disable(); |
fc5d2d27 | 717 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 718 | if (size >= scache_size) |
1da177e4 | 719 | r4k_blast_scache(); |
a8ca8b64 | 720 | else { |
a8ca8b64 RB |
721 | /* |
722 | * There is no clearly documented alignment requirement | |
723 | * for the cache instruction on MIPS processors and | |
724 | * some processors, among them the RM5200 and RM7000 | |
725 | * QED processors will throw an address error for cache | |
70342287 | 726 | * hit ops with insufficient alignment. Solved by |
a8ca8b64 RB |
727 | * aligning the address to cache line size. |
728 | */ | |
e9c33572 | 729 | blast_inv_scache_range(addr, addr + size); |
a8ca8b64 | 730 | } |
5596b0b2 | 731 | preempt_enable(); |
d0023c4a | 732 | __sync(); |
1da177e4 LT |
733 | return; |
734 | } | |
735 | ||
39b8d525 | 736 | if (cpu_has_safe_index_cacheops && size >= dcache_size) { |
1da177e4 LT |
737 | r4k_blast_dcache(); |
738 | } else { | |
1da177e4 | 739 | R4600_HIT_CACHEOP_WAR_IMPL; |
e9c33572 | 740 | blast_inv_dcache_range(addr, addr + size); |
1da177e4 | 741 | } |
ff522058 | 742 | preempt_enable(); |
1da177e4 LT |
743 | |
744 | bc_inv(addr, size); | |
d0023c4a | 745 | __sync(); |
1da177e4 | 746 | } |
8005711c | 747 | #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ |
1da177e4 LT |
748 | |
749 | /* | |
750 | * While we're protected against bad userland addresses we don't care | |
751 | * very much about what happens in that case. Usually a segmentation | |
752 | * fault will dump the process later on anyway ... | |
753 | */ | |
754 | static void local_r4k_flush_cache_sigtramp(void * arg) | |
755 | { | |
02fe2c9c TS |
756 | unsigned long ic_lsize = cpu_icache_line_size(); |
757 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
758 | unsigned long sc_lsize = cpu_scache_line_size(); | |
1da177e4 LT |
759 | unsigned long addr = (unsigned long) arg; |
760 | ||
761 | R4600_HIT_CACHEOP_WAR_IMPL; | |
73f40352 CD |
762 | if (dc_lsize) |
763 | protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); | |
4debe4f9 | 764 | if (!cpu_icache_snoops_remote_store && scache_size) |
1da177e4 | 765 | protected_writeback_scache_line(addr & ~(sc_lsize - 1)); |
73f40352 CD |
766 | if (ic_lsize) |
767 | protected_flush_icache_line(addr & ~(ic_lsize - 1)); | |
1da177e4 LT |
768 | if (MIPS4K_ICACHE_REFILL_WAR) { |
769 | __asm__ __volatile__ ( | |
770 | ".set push\n\t" | |
771 | ".set noat\n\t" | |
772 | ".set mips3\n\t" | |
875d43e7 | 773 | #ifdef CONFIG_32BIT |
1da177e4 LT |
774 | "la $at,1f\n\t" |
775 | #endif | |
875d43e7 | 776 | #ifdef CONFIG_64BIT |
1da177e4 LT |
777 | "dla $at,1f\n\t" |
778 | #endif | |
779 | "cache %0,($at)\n\t" | |
780 | "nop; nop; nop\n" | |
781 | "1:\n\t" | |
782 | ".set pop" | |
783 | : | |
784 | : "i" (Hit_Invalidate_I)); | |
785 | } | |
786 | if (MIPS_CACHE_SYNC_WAR) | |
787 | __asm__ __volatile__ ("sync"); | |
788 | } | |
789 | ||
790 | static void r4k_flush_cache_sigtramp(unsigned long addr) | |
791 | { | |
48a26e60 | 792 | r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr); |
1da177e4 LT |
793 | } |
794 | ||
795 | static void r4k_flush_icache_all(void) | |
796 | { | |
797 | if (cpu_has_vtag_icache) | |
798 | r4k_blast_icache(); | |
799 | } | |
800 | ||
d9cdc901 RB |
801 | struct flush_kernel_vmap_range_args { |
802 | unsigned long vaddr; | |
803 | int size; | |
804 | }; | |
805 | ||
806 | static inline void local_r4k_flush_kernel_vmap_range(void *args) | |
807 | { | |
808 | struct flush_kernel_vmap_range_args *vmra = args; | |
809 | unsigned long vaddr = vmra->vaddr; | |
810 | int size = vmra->size; | |
811 | ||
812 | /* | |
813 | * Aliases only affect the primary caches so don't bother with | |
814 | * S-caches or T-caches. | |
815 | */ | |
816 | if (cpu_has_safe_index_cacheops && size >= dcache_size) | |
817 | r4k_blast_dcache(); | |
818 | else { | |
819 | R4600_HIT_CACHEOP_WAR_IMPL; | |
820 | blast_dcache_range(vaddr, vaddr + size); | |
821 | } | |
822 | } | |
823 | ||
824 | static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size) | |
825 | { | |
826 | struct flush_kernel_vmap_range_args args; | |
827 | ||
828 | args.vaddr = (unsigned long) vaddr; | |
829 | args.size = size; | |
830 | ||
831 | r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args); | |
832 | } | |
833 | ||
1da177e4 LT |
834 | static inline void rm7k_erratum31(void) |
835 | { | |
836 | const unsigned long ic_lsize = 32; | |
837 | unsigned long addr; | |
838 | ||
839 | /* RM7000 erratum #31. The icache is screwed at startup. */ | |
840 | write_c0_taglo(0); | |
841 | write_c0_taghi(0); | |
842 | ||
843 | for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { | |
844 | __asm__ __volatile__ ( | |
d8748a3a | 845 | ".set push\n\t" |
1da177e4 LT |
846 | ".set noreorder\n\t" |
847 | ".set mips3\n\t" | |
848 | "cache\t%1, 0(%0)\n\t" | |
849 | "cache\t%1, 0x1000(%0)\n\t" | |
850 | "cache\t%1, 0x2000(%0)\n\t" | |
851 | "cache\t%1, 0x3000(%0)\n\t" | |
852 | "cache\t%2, 0(%0)\n\t" | |
853 | "cache\t%2, 0x1000(%0)\n\t" | |
854 | "cache\t%2, 0x2000(%0)\n\t" | |
855 | "cache\t%2, 0x3000(%0)\n\t" | |
856 | "cache\t%1, 0(%0)\n\t" | |
857 | "cache\t%1, 0x1000(%0)\n\t" | |
858 | "cache\t%1, 0x2000(%0)\n\t" | |
859 | "cache\t%1, 0x3000(%0)\n\t" | |
d8748a3a | 860 | ".set pop\n" |
1da177e4 LT |
861 | : |
862 | : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); | |
863 | } | |
864 | } | |
865 | ||
006a851b SH |
866 | static inline void alias_74k_erratum(struct cpuinfo_mips *c) |
867 | { | |
9213ad77 MR |
868 | unsigned int imp = c->processor_id & PRID_IMP_MASK; |
869 | unsigned int rev = c->processor_id & PRID_REV_MASK; | |
870 | ||
006a851b SH |
871 | /* |
872 | * Early versions of the 74K do not update the cache tags on a | |
873 | * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG | |
874 | * aliases. In this case it is better to treat the cache as always | |
875 | * having aliases. | |
876 | */ | |
9213ad77 MR |
877 | switch (imp) { |
878 | case PRID_IMP_74K: | |
879 | if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) | |
880 | c->dcache.flags |= MIPS_CACHE_VTAG; | |
881 | if (rev == PRID_REV_ENCODE_332(2, 4, 0)) | |
882 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); | |
883 | break; | |
884 | case PRID_IMP_1074K: | |
885 | if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) { | |
886 | c->dcache.flags |= MIPS_CACHE_VTAG; | |
887 | write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); | |
888 | } | |
889 | break; | |
890 | default: | |
891 | BUG(); | |
006a851b SH |
892 | } |
893 | } | |
894 | ||
078a55fc | 895 | static char *way_string[] = { NULL, "direct mapped", "2-way", |
1da177e4 LT |
896 | "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" |
897 | }; | |
898 | ||
078a55fc | 899 | static void probe_pcache(void) |
1da177e4 LT |
900 | { |
901 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
902 | unsigned int config = read_c0_config(); | |
903 | unsigned int prid = read_c0_prid(); | |
904 | unsigned long config1; | |
905 | unsigned int lsize; | |
906 | ||
69f24d17 | 907 | switch (current_cpu_type()) { |
1da177e4 LT |
908 | case CPU_R4600: /* QED style two way caches? */ |
909 | case CPU_R4700: | |
910 | case CPU_R5000: | |
911 | case CPU_NEVADA: | |
912 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
913 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
914 | c->icache.ways = 2; | |
3c68da79 | 915 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
916 | |
917 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
918 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
919 | c->dcache.ways = 2; | |
3c68da79 | 920 | c->dcache.waybit= __ffs(dcache_size/2); |
1da177e4 LT |
921 | |
922 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
923 | break; | |
924 | ||
925 | case CPU_R5432: | |
926 | case CPU_R5500: | |
927 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
928 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
929 | c->icache.ways = 2; | |
930 | c->icache.waybit= 0; | |
931 | ||
932 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
933 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
934 | c->dcache.ways = 2; | |
935 | c->dcache.waybit = 0; | |
936 | ||
5864810b | 937 | c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; |
1da177e4 LT |
938 | break; |
939 | ||
940 | case CPU_TX49XX: | |
941 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
942 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
943 | c->icache.ways = 4; | |
944 | c->icache.waybit= 0; | |
945 | ||
946 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
947 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
948 | c->dcache.ways = 4; | |
949 | c->dcache.waybit = 0; | |
950 | ||
951 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
de862b48 | 952 | c->options |= MIPS_CPU_PREFETCH; |
1da177e4 LT |
953 | break; |
954 | ||
955 | case CPU_R4000PC: | |
956 | case CPU_R4000SC: | |
957 | case CPU_R4000MC: | |
958 | case CPU_R4400PC: | |
959 | case CPU_R4400SC: | |
960 | case CPU_R4400MC: | |
961 | case CPU_R4300: | |
962 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
963 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
964 | c->icache.ways = 1; | |
70342287 | 965 | c->icache.waybit = 0; /* doesn't matter */ |
1da177e4 LT |
966 | |
967 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
968 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
969 | c->dcache.ways = 1; | |
970 | c->dcache.waybit = 0; /* does not matter */ | |
971 | ||
972 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
973 | break; | |
974 | ||
975 | case CPU_R10000: | |
976 | case CPU_R12000: | |
44d921b2 | 977 | case CPU_R14000: |
1da177e4 LT |
978 | icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); |
979 | c->icache.linesz = 64; | |
980 | c->icache.ways = 2; | |
981 | c->icache.waybit = 0; | |
982 | ||
983 | dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); | |
984 | c->dcache.linesz = 32; | |
985 | c->dcache.ways = 2; | |
986 | c->dcache.waybit = 0; | |
987 | ||
988 | c->options |= MIPS_CPU_PREFETCH; | |
989 | break; | |
990 | ||
991 | case CPU_VR4133: | |
2874fe55 | 992 | write_c0_config(config & ~VR41_CONF_P4K); |
1da177e4 LT |
993 | case CPU_VR4131: |
994 | /* Workaround for cache instruction bug of VR4131 */ | |
995 | if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || | |
996 | c->processor_id == 0x0c82U) { | |
4e8ab361 YY |
997 | config |= 0x00400000U; |
998 | if (c->processor_id == 0x0c80U) | |
999 | config |= VR41_CONF_BP; | |
1da177e4 | 1000 | write_c0_config(config); |
1058ecda YY |
1001 | } else |
1002 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
1003 | ||
1da177e4 LT |
1004 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); |
1005 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1006 | c->icache.ways = 2; | |
3c68da79 | 1007 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
1008 | |
1009 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
1010 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1011 | c->dcache.ways = 2; | |
3c68da79 | 1012 | c->dcache.waybit = __ffs(dcache_size/2); |
1da177e4 LT |
1013 | break; |
1014 | ||
1015 | case CPU_VR41XX: | |
1016 | case CPU_VR4111: | |
1017 | case CPU_VR4121: | |
1018 | case CPU_VR4122: | |
1019 | case CPU_VR4181: | |
1020 | case CPU_VR4181A: | |
1021 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); | |
1022 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1023 | c->icache.ways = 1; | |
70342287 | 1024 | c->icache.waybit = 0; /* doesn't matter */ |
1da177e4 LT |
1025 | |
1026 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
1027 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1028 | c->dcache.ways = 1; | |
1029 | c->dcache.waybit = 0; /* does not matter */ | |
1030 | ||
1031 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
1032 | break; | |
1033 | ||
1034 | case CPU_RM7000: | |
1035 | rm7k_erratum31(); | |
1036 | ||
1da177e4 LT |
1037 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); |
1038 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1039 | c->icache.ways = 4; | |
3c68da79 | 1040 | c->icache.waybit = __ffs(icache_size / c->icache.ways); |
1da177e4 LT |
1041 | |
1042 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1043 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1044 | c->dcache.ways = 4; | |
3c68da79 | 1045 | c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); |
1da177e4 | 1046 | |
1da177e4 | 1047 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
1da177e4 LT |
1048 | c->options |= MIPS_CPU_PREFETCH; |
1049 | break; | |
1050 | ||
2a21c730 FZ |
1051 | case CPU_LOONGSON2: |
1052 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
1053 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
1054 | if (prid & 0x3) | |
1055 | c->icache.ways = 4; | |
1056 | else | |
1057 | c->icache.ways = 2; | |
1058 | c->icache.waybit = 0; | |
1059 | ||
1060 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
1061 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
1062 | if (prid & 0x3) | |
1063 | c->dcache.ways = 4; | |
1064 | else | |
1065 | c->dcache.ways = 2; | |
1066 | c->dcache.waybit = 0; | |
1067 | break; | |
1068 | ||
c579d310 HC |
1069 | case CPU_LOONGSON3: |
1070 | config1 = read_c0_config1(); | |
1071 | lsize = (config1 >> 19) & 7; | |
1072 | if (lsize) | |
1073 | c->icache.linesz = 2 << lsize; | |
1074 | else | |
1075 | c->icache.linesz = 0; | |
1076 | c->icache.sets = 64 << ((config1 >> 22) & 7); | |
1077 | c->icache.ways = 1 + ((config1 >> 16) & 7); | |
1078 | icache_size = c->icache.sets * | |
1079 | c->icache.ways * | |
1080 | c->icache.linesz; | |
1081 | c->icache.waybit = 0; | |
1082 | ||
1083 | lsize = (config1 >> 10) & 7; | |
1084 | if (lsize) | |
1085 | c->dcache.linesz = 2 << lsize; | |
1086 | else | |
1087 | c->dcache.linesz = 0; | |
1088 | c->dcache.sets = 64 << ((config1 >> 13) & 7); | |
1089 | c->dcache.ways = 1 + ((config1 >> 7) & 7); | |
1090 | dcache_size = c->dcache.sets * | |
1091 | c->dcache.ways * | |
1092 | c->dcache.linesz; | |
1093 | c->dcache.waybit = 0; | |
1094 | break; | |
1095 | ||
1da177e4 LT |
1096 | default: |
1097 | if (!(config & MIPS_CONF_M)) | |
1098 | panic("Don't know how to probe P-caches on this cpu."); | |
1099 | ||
1100 | /* | |
1101 | * So we seem to be a MIPS32 or MIPS64 CPU | |
1102 | * So let's probe the I-cache ... | |
1103 | */ | |
1104 | config1 = read_c0_config1(); | |
1105 | ||
175cba8c MC |
1106 | lsize = (config1 >> 19) & 7; |
1107 | ||
1108 | /* IL == 7 is reserved */ | |
1109 | if (lsize == 7) | |
1110 | panic("Invalid icache line size"); | |
1111 | ||
1112 | c->icache.linesz = lsize ? 2 << lsize : 0; | |
1113 | ||
dc34b05f | 1114 | c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); |
1da177e4 LT |
1115 | c->icache.ways = 1 + ((config1 >> 16) & 7); |
1116 | ||
1117 | icache_size = c->icache.sets * | |
70342287 RB |
1118 | c->icache.ways * |
1119 | c->icache.linesz; | |
3c68da79 | 1120 | c->icache.waybit = __ffs(icache_size/c->icache.ways); |
1da177e4 LT |
1121 | |
1122 | if (config & 0x8) /* VI bit */ | |
1123 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1124 | ||
1125 | /* | |
1126 | * Now probe the MIPS32 / MIPS64 data cache. | |
1127 | */ | |
1128 | c->dcache.flags = 0; | |
1129 | ||
175cba8c MC |
1130 | lsize = (config1 >> 10) & 7; |
1131 | ||
1132 | /* DL == 7 is reserved */ | |
1133 | if (lsize == 7) | |
1134 | panic("Invalid dcache line size"); | |
1135 | ||
1136 | c->dcache.linesz = lsize ? 2 << lsize : 0; | |
1137 | ||
dc34b05f | 1138 | c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); |
1da177e4 LT |
1139 | c->dcache.ways = 1 + ((config1 >> 7) & 7); |
1140 | ||
1141 | dcache_size = c->dcache.sets * | |
70342287 RB |
1142 | c->dcache.ways * |
1143 | c->dcache.linesz; | |
3c68da79 | 1144 | c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); |
1da177e4 LT |
1145 | |
1146 | c->options |= MIPS_CPU_PREFETCH; | |
1147 | break; | |
1148 | } | |
1149 | ||
1150 | /* | |
1151 | * Processor configuration sanity check for the R4000SC erratum | |
70342287 | 1152 | * #5. With page sizes larger than 32kB there is no possibility |
1da177e4 LT |
1153 | * to get a VCE exception anymore so we don't care about this |
1154 | * misconfiguration. The case is rather theoretical anyway; | |
1155 | * presumably no vendor is shipping his hardware in the "bad" | |
1156 | * configuration. | |
1157 | */ | |
8ff374b9 MR |
1158 | if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 && |
1159 | (prid & PRID_REV_MASK) < PRID_REV_R4400 && | |
1da177e4 LT |
1160 | !(config & CONF_SC) && c->icache.linesz != 16 && |
1161 | PAGE_SIZE <= 0x8000) | |
1162 | panic("Improper R4000SC processor configuration detected"); | |
1163 | ||
1164 | /* compute a couple of other cache variables */ | |
1165 | c->icache.waysize = icache_size / c->icache.ways; | |
1166 | c->dcache.waysize = dcache_size / c->dcache.ways; | |
1167 | ||
73f40352 CD |
1168 | c->icache.sets = c->icache.linesz ? |
1169 | icache_size / (c->icache.linesz * c->icache.ways) : 0; | |
1170 | c->dcache.sets = c->dcache.linesz ? | |
1171 | dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; | |
1da177e4 LT |
1172 | |
1173 | /* | |
1174 | * R10000 and R12000 P-caches are odd in a positive way. They're 32kB | |
1175 | * 2-way virtually indexed so normally would suffer from aliases. So | |
1176 | * normally they'd suffer from aliases but magic in the hardware deals | |
1177 | * with that for us so we don't need to take care ourselves. | |
1178 | */ | |
69f24d17 | 1179 | switch (current_cpu_type()) { |
a95970f3 | 1180 | case CPU_20KC: |
505403b6 | 1181 | case CPU_25KF: |
641e97f3 RB |
1182 | case CPU_SB1: |
1183 | case CPU_SB1A: | |
efa0f81c | 1184 | case CPU_XLR: |
de62893b | 1185 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
641e97f3 RB |
1186 | break; |
1187 | ||
d1e344e5 RB |
1188 | case CPU_R10000: |
1189 | case CPU_R12000: | |
44d921b2 | 1190 | case CPU_R14000: |
d1e344e5 | 1191 | break; |
641e97f3 | 1192 | |
113c62d9 | 1193 | case CPU_M14KC: |
f8fa4811 | 1194 | case CPU_M14KEC: |
d1e344e5 | 1195 | case CPU_24K: |
98a41de9 | 1196 | case CPU_34K: |
2e78ae3f | 1197 | case CPU_74K: |
39b8d525 | 1198 | case CPU_1004K: |
442e14a2 | 1199 | case CPU_1074K: |
26ab96df | 1200 | case CPU_INTERAPTIV: |
aced4cbd | 1201 | case CPU_P5600: |
708ac4b8 | 1202 | case CPU_PROAPTIV: |
f36c4720 | 1203 | case CPU_M5150: |
442e14a2 | 1204 | if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K)) |
006a851b | 1205 | alias_74k_erratum(c); |
02dc6bfb MC |
1206 | if (!(read_c0_config7() & MIPS_CONF7_IAR) && |
1207 | (c->icache.waysize > PAGE_SIZE)) | |
1208 | c->icache.flags |= MIPS_CACHE_ALIASES; | |
1209 | if (read_c0_config7() & MIPS_CONF7_AR) { | |
1210 | /* | |
1211 | * Effectively physically indexed dcache, | |
1212 | * thus no virtual aliases. | |
1213 | */ | |
beab375a RB |
1214 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
1215 | break; | |
1216 | } | |
d1e344e5 | 1217 | default: |
beab375a RB |
1218 | if (c->dcache.waysize > PAGE_SIZE) |
1219 | c->dcache.flags |= MIPS_CACHE_ALIASES; | |
d1e344e5 | 1220 | } |
1da177e4 | 1221 | |
69f24d17 | 1222 | switch (current_cpu_type()) { |
1da177e4 LT |
1223 | case CPU_20KC: |
1224 | /* | |
1225 | * Some older 20Kc chips doesn't have the 'VI' bit in | |
1226 | * the config register. | |
1227 | */ | |
1228 | c->icache.flags |= MIPS_CACHE_VTAG; | |
1229 | break; | |
1230 | ||
270717a8 | 1231 | case CPU_ALCHEMY: |
1da177e4 LT |
1232 | c->icache.flags |= MIPS_CACHE_IC_F_DC; |
1233 | break; | |
1da177e4 | 1234 | |
14bd8c08 RB |
1235 | case CPU_LOONGSON2: |
1236 | /* | |
1237 | * LOONGSON2 has 4 way icache, but when using indexed cache op, | |
1238 | * one op will act on all 4 ways | |
1239 | */ | |
1240 | c->icache.ways = 1; | |
1241 | } | |
2a21c730 | 1242 | |
1da177e4 LT |
1243 | printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", |
1244 | icache_size >> 10, | |
7fc7316a | 1245 | c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", |
1da177e4 LT |
1246 | way_string[c->icache.ways], c->icache.linesz); |
1247 | ||
64bfca5c RB |
1248 | printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", |
1249 | dcache_size >> 10, way_string[c->dcache.ways], | |
1250 | (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", | |
1251 | (c->dcache.flags & MIPS_CACHE_ALIASES) ? | |
1252 | "cache aliases" : "no aliases", | |
1253 | c->dcache.linesz); | |
1da177e4 LT |
1254 | } |
1255 | ||
1256 | /* | |
1257 | * If you even _breathe_ on this function, look at the gcc output and make sure | |
1258 | * it does not pop things on and off the stack for the cache sizing loop that | |
1259 | * executes in KSEG1 space or else you will crash and burn badly. You have | |
1260 | * been warned. | |
1261 | */ | |
078a55fc | 1262 | static int probe_scache(void) |
1da177e4 | 1263 | { |
1da177e4 LT |
1264 | unsigned long flags, addr, begin, end, pow2; |
1265 | unsigned int config = read_c0_config(); | |
1266 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1da177e4 LT |
1267 | |
1268 | if (config & CONF_SC) | |
1269 | return 0; | |
1270 | ||
e001e528 | 1271 | begin = (unsigned long) &_stext; |
1da177e4 LT |
1272 | begin &= ~((4 * 1024 * 1024) - 1); |
1273 | end = begin + (4 * 1024 * 1024); | |
1274 | ||
1275 | /* | |
1276 | * This is such a bitch, you'd think they would make it easy to do | |
1277 | * this. Away you daemons of stupidity! | |
1278 | */ | |
1279 | local_irq_save(flags); | |
1280 | ||
1281 | /* Fill each size-multiple cache line with a valid tag. */ | |
1282 | pow2 = (64 * 1024); | |
1283 | for (addr = begin; addr < end; addr = (begin + pow2)) { | |
1284 | unsigned long *p = (unsigned long *) addr; | |
1285 | __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ | |
1286 | pow2 <<= 1; | |
1287 | } | |
1288 | ||
1289 | /* Load first line with zero (therefore invalid) tag. */ | |
1290 | write_c0_taglo(0); | |
1291 | write_c0_taghi(0); | |
1292 | __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ | |
1293 | cache_op(Index_Store_Tag_I, begin); | |
1294 | cache_op(Index_Store_Tag_D, begin); | |
1295 | cache_op(Index_Store_Tag_SD, begin); | |
1296 | ||
1297 | /* Now search for the wrap around point. */ | |
1298 | pow2 = (128 * 1024); | |
1da177e4 LT |
1299 | for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { |
1300 | cache_op(Index_Load_Tag_SD, addr); | |
1301 | __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ | |
1302 | if (!read_c0_taglo()) | |
1303 | break; | |
1304 | pow2 <<= 1; | |
1305 | } | |
1306 | local_irq_restore(flags); | |
1307 | addr -= begin; | |
1308 | ||
1309 | scache_size = addr; | |
1310 | c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); | |
1311 | c->scache.ways = 1; | |
1312 | c->dcache.waybit = 0; /* does not matter */ | |
1313 | ||
1314 | return 1; | |
1315 | } | |
1316 | ||
2a21c730 FZ |
1317 | static void __init loongson2_sc_init(void) |
1318 | { | |
1319 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1320 | ||
1321 | scache_size = 512*1024; | |
1322 | c->scache.linesz = 32; | |
1323 | c->scache.ways = 4; | |
1324 | c->scache.waybit = 0; | |
1325 | c->scache.waysize = scache_size / (c->scache.ways); | |
1326 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1327 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1328 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1329 | ||
1330 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1331 | } | |
2a21c730 | 1332 | |
c579d310 HC |
1333 | static void __init loongson3_sc_init(void) |
1334 | { | |
1335 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1336 | unsigned int config2, lsize; | |
1337 | ||
1338 | config2 = read_c0_config2(); | |
1339 | lsize = (config2 >> 4) & 15; | |
1340 | if (lsize) | |
1341 | c->scache.linesz = 2 << lsize; | |
1342 | else | |
1343 | c->scache.linesz = 0; | |
1344 | c->scache.sets = 64 << ((config2 >> 8) & 15); | |
1345 | c->scache.ways = 1 + (config2 & 15); | |
1346 | ||
1347 | scache_size = c->scache.sets * | |
1348 | c->scache.ways * | |
1349 | c->scache.linesz; | |
1350 | /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */ | |
1351 | scache_size *= 4; | |
1352 | c->scache.waybit = 0; | |
1353 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1354 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1355 | if (scache_size) | |
1356 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1357 | return; | |
1358 | } | |
1359 | ||
1da177e4 LT |
1360 | extern int r5k_sc_init(void); |
1361 | extern int rm7k_sc_init(void); | |
9318c51a | 1362 | extern int mips_sc_init(void); |
1da177e4 | 1363 | |
078a55fc | 1364 | static void setup_scache(void) |
1da177e4 LT |
1365 | { |
1366 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1367 | unsigned int config = read_c0_config(); | |
1da177e4 LT |
1368 | int sc_present = 0; |
1369 | ||
1370 | /* | |
1371 | * Do the probing thing on R4000SC and R4400SC processors. Other | |
1372 | * processors don't have a S-cache that would be relevant to the | |
603e82ed | 1373 | * Linux memory management. |
1da177e4 | 1374 | */ |
69f24d17 | 1375 | switch (current_cpu_type()) { |
1da177e4 LT |
1376 | case CPU_R4000SC: |
1377 | case CPU_R4000MC: | |
1378 | case CPU_R4400SC: | |
1379 | case CPU_R4400MC: | |
ba5187db | 1380 | sc_present = run_uncached(probe_scache); |
1da177e4 LT |
1381 | if (sc_present) |
1382 | c->options |= MIPS_CPU_CACHE_CDEX_S; | |
1383 | break; | |
1384 | ||
1385 | case CPU_R10000: | |
1386 | case CPU_R12000: | |
44d921b2 | 1387 | case CPU_R14000: |
1da177e4 LT |
1388 | scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); |
1389 | c->scache.linesz = 64 << ((config >> 13) & 1); | |
1390 | c->scache.ways = 2; | |
1391 | c->scache.waybit= 0; | |
1392 | sc_present = 1; | |
1393 | break; | |
1394 | ||
1395 | case CPU_R5000: | |
1396 | case CPU_NEVADA: | |
1397 | #ifdef CONFIG_R5000_CPU_SCACHE | |
1398 | r5k_sc_init(); | |
1399 | #endif | |
70342287 | 1400 | return; |
1da177e4 LT |
1401 | |
1402 | case CPU_RM7000: | |
1da177e4 LT |
1403 | #ifdef CONFIG_RM7000_CPU_SCACHE |
1404 | rm7k_sc_init(); | |
1405 | #endif | |
1406 | return; | |
1407 | ||
2a21c730 FZ |
1408 | case CPU_LOONGSON2: |
1409 | loongson2_sc_init(); | |
1410 | return; | |
14bd8c08 | 1411 | |
c579d310 HC |
1412 | case CPU_LOONGSON3: |
1413 | loongson3_sc_init(); | |
1414 | return; | |
1415 | ||
a3d4fb2d J |
1416 | case CPU_XLP: |
1417 | /* don't need to worry about L2, fully coherent */ | |
1418 | return; | |
2a21c730 | 1419 | |
1da177e4 | 1420 | default: |
adb37892 DCZ |
1421 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | |
1422 | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { | |
9318c51a CD |
1423 | #ifdef CONFIG_MIPS_CPU_SCACHE |
1424 | if (mips_sc_init ()) { | |
1425 | scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; | |
1426 | printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", | |
1427 | scache_size >> 10, | |
1428 | way_string[c->scache.ways], c->scache.linesz); | |
1429 | } | |
1430 | #else | |
1431 | if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) | |
1432 | panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); | |
1433 | #endif | |
1434 | return; | |
1435 | } | |
1da177e4 LT |
1436 | sc_present = 0; |
1437 | } | |
1438 | ||
1439 | if (!sc_present) | |
1440 | return; | |
1441 | ||
1da177e4 LT |
1442 | /* compute a couple of other cache variables */ |
1443 | c->scache.waysize = scache_size / c->scache.ways; | |
1444 | ||
1445 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1446 | ||
1447 | printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1448 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1449 | ||
fc5d2d27 | 1450 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
1da177e4 LT |
1451 | } |
1452 | ||
9370b351 SS |
1453 | void au1x00_fixup_config_od(void) |
1454 | { | |
1455 | /* | |
1456 | * c0_config.od (bit 19) was write only (and read as 0) | |
1457 | * on the early revisions of Alchemy SOCs. It disables the bus | |
1458 | * transaction overlapping and needs to be set to fix various errata. | |
1459 | */ | |
1460 | switch (read_c0_prid()) { | |
1461 | case 0x00030100: /* Au1000 DA */ | |
1462 | case 0x00030201: /* Au1000 HA */ | |
1463 | case 0x00030202: /* Au1000 HB */ | |
1464 | case 0x01030200: /* Au1500 AB */ | |
1465 | /* | |
1466 | * Au1100 errata actually keeps silence about this bit, so we set it | |
1467 | * just in case for those revisions that require it to be set according | |
270717a8 | 1468 | * to the (now gone) cpu table. |
9370b351 SS |
1469 | */ |
1470 | case 0x02030200: /* Au1100 AB */ | |
1471 | case 0x02030201: /* Au1100 BA */ | |
1472 | case 0x02030202: /* Au1100 BC */ | |
1473 | set_c0_config(1 << 19); | |
1474 | break; | |
1475 | } | |
1476 | } | |
1477 | ||
89052bd7 RB |
1478 | /* CP0 hazard avoidance. */ |
1479 | #define NXP_BARRIER() \ | |
1480 | __asm__ __volatile__( \ | |
1481 | ".set noreorder\n\t" \ | |
1482 | "nop; nop; nop; nop; nop; nop;\n\t" \ | |
1483 | ".set reorder\n\t") | |
1484 | ||
1485 | static void nxp_pr4450_fixup_config(void) | |
1486 | { | |
1487 | unsigned long config0; | |
1488 | ||
1489 | config0 = read_c0_config(); | |
1490 | ||
1491 | /* clear all three cache coherency fields */ | |
1492 | config0 &= ~(0x7 | (7 << 25) | (7 << 28)); | |
1493 | config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) | | |
1494 | ((_page_cachable_default >> _CACHE_SHIFT) << 25) | | |
1495 | ((_page_cachable_default >> _CACHE_SHIFT) << 28)); | |
1496 | write_c0_config(config0); | |
1497 | NXP_BARRIER(); | |
1498 | } | |
1499 | ||
078a55fc | 1500 | static int cca = -1; |
35133692 CD |
1501 | |
1502 | static int __init cca_setup(char *str) | |
1503 | { | |
1504 | get_option(&str, &cca); | |
1505 | ||
b5b64f2b | 1506 | return 0; |
35133692 CD |
1507 | } |
1508 | ||
b5b64f2b | 1509 | early_param("cca", cca_setup); |
35133692 | 1510 | |
078a55fc | 1511 | static void coherency_setup(void) |
1da177e4 | 1512 | { |
35133692 CD |
1513 | if (cca < 0 || cca > 7) |
1514 | cca = read_c0_config() & CONF_CM_CMASK; | |
1515 | _page_cachable_default = cca << _CACHE_SHIFT; | |
1516 | ||
1517 | pr_debug("Using cache attribute %d\n", cca); | |
1518 | change_c0_config(CONF_CM_CMASK, cca); | |
1da177e4 LT |
1519 | |
1520 | /* | |
1521 | * c0_status.cu=0 specifies that updates by the sc instruction use | |
1522 | * the coherency mode specified by the TLB; 1 means cachable | |
1523 | * coherent update on write will be used. Not all processors have | |
1524 | * this bit and; some wire it to zero, others like Toshiba had the | |
1525 | * silly idea of putting something else there ... | |
1526 | */ | |
10cc3529 | 1527 | switch (current_cpu_type()) { |
1da177e4 LT |
1528 | case CPU_R4000PC: |
1529 | case CPU_R4000SC: | |
1530 | case CPU_R4000MC: | |
1531 | case CPU_R4400PC: | |
1532 | case CPU_R4400SC: | |
1533 | case CPU_R4400MC: | |
1534 | clear_c0_config(CONF_CU); | |
1535 | break; | |
9370b351 | 1536 | /* |
df586d59 | 1537 | * We need to catch the early Alchemy SOCs with |
270717a8 ML |
1538 | * the write-only co_config.od bit and set it back to one on: |
1539 | * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB | |
9370b351 | 1540 | */ |
270717a8 | 1541 | case CPU_ALCHEMY: |
9370b351 SS |
1542 | au1x00_fixup_config_od(); |
1543 | break; | |
89052bd7 RB |
1544 | |
1545 | case PRID_IMP_PR4450: | |
1546 | nxp_pr4450_fixup_config(); | |
1547 | break; | |
1da177e4 LT |
1548 | } |
1549 | } | |
1550 | ||
078a55fc | 1551 | static void r4k_cache_error_setup(void) |
1da177e4 | 1552 | { |
641e97f3 RB |
1553 | extern char __weak except_vec2_generic; |
1554 | extern char __weak except_vec2_sb1; | |
1da177e4 | 1555 | |
69f24d17 | 1556 | switch (current_cpu_type()) { |
641e97f3 RB |
1557 | case CPU_SB1: |
1558 | case CPU_SB1A: | |
1559 | set_uncached_handler(0x100, &except_vec2_sb1, 0x80); | |
1560 | break; | |
1561 | ||
1562 | default: | |
1563 | set_uncached_handler(0x100, &except_vec2_generic, 0x80); | |
1564 | break; | |
1565 | } | |
9cd9669b DD |
1566 | } |
1567 | ||
078a55fc | 1568 | void r4k_cache_init(void) |
9cd9669b DD |
1569 | { |
1570 | extern void build_clear_page(void); | |
1571 | extern void build_copy_page(void); | |
1572 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1da177e4 LT |
1573 | |
1574 | probe_pcache(); | |
1575 | setup_scache(); | |
1576 | ||
1da177e4 LT |
1577 | r4k_blast_dcache_page_setup(); |
1578 | r4k_blast_dcache_page_indexed_setup(); | |
1579 | r4k_blast_dcache_setup(); | |
1580 | r4k_blast_icache_page_setup(); | |
1581 | r4k_blast_icache_page_indexed_setup(); | |
1582 | r4k_blast_icache_setup(); | |
1583 | r4k_blast_scache_page_setup(); | |
1584 | r4k_blast_scache_page_indexed_setup(); | |
1585 | r4k_blast_scache_setup(); | |
4caa906e LY |
1586 | #ifdef CONFIG_EVA |
1587 | r4k_blast_dcache_user_page_setup(); | |
1588 | r4k_blast_icache_user_page_setup(); | |
1589 | #endif | |
1da177e4 LT |
1590 | |
1591 | /* | |
1592 | * Some MIPS32 and MIPS64 processors have physically indexed caches. | |
1593 | * This code supports virtually indexed processors and will be | |
1594 | * unnecessarily inefficient on physically indexed processors. | |
1595 | */ | |
73f40352 CD |
1596 | if (c->dcache.linesz) |
1597 | shm_align_mask = max_t( unsigned long, | |
1598 | c->dcache.sets * c->dcache.linesz - 1, | |
1599 | PAGE_SIZE - 1); | |
1600 | else | |
1601 | shm_align_mask = PAGE_SIZE-1; | |
9c5a3d72 RB |
1602 | |
1603 | __flush_cache_vmap = r4k__flush_cache_vmap; | |
1604 | __flush_cache_vunmap = r4k__flush_cache_vunmap; | |
1605 | ||
db813fe5 | 1606 | flush_cache_all = cache_noop; |
1da177e4 LT |
1607 | __flush_cache_all = r4k___flush_cache_all; |
1608 | flush_cache_mm = r4k_flush_cache_mm; | |
1609 | flush_cache_page = r4k_flush_cache_page; | |
1da177e4 LT |
1610 | flush_cache_range = r4k_flush_cache_range; |
1611 | ||
d9cdc901 RB |
1612 | __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; |
1613 | ||
1da177e4 LT |
1614 | flush_cache_sigtramp = r4k_flush_cache_sigtramp; |
1615 | flush_icache_all = r4k_flush_icache_all; | |
7e3bfc7c | 1616 | local_flush_data_cache_page = local_r4k_flush_data_cache_page; |
1da177e4 LT |
1617 | flush_data_cache_page = r4k_flush_data_cache_page; |
1618 | flush_icache_range = r4k_flush_icache_range; | |
e0cee3ee | 1619 | local_flush_icache_range = local_r4k_flush_icache_range; |
1da177e4 | 1620 | |
8005711c | 1621 | #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT) |
39b8d525 RB |
1622 | if (coherentio) { |
1623 | _dma_cache_wback_inv = (void *)cache_noop; | |
1624 | _dma_cache_wback = (void *)cache_noop; | |
1625 | _dma_cache_inv = (void *)cache_noop; | |
1626 | } else { | |
1627 | _dma_cache_wback_inv = r4k_dma_cache_wback_inv; | |
1628 | _dma_cache_wback = r4k_dma_cache_wback_inv; | |
1629 | _dma_cache_inv = r4k_dma_cache_inv; | |
1630 | } | |
1da177e4 LT |
1631 | #endif |
1632 | ||
1da177e4 LT |
1633 | build_clear_page(); |
1634 | build_copy_page(); | |
b6d92b4a SH |
1635 | |
1636 | /* | |
1637 | * We want to run CMP kernels on core with and without coherent | |
1638 | * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether | |
1639 | * or not to flush caches. | |
1640 | */ | |
1d40cfcd | 1641 | local_r4k___flush_cache_all(NULL); |
b6d92b4a | 1642 | |
1d40cfcd | 1643 | coherency_setup(); |
9cd9669b | 1644 | board_cache_error_setup = r4k_cache_error_setup; |
1da177e4 | 1645 | } |