[mirror_ubuntu-zesty-kernel.git] / arch / mips / mm / c-tx39.c

/*
 * r2300.c: R2000 and R3000 specific mmu/cache code.
 *
 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
 *
 * with a lot of changes to make this thing work for R3000s
 * Tx39XX R4k style caches added. HK
 * Copyright (C) 1998, 1999, 2000 Harald Koerfgen
 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>

#include <asm/cacheops.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mmu_context.h>
#include <asm/system.h>
#include <asm/isadep.h>
#include <asm/io.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>

/* For R3000 cores with R4000 style caches */
static unsigned long icache_size, dcache_size;		/* Size in bytes */

#include <asm/r4kcache.h>

extern int r3k_have_wired_reg;	/* in r3k-tlb.c */

/* This sequence is required to ensure icache is disabled immediately */
#define TX39_STOP_STREAMING() \
__asm__ __volatile__( \
	".set    push\n\t" \
	".set    noreorder\n\t" \
	"b       1f\n\t" \
	"nop\n\t" \
	"1:\n\t" \
	".set pop" \
	)

/* TX39H-style cache flush routines. */
static void tx39h_flush_icache_all(void)
{
	unsigned long flags, config;

	/* disable icache (set ICE#) */
	local_irq_save(flags);
	config = read_c0_conf();
	write_c0_conf(config & ~TX39_CONF_ICE);
	TX39_STOP_STREAMING();
	blast_icache16();
	write_c0_conf(config);
	local_irq_restore(flags);
}

static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
{
	/* Catch bad driver code */
	BUG_ON(size == 0);

	iob();
	blast_inv_dcache_range(addr, addr + size);
}


/* TX39H2,TX39H3 */
static inline void tx39_blast_dcache_page(unsigned long addr)
{
	if (current_cpu_type() != CPU_TX3912)
		blast_dcache16_page(addr);
}

static inline void tx39_blast_dcache_page_indexed(unsigned long addr)
{
	blast_dcache16_page_indexed(addr);
}

static inline void tx39_blast_dcache(void)
{
	blast_dcache16();
}

static inline void tx39_blast_icache_page(unsigned long addr)
{
	unsigned long flags, config;
	/* disable icache (set ICE#) */
	local_irq_save(flags);
	config = read_c0_conf();
	write_c0_conf(config & ~TX39_CONF_ICE);
	TX39_STOP_STREAMING();
	blast_icache16_page(addr);
	write_c0_conf(config);
	local_irq_restore(flags);
}

static inline void tx39_blast_icache_page_indexed(unsigned long addr)
{
	unsigned long flags, config;
	/* disable icache (set ICE#) */
	local_irq_save(flags);
	config = read_c0_conf();
	write_c0_conf(config & ~TX39_CONF_ICE);
	TX39_STOP_STREAMING();
	blast_icache16_page_indexed(addr);
	write_c0_conf(config);
	local_irq_restore(flags);
}

static inline void tx39_blast_icache(void)
{
	unsigned long flags, config;
	/* disable icache (set ICE#) */
	local_irq_save(flags);
	config = read_c0_conf();
	write_c0_conf(config & ~TX39_CONF_ICE);
	TX39_STOP_STREAMING();
	blast_icache16();
	write_c0_conf(config);
	local_irq_restore(flags);
}

static inline void tx39_flush_cache_all(void)
{
	if (!cpu_has_dc_aliases)
		return;

	tx39_blast_dcache();
}

static inline void tx39___flush_cache_all(void)
{
	tx39_blast_dcache();
	tx39_blast_icache();
}

static void tx39_flush_cache_mm(struct mm_struct *mm)
{
	if (!cpu_has_dc_aliases)
		return;

	if (cpu_context(smp_processor_id(), mm) != 0)
		tx39_blast_dcache();
}

static void tx39_flush_cache_range(struct vm_area_struct *vma,
	unsigned long start, unsigned long end)
{
	if (!cpu_has_dc_aliases)
		return;
	if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
		return;

	tx39_blast_dcache();
}

static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
{
	int exec = vma->vm_flags & VM_EXEC;
	struct mm_struct *mm = vma->vm_mm;
	pgd_t *pgdp;
	pud_t *pudp;
	pmd_t *pmdp;
	pte_t *ptep;

	/*
	 * If ownes no valid ASID yet, cannot possibly have gotten
	 * this page into the cache.
	 */
	if (cpu_context(smp_processor_id(), mm) == 0)
		return;

	page &= PAGE_MASK;
	pgdp = pgd_offset(mm, page);
	pudp = pud_offset(pgdp, page);
	pmdp = pmd_offset(pudp, page);
	ptep = pte_offset(pmdp, page);

	/*
	 * If the page isn't marked valid, the page cannot possibly be
	 * in the cache.
	 */
	if (!(pte_val(*ptep) & _PAGE_PRESENT))
		return;

	/*
	 * Doing flushes for another ASID than the current one is
	 * too difficult since stupid R4k caches do a TLB translation
	 * for every cache flush operation.  So we do indexed flushes
	 * in that case, which doesn't overly flush the cache too much.
	 */
	if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
		if (cpu_has_dc_aliases || exec)
			tx39_blast_dcache_page(page);
		if (exec)
			tx39_blast_icache_page(page);

		return;
	}

	/*
	 * Do indexed flush, too much work to get the (possible) TLB refills
	 * to work correctly.
	 */
	if (cpu_has_dc_aliases || exec)
		tx39_blast_dcache_page_indexed(page);
	if (exec)
		tx39_blast_icache_page_indexed(page);
}

static void local_tx39_flush_data_cache_page(void * addr)
{
	tx39_blast_dcache_page((unsigned long)addr);
}

static void tx39_flush_data_cache_page(unsigned long addr)
{
	tx39_blast_dcache_page(addr);
}

static void tx39_flush_icache_range(unsigned long start, unsigned long end)
{
	if (end - start > dcache_size)
		tx39_blast_dcache();
	else
		protected_blast_dcache_range(start, end);

	if (end - start > icache_size)
		tx39_blast_icache();
	else {
		unsigned long flags, config;
		/* disable icache (set ICE#) */
		local_irq_save(flags);
		config = read_c0_conf();
		write_c0_conf(config & ~TX39_CONF_ICE);
		TX39_STOP_STREAMING();
		protected_blast_icache_range(start, end);
		write_c0_conf(config);
		local_irq_restore(flags);
	}
}

static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
{
	unsigned long end;

	if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
		end = addr + size;
		do {
			tx39_blast_dcache_page(addr);
			addr += PAGE_SIZE;
		} while(addr != end);
	} else if (size > dcache_size) {
		tx39_blast_dcache();
	} else {
		blast_dcache_range(addr, addr + size);
	}
}

static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
{
	unsigned long end;

	if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
		end = addr + size;
		do {
			tx39_blast_dcache_page(addr);
			addr += PAGE_SIZE;
		} while(addr != end);
	} else if (size > dcache_size) {
		tx39_blast_dcache();
	} else {
		blast_inv_dcache_range(addr, addr + size);
	}
}

static void tx39_flush_cache_sigtramp(unsigned long addr)
{
	unsigned long ic_lsize = current_cpu_data.icache.linesz;
	unsigned long dc_lsize = current_cpu_data.dcache.linesz;
	unsigned long config;
	unsigned long flags;

	protected_writeback_dcache_line(addr & ~(dc_lsize - 1));

	/* disable icache (set ICE#) */
	local_irq_save(flags);
	config = read_c0_conf();
	write_c0_conf(config & ~TX39_CONF_ICE);
	TX39_STOP_STREAMING();
	protected_flush_icache_line(addr & ~(ic_lsize - 1));
	write_c0_conf(config);
	local_irq_restore(flags);
}

static __init void tx39_probe_cache(void)
{
	unsigned long config;

	config = read_c0_conf();

	icache_size = 1 << (10 + ((config & TX39_CONF_ICS_MASK) >>
				  TX39_CONF_ICS_SHIFT));
	dcache_size = 1 << (10 + ((config & TX39_CONF_DCS_MASK) >>
				  TX39_CONF_DCS_SHIFT));

	current_cpu_data.icache.linesz = 16;
	switch (current_cpu_type()) {
	case CPU_TX3912:
		current_cpu_data.icache.ways = 1;
		current_cpu_data.dcache.ways = 1;
		current_cpu_data.dcache.linesz = 4;
		break;

	case CPU_TX3927:
		current_cpu_data.icache.ways = 2;
		current_cpu_data.dcache.ways = 2;
		current_cpu_data.dcache.linesz = 16;
		break;

	case CPU_TX3922:
	default:
		current_cpu_data.icache.ways = 1;
		current_cpu_data.dcache.ways = 1;
		current_cpu_data.dcache.linesz = 16;
		break;
	}
}

void __cpuinit tx39_cache_init(void)
{
	extern void build_clear_page(void);
	extern void build_copy_page(void);
	unsigned long config;

	config = read_c0_conf();
	config &= ~TX39_CONF_WBON;
	write_c0_conf(config);

	tx39_probe_cache();

	switch (current_cpu_type()) {
	case CPU_TX3912:
		/* TX39/H core (writethru direct-map cache) */
		flush_cache_all	= tx39h_flush_icache_all;
		__flush_cache_all	= tx39h_flush_icache_all;
		flush_cache_mm		= (void *) tx39h_flush_icache_all;
		flush_cache_range	= (void *) tx39h_flush_icache_all;
		flush_cache_page	= (void *) tx39h_flush_icache_all;
		flush_icache_range	= (void *) tx39h_flush_icache_all;

		flush_cache_sigtramp	= (void *) tx39h_flush_icache_all;
		local_flush_data_cache_page	= (void *) tx39h_flush_icache_all;
		flush_data_cache_page	= (void *) tx39h_flush_icache_all;

		_dma_cache_wback_inv	= tx39h_dma_cache_wback_inv;

		shm_align_mask		= PAGE_SIZE - 1;

		break;

	case CPU_TX3922:
	case CPU_TX3927:
	default:
		/* TX39/H2,H3 core (writeback 2way-set-associative cache) */
		r3k_have_wired_reg = 1;
		write_c0_wired(0);	/* set 8 on reset... */
		/* board-dependent init code may set WBON */

		flush_cache_all = tx39_flush_cache_all;
		__flush_cache_all = tx39___flush_cache_all;
		flush_cache_mm = tx39_flush_cache_mm;
		flush_cache_range = tx39_flush_cache_range;
		flush_cache_page = tx39_flush_cache_page;
		flush_icache_range = tx39_flush_icache_range;

		flush_cache_sigtramp = tx39_flush_cache_sigtramp;
		local_flush_data_cache_page = local_tx39_flush_data_cache_page;
		flush_data_cache_page = tx39_flush_data_cache_page;

		_dma_cache_wback_inv = tx39_dma_cache_wback_inv;
		_dma_cache_wback = tx39_dma_cache_wback_inv;
		_dma_cache_inv = tx39_dma_cache_inv;

		shm_align_mask = max_t(unsigned long,
		                       (dcache_size / current_cpu_data.dcache.ways) - 1,
		                       PAGE_SIZE - 1);

		break;
	}

	current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways;
	current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways;

	current_cpu_data.icache.sets =
		current_cpu_data.icache.waysize / current_cpu_data.icache.linesz;
	current_cpu_data.dcache.sets =
		current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz;

	if (current_cpu_data.dcache.waysize > PAGE_SIZE)
		current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES;

	current_cpu_data.icache.waybit = 0;
	current_cpu_data.dcache.waybit = 0;

	printk("Primary instruction cache %ldkB, linesize %d bytes\n",
		icache_size >> 10, current_cpu_data.icache.linesz);
	printk("Primary data cache %ldkB, linesize %d bytes\n",
		dcache_size >> 10, current_cpu_data.dcache.linesz);

	build_clear_page();
	build_copy_page();
	tx39h_flush_icache_all();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* r2300.c: R2000 and R3000 specific mmu/cache code.
	3	*
	4	* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
	5	*
	6	* with a lot of changes to make this thing work for R3000s
	7	* Tx39XX R4k style caches added. HK
	8	* Copyright (C) 1998, 1999, 2000 Harald Koerfgen
	9	* Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/kernel.h>
	13	#include <linux/sched.h>
	14	#include <linux/mm.h>
	15
	16	#include <asm/cacheops.h>
	17	#include <asm/page.h>
	18	#include <asm/pgtable.h>
	19	#include <asm/mmu_context.h>
	20	#include <asm/system.h>
	21	#include <asm/isadep.h>
	22	#include <asm/io.h>
	23	#include <asm/bootinfo.h>
	24	#include <asm/cpu.h>
	25
	26	/* For R3000 cores with R4000 style caches */
	27	static unsigned long icache_size, dcache_size; /* Size in bytes */
	28
	29	#include <asm/r4kcache.h>
	30
	31	extern int r3k_have_wired_reg; /* in r3k-tlb.c */
	32
	33	/* This sequence is required to ensure icache is disabled immediately */
	34	#define TX39_STOP_STREAMING() \
	35	__asm__ __volatile__( \
	36	".set push\n\t" \
	37	".set noreorder\n\t" \
	38	"b 1f\n\t" \
	39	"nop\n\t" \
	40	"1:\n\t" \
	41	".set pop" \
	42	)
	43
	44	/* TX39H-style cache flush routines. */
	45	static void tx39h_flush_icache_all(void)
	46	{
1da177e4 LT	47	unsigned long flags, config;
	48
	49	/* disable icache (set ICE#) */
	50	local_irq_save(flags);
	51	config = read_c0_conf();
	52	write_c0_conf(config & ~TX39_CONF_ICE);
	53	TX39_STOP_STREAMING();
41700e73	54	blast_icache16();
1da177e4 LT	55	write_c0_conf(config);
	56	local_irq_restore(flags);
	57	}
	58
	59	static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
	60	{
1da177e4 LT	61	/* Catch bad driver code */
	62	BUG_ON(size == 0);
	63
	64	iob();
41700e73	65	blast_inv_dcache_range(addr, addr + size);
1da177e4 LT	66	}
	67
	68
	69	/* TX39H2,TX39H3 */
	70	static inline void tx39_blast_dcache_page(unsigned long addr)
	71	{
10cc3529	72	if (current_cpu_type() != CPU_TX3912)
1da177e4 LT	73	blast_dcache16_page(addr);
	74	}
	75
	76	static inline void tx39_blast_dcache_page_indexed(unsigned long addr)
	77	{
	78	blast_dcache16_page_indexed(addr);
	79	}
	80
	81	static inline void tx39_blast_dcache(void)
	82	{
	83	blast_dcache16();
	84	}
	85
	86	static inline void tx39_blast_icache_page(unsigned long addr)
	87	{
	88	unsigned long flags, config;
	89	/* disable icache (set ICE#) */
	90	local_irq_save(flags);
	91	config = read_c0_conf();
	92	write_c0_conf(config & ~TX39_CONF_ICE);
	93	TX39_STOP_STREAMING();
	94	blast_icache16_page(addr);
	95	write_c0_conf(config);
	96	local_irq_restore(flags);
	97	}
	98
	99	static inline void tx39_blast_icache_page_indexed(unsigned long addr)
	100	{
	101	unsigned long flags, config;
	102	/* disable icache (set ICE#) */
	103	local_irq_save(flags);
	104	config = read_c0_conf();
	105	write_c0_conf(config & ~TX39_CONF_ICE);
	106	TX39_STOP_STREAMING();
	107	blast_icache16_page_indexed(addr);
	108	write_c0_conf(config);
	109	local_irq_restore(flags);
	110	}
	111
	112	static inline void tx39_blast_icache(void)
	113	{
	114	unsigned long flags, config;
	115	/* disable icache (set ICE#) */
	116	local_irq_save(flags);
	117	config = read_c0_conf();
	118	write_c0_conf(config & ~TX39_CONF_ICE);
	119	TX39_STOP_STREAMING();
	120	blast_icache16();
	121	write_c0_conf(config);
	122	local_irq_restore(flags);
	123	}
	124
	125	static inline void tx39_flush_cache_all(void)
	126	{
	127	if (!cpu_has_dc_aliases)
	128	return;
	129
	130	tx39_blast_dcache();
1da177e4 LT	131	}
	132
	133	static inline void tx39___flush_cache_all(void)
	134	{
	135	tx39_blast_dcache();
	136	tx39_blast_icache();
	137	}
	138
	139	static void tx39_flush_cache_mm(struct mm_struct *mm)
	140	{
	141	if (!cpu_has_dc_aliases)
	142	return;
	143
a5664c40 AN	144	if (cpu_context(smp_processor_id(), mm) != 0)
a5664c40 AN	145	tx39_blast_dcache();
1da177e4 LT	146	}
	147
	148	static void tx39_flush_cache_range(struct vm_area_struct *vma,
	149	unsigned long start, unsigned long end)
	150	{
a5664c40 AN	151	if (!cpu_has_dc_aliases)
a5664c40 AN	152	return;
9043f7e9	153	if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
1da177e4 LT	154	return;
1da177e4 LT	155
a5664c40	156	tx39_blast_dcache();
1da177e4 LT	157	}
	158
	159	static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
	160	{
	161	int exec = vma->vm_flags & VM_EXEC;
	162	struct mm_struct *mm = vma->vm_mm;
	163	pgd_t *pgdp;
c6e8b587	164	pud_t *pudp;
1da177e4 LT	165	pmd_t *pmdp;
	166	pte_t *ptep;
	167
	168	/*
	169	* If ownes no valid ASID yet, cannot possibly have gotten
	170	* this page into the cache.
	171	*/
	172	if (cpu_context(smp_processor_id(), mm) == 0)
	173	return;
	174
	175	page &= PAGE_MASK;
	176	pgdp = pgd_offset(mm, page);
c6e8b587 RB	177	pudp = pud_offset(pgdp, page);
c6e8b587 RB	178	pmdp = pmd_offset(pudp, page);
1da177e4 LT	179	ptep = pte_offset(pmdp, page);
	180
	181	/*
	182	* If the page isn't marked valid, the page cannot possibly be
	183	* in the cache.
	184	*/
	185	if (!(pte_val(*ptep) & _PAGE_PRESENT))
	186	return;
	187
	188	/*
	189	* Doing flushes for another ASID than the current one is
	190	* too difficult since stupid R4k caches do a TLB translation
	191	* for every cache flush operation. So we do indexed flushes
	192	* in that case, which doesn't overly flush the cache too much.
	193	*/
	194	if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
	195	if (cpu_has_dc_aliases \|\| exec)
	196	tx39_blast_dcache_page(page);
	197	if (exec)
	198	tx39_blast_icache_page(page);
	199
	200	return;
	201	}
	202
	203	/*
	204	* Do indexed flush, too much work to get the (possible) TLB refills
	205	* to work correctly.
	206	*/
1da177e4 LT	207	if (cpu_has_dc_aliases \|\| exec)
	208	tx39_blast_dcache_page_indexed(page);
	209	if (exec)
	210	tx39_blast_icache_page_indexed(page);
	211	}
	212
7e3bfc7c RB	213	static void local_tx39_flush_data_cache_page(void * addr)
7e3bfc7c RB	214	{
a5664c40	215	tx39_blast_dcache_page((unsigned long)addr);
7e3bfc7c RB	216	}
7e3bfc7c RB	217
1da177e4 LT	218	static void tx39_flush_data_cache_page(unsigned long addr)
	219	{
	220	tx39_blast_dcache_page(addr);
	221	}
	222
	223	static void tx39_flush_icache_range(unsigned long start, unsigned long end)
	224	{
1da177e4 LT	225	if (end - start > dcache_size)
1da177e4 LT	226	tx39_blast_dcache();
41700e73 AN	227	else
41700e73 AN	228	protected_blast_dcache_range(start, end);
1da177e4 LT	229
	230	if (end - start > icache_size)
	231	tx39_blast_icache();
	232	else {
	233	unsigned long flags, config;
1da177e4 LT	234	/* disable icache (set ICE#) */
	235	local_irq_save(flags);
	236	config = read_c0_conf();
	237	write_c0_conf(config & ~TX39_CONF_ICE);
	238	TX39_STOP_STREAMING();
41700e73	239	protected_blast_icache_range(start, end);
1da177e4 LT	240	write_c0_conf(config);
	241	local_irq_restore(flags);
	242	}
	243	}
	244
1da177e4 LT	245	static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
1da177e4 LT	246	{
41700e73	247	unsigned long end;
1da177e4 LT	248
	249	if (((size \| addr) & (PAGE_SIZE - 1)) == 0) {
	250	end = addr + size;
	251	do {
	252	tx39_blast_dcache_page(addr);
	253	addr += PAGE_SIZE;
	254	} while(addr != end);
	255	} else if (size > dcache_size) {
	256	tx39_blast_dcache();
	257	} else {
41700e73	258	blast_dcache_range(addr, addr + size);
1da177e4 LT	259	}
	260	}
	261
	262	static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
	263	{
41700e73	264	unsigned long end;
1da177e4 LT	265
	266	if (((size \| addr) & (PAGE_SIZE - 1)) == 0) {
	267	end = addr + size;
	268	do {
	269	tx39_blast_dcache_page(addr);
	270	addr += PAGE_SIZE;
	271	} while(addr != end);
	272	} else if (size > dcache_size) {
	273	tx39_blast_dcache();
	274	} else {
41700e73	275	blast_inv_dcache_range(addr, addr + size);
1da177e4 LT	276	}
	277	}
	278
	279	static void tx39_flush_cache_sigtramp(unsigned long addr)
	280	{
	281	unsigned long ic_lsize = current_cpu_data.icache.linesz;
	282	unsigned long dc_lsize = current_cpu_data.dcache.linesz;
	283	unsigned long config;
	284	unsigned long flags;
	285
	286	protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
	287
	288	/* disable icache (set ICE#) */
	289	local_irq_save(flags);
	290	config = read_c0_conf();
	291	write_c0_conf(config & ~TX39_CONF_ICE);
	292	TX39_STOP_STREAMING();
	293	protected_flush_icache_line(addr & ~(ic_lsize - 1));
	294	write_c0_conf(config);
	295	local_irq_restore(flags);
	296	}
	297
	298	static __init void tx39_probe_cache(void)
	299	{
	300	unsigned long config;
	301
	302	config = read_c0_conf();
	303
	304	icache_size = 1 << (10 + ((config & TX39_CONF_ICS_MASK) >>
	305	TX39_CONF_ICS_SHIFT));
	306	dcache_size = 1 << (10 + ((config & TX39_CONF_DCS_MASK) >>
	307	TX39_CONF_DCS_SHIFT));
	308
	309	current_cpu_data.icache.linesz = 16;
10cc3529	310	switch (current_cpu_type()) {
1da177e4 LT	311	case CPU_TX3912:
	312	current_cpu_data.icache.ways = 1;
	313	current_cpu_data.dcache.ways = 1;
	314	current_cpu_data.dcache.linesz = 4;
	315	break;
	316
	317	case CPU_TX3927:
	318	current_cpu_data.icache.ways = 2;
	319	current_cpu_data.dcache.ways = 2;
	320	current_cpu_data.dcache.linesz = 16;
	321	break;
	322
	323	case CPU_TX3922:
	324	default:
	325	current_cpu_data.icache.ways = 1;
	326	current_cpu_data.dcache.ways = 1;
	327	current_cpu_data.dcache.linesz = 16;
	328	break;
	329	}
	330	}
	331
234fcd14	332	void __cpuinit tx39_cache_init(void)
1da177e4 LT	333	{
	334	extern void build_clear_page(void);
	335	extern void build_copy_page(void);
	336	unsigned long config;
	337
	338	config = read_c0_conf();
	339	config &= ~TX39_CONF_WBON;
	340	write_c0_conf(config);
	341
	342	tx39_probe_cache();
	343
10cc3529	344	switch (current_cpu_type()) {
1da177e4 LT	345	case CPU_TX3912:
	346	/* TX39/H core (writethru direct-map cache) */
	347	flush_cache_all = tx39h_flush_icache_all;
	348	__flush_cache_all = tx39h_flush_icache_all;
	349	flush_cache_mm = (void *) tx39h_flush_icache_all;
	350	flush_cache_range = (void *) tx39h_flush_icache_all;
	351	flush_cache_page = (void *) tx39h_flush_icache_all;
1da177e4 LT	352	flush_icache_range = (void *) tx39h_flush_icache_all;
	353
	354	flush_cache_sigtramp = (void *) tx39h_flush_icache_all;
7e3bfc7c	355	local_flush_data_cache_page = (void *) tx39h_flush_icache_all;
1da177e4 LT	356	flush_data_cache_page = (void *) tx39h_flush_icache_all;
	357
	358	_dma_cache_wback_inv = tx39h_dma_cache_wback_inv;
	359
	360	shm_align_mask = PAGE_SIZE - 1;
	361
	362	break;
	363
	364	case CPU_TX3922:
	365	case CPU_TX3927:
	366	default:
	367	/* TX39/H2,H3 core (writeback 2way-set-associative cache) */
	368	r3k_have_wired_reg = 1;
	369	write_c0_wired(0); /* set 8 on reset... */
	370	/* board-dependent init code may set WBON */
	371
	372	flush_cache_all = tx39_flush_cache_all;
	373	__flush_cache_all = tx39___flush_cache_all;
	374	flush_cache_mm = tx39_flush_cache_mm;
	375	flush_cache_range = tx39_flush_cache_range;
	376	flush_cache_page = tx39_flush_cache_page;
1da177e4 LT	377	flush_icache_range = tx39_flush_icache_range;
	378
	379	flush_cache_sigtramp = tx39_flush_cache_sigtramp;
7e3bfc7c	380	local_flush_data_cache_page = local_tx39_flush_data_cache_page;
1da177e4 LT	381	flush_data_cache_page = tx39_flush_data_cache_page;
	382
	383	_dma_cache_wback_inv = tx39_dma_cache_wback_inv;
	384	_dma_cache_wback = tx39_dma_cache_wback_inv;
	385	_dma_cache_inv = tx39_dma_cache_inv;
	386
	387	shm_align_mask = max_t(unsigned long,
	388	(dcache_size / current_cpu_data.dcache.ways) - 1,
	389	PAGE_SIZE - 1);
	390
	391	break;
	392	}
	393
	394	current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways;
	395	current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways;
	396
	397	current_cpu_data.icache.sets =
	398	current_cpu_data.icache.waysize / current_cpu_data.icache.linesz;
	399	current_cpu_data.dcache.sets =
	400	current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz;
	401
	402	if (current_cpu_data.dcache.waysize > PAGE_SIZE)
	403	current_cpu_data.dcache.flags \|= MIPS_CACHE_ALIASES;
	404
	405	current_cpu_data.icache.waybit = 0;
	406	current_cpu_data.dcache.waybit = 0;
	407
	408	printk("Primary instruction cache %ldkB, linesize %d bytes\n",
	409	icache_size >> 10, current_cpu_data.icache.linesz);
	410	printk("Primary data cache %ldkB, linesize %d bytes\n",
	411	dcache_size >> 10, current_cpu_data.dcache.linesz);
	412
	413	build_clear_page();
	414	build_copy_page();
1d40cfcd	415	tx39h_flush_icache_all();
1da177e4	416	}