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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com> | |
70342287 | 7 | * Copyright (C) 2000, 2001, 06 Ralf Baechle <ralf@linux-mips.org> |
1da177e4 LT |
8 | * swiped from i386, and cloned for MIPS by Geert, polished by Ralf. |
9 | */ | |
9a88cbb5 | 10 | |
1da177e4 | 11 | #include <linux/types.h> |
9a88cbb5 | 12 | #include <linux/dma-mapping.h> |
1da177e4 LT |
13 | #include <linux/mm.h> |
14 | #include <linux/module.h> | |
4fcc47a0 | 15 | #include <linux/scatterlist.h> |
6e86b0bf | 16 | #include <linux/string.h> |
5a0e3ad6 | 17 | #include <linux/gfp.h> |
e36863a5 | 18 | #include <linux/highmem.h> |
f4649382 | 19 | #include <linux/dma-contiguous.h> |
1da177e4 LT |
20 | |
21 | #include <asm/cache.h> | |
69f24d17 | 22 | #include <asm/cpu-type.h> |
1da177e4 LT |
23 | #include <asm/io.h> |
24 | ||
9a88cbb5 RB |
25 | #include <dma-coherence.h> |
26 | ||
885014bc | 27 | #ifdef CONFIG_DMA_MAYBE_COHERENT |
b6d92b4a SH |
28 | int coherentio = 0; /* User defined DMA coherency from command line. */ |
29 | EXPORT_SYMBOL_GPL(coherentio); | |
30 | int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */ | |
31 | ||
32 | static int __init setcoherentio(char *str) | |
33 | { | |
34 | coherentio = 1; | |
35 | pr_info("Hardware DMA cache coherency (command line)\n"); | |
36 | return 0; | |
37 | } | |
38 | early_param("coherentio", setcoherentio); | |
39 | ||
40 | static int __init setnocoherentio(char *str) | |
41 | { | |
42 | coherentio = 0; | |
43 | pr_info("Software DMA cache coherency (command line)\n"); | |
44 | return 0; | |
45 | } | |
46 | early_param("nocoherentio", setnocoherentio); | |
885014bc | 47 | #endif |
b6d92b4a | 48 | |
e36863a5 | 49 | static inline struct page *dma_addr_to_page(struct device *dev, |
3807ef3f | 50 | dma_addr_t dma_addr) |
c9d06962 | 51 | { |
e36863a5 DD |
52 | return pfn_to_page( |
53 | plat_dma_addr_to_phys(dev, dma_addr) >> PAGE_SHIFT); | |
c9d06962 FBH |
54 | } |
55 | ||
1da177e4 | 56 | /* |
f86f55d3 JQ |
57 | * The affected CPUs below in 'cpu_needs_post_dma_flush()' can |
58 | * speculatively fill random cachelines with stale data at any time, | |
59 | * requiring an extra flush post-DMA. | |
60 | * | |
1da177e4 LT |
61 | * Warning on the terminology - Linux calls an uncached area coherent; |
62 | * MIPS terminology calls memory areas with hardware maintained coherency | |
63 | * coherent. | |
0dc294c0 RB |
64 | * |
65 | * Note that the R14000 and R16000 should also be checked for in this | |
66 | * condition. However this function is only called on non-I/O-coherent | |
67 | * systems and only the R10000 and R12000 are used in such systems, the | |
68 | * SGI IP28 Indigo² rsp. SGI IP32 aka O2. | |
1da177e4 | 69 | */ |
f86f55d3 | 70 | static inline int cpu_needs_post_dma_flush(struct device *dev) |
9a88cbb5 RB |
71 | { |
72 | return !plat_device_is_coherent(dev) && | |
d451e734 | 73 | (boot_cpu_type() == CPU_R10000 || |
eb37e6dd RB |
74 | boot_cpu_type() == CPU_R12000 || |
75 | boot_cpu_type() == CPU_BMIPS5000); | |
9a88cbb5 RB |
76 | } |
77 | ||
cce335ae RB |
78 | static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp) |
79 | { | |
a2e715a8 RB |
80 | gfp_t dma_flag; |
81 | ||
cce335ae RB |
82 | /* ignore region specifiers */ |
83 | gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM); | |
84 | ||
a2e715a8 | 85 | #ifdef CONFIG_ISA |
cce335ae | 86 | if (dev == NULL) |
a2e715a8 | 87 | dma_flag = __GFP_DMA; |
cce335ae RB |
88 | else |
89 | #endif | |
a2e715a8 | 90 | #if defined(CONFIG_ZONE_DMA32) && defined(CONFIG_ZONE_DMA) |
cce335ae | 91 | if (dev->coherent_dma_mask < DMA_BIT_MASK(32)) |
a2e715a8 RB |
92 | dma_flag = __GFP_DMA; |
93 | else if (dev->coherent_dma_mask < DMA_BIT_MASK(64)) | |
94 | dma_flag = __GFP_DMA32; | |
95 | else | |
96 | #endif | |
97 | #if defined(CONFIG_ZONE_DMA32) && !defined(CONFIG_ZONE_DMA) | |
98 | if (dev->coherent_dma_mask < DMA_BIT_MASK(64)) | |
99 | dma_flag = __GFP_DMA32; | |
100 | else | |
101 | #endif | |
102 | #if defined(CONFIG_ZONE_DMA) && !defined(CONFIG_ZONE_DMA32) | |
53960059 | 103 | if (dev->coherent_dma_mask < DMA_BIT_MASK(sizeof(phys_addr_t) * 8)) |
a2e715a8 | 104 | dma_flag = __GFP_DMA; |
cce335ae RB |
105 | else |
106 | #endif | |
a2e715a8 | 107 | dma_flag = 0; |
cce335ae RB |
108 | |
109 | /* Don't invoke OOM killer */ | |
110 | gfp |= __GFP_NORETRY; | |
111 | ||
a2e715a8 | 112 | return gfp | dma_flag; |
cce335ae RB |
113 | } |
114 | ||
1e893752 | 115 | static void *mips_dma_alloc_noncoherent(struct device *dev, size_t size, |
185a8ff5 | 116 | dma_addr_t * dma_handle, gfp_t gfp) |
1da177e4 LT |
117 | { |
118 | void *ret; | |
9a88cbb5 | 119 | |
cce335ae | 120 | gfp = massage_gfp_flags(dev, gfp); |
1da177e4 | 121 | |
1da177e4 LT |
122 | ret = (void *) __get_free_pages(gfp, get_order(size)); |
123 | ||
124 | if (ret != NULL) { | |
125 | memset(ret, 0, size); | |
9a88cbb5 | 126 | *dma_handle = plat_map_dma_mem(dev, ret, size); |
1da177e4 LT |
127 | } |
128 | ||
129 | return ret; | |
130 | } | |
1da177e4 | 131 | |
48e1fd5a | 132 | static void *mips_dma_alloc_coherent(struct device *dev, size_t size, |
e8d51e54 | 133 | dma_addr_t * dma_handle, gfp_t gfp, struct dma_attrs *attrs) |
1da177e4 LT |
134 | { |
135 | void *ret; | |
f4649382 ZLK |
136 | struct page *page = NULL; |
137 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1da177e4 | 138 | |
1e893752 CH |
139 | /* |
140 | * XXX: seems like the coherent and non-coherent implementations could | |
141 | * be consolidated. | |
142 | */ | |
143 | if (dma_get_attr(DMA_ATTR_NON_CONSISTENT, attrs)) | |
144 | return mips_dma_alloc_noncoherent(dev, size, dma_handle, gfp); | |
145 | ||
cce335ae | 146 | gfp = massage_gfp_flags(dev, gfp); |
9a88cbb5 | 147 | |
f4649382 ZLK |
148 | if (IS_ENABLED(CONFIG_DMA_CMA) && !(gfp & GFP_ATOMIC)) |
149 | page = dma_alloc_from_contiguous(dev, | |
150 | count, get_order(size)); | |
151 | if (!page) | |
152 | page = alloc_pages(gfp, get_order(size)); | |
153 | ||
154 | if (!page) | |
155 | return NULL; | |
156 | ||
157 | ret = page_address(page); | |
158 | memset(ret, 0, size); | |
159 | *dma_handle = plat_map_dma_mem(dev, ret, size); | |
160 | if (!plat_device_is_coherent(dev)) { | |
161 | dma_cache_wback_inv((unsigned long) ret, size); | |
162 | if (!hw_coherentio) | |
163 | ret = UNCAC_ADDR(ret); | |
1da177e4 LT |
164 | } |
165 | ||
166 | return ret; | |
167 | } | |
168 | ||
1da177e4 | 169 | |
1e893752 CH |
170 | static void mips_dma_free_noncoherent(struct device *dev, size_t size, |
171 | void *vaddr, dma_addr_t dma_handle) | |
1da177e4 | 172 | { |
d3f634b9 | 173 | plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); |
1da177e4 LT |
174 | free_pages((unsigned long) vaddr, get_order(size)); |
175 | } | |
1da177e4 | 176 | |
48e1fd5a | 177 | static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, |
e8d51e54 | 178 | dma_addr_t dma_handle, struct dma_attrs *attrs) |
1da177e4 LT |
179 | { |
180 | unsigned long addr = (unsigned long) vaddr; | |
f4649382 ZLK |
181 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
182 | struct page *page = NULL; | |
f8ac0425 | 183 | |
1e893752 CH |
184 | if (dma_get_attr(DMA_ATTR_NON_CONSISTENT, attrs)) { |
185 | mips_dma_free_noncoherent(dev, size, vaddr, dma_handle); | |
186 | return; | |
187 | } | |
188 | ||
d3f634b9 | 189 | plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); |
11531ac2 | 190 | |
b6d92b4a | 191 | if (!plat_device_is_coherent(dev) && !hw_coherentio) |
9a88cbb5 RB |
192 | addr = CAC_ADDR(addr); |
193 | ||
f4649382 ZLK |
194 | page = virt_to_page((void *) addr); |
195 | ||
196 | if (!dma_release_from_contiguous(dev, page, count)) | |
197 | __free_pages(page, get_order(size)); | |
1da177e4 LT |
198 | } |
199 | ||
8c172467 AS |
200 | static int mips_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
201 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
202 | struct dma_attrs *attrs) | |
203 | { | |
204 | unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; | |
205 | unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
206 | unsigned long addr = (unsigned long)cpu_addr; | |
207 | unsigned long off = vma->vm_pgoff; | |
208 | unsigned long pfn; | |
209 | int ret = -ENXIO; | |
210 | ||
211 | if (!plat_device_is_coherent(dev) && !hw_coherentio) | |
212 | addr = CAC_ADDR(addr); | |
213 | ||
214 | pfn = page_to_pfn(virt_to_page((void *)addr)); | |
215 | ||
216 | if (dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs)) | |
217 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
218 | else | |
219 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
220 | ||
221 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) | |
222 | return ret; | |
223 | ||
224 | if (off < count && user_count <= (count - off)) { | |
225 | ret = remap_pfn_range(vma, vma->vm_start, | |
226 | pfn + off, | |
227 | user_count << PAGE_SHIFT, | |
228 | vma->vm_page_prot); | |
229 | } | |
230 | ||
231 | return ret; | |
232 | } | |
233 | ||
e36863a5 | 234 | static inline void __dma_sync_virtual(void *addr, size_t size, |
1da177e4 LT |
235 | enum dma_data_direction direction) |
236 | { | |
237 | switch (direction) { | |
238 | case DMA_TO_DEVICE: | |
e36863a5 | 239 | dma_cache_wback((unsigned long)addr, size); |
1da177e4 LT |
240 | break; |
241 | ||
242 | case DMA_FROM_DEVICE: | |
e36863a5 | 243 | dma_cache_inv((unsigned long)addr, size); |
1da177e4 LT |
244 | break; |
245 | ||
246 | case DMA_BIDIRECTIONAL: | |
e36863a5 | 247 | dma_cache_wback_inv((unsigned long)addr, size); |
1da177e4 LT |
248 | break; |
249 | ||
250 | default: | |
251 | BUG(); | |
252 | } | |
253 | } | |
254 | ||
e36863a5 DD |
255 | /* |
256 | * A single sg entry may refer to multiple physically contiguous | |
257 | * pages. But we still need to process highmem pages individually. | |
258 | * If highmem is not configured then the bulk of this loop gets | |
259 | * optimized out. | |
260 | */ | |
261 | static inline void __dma_sync(struct page *page, | |
262 | unsigned long offset, size_t size, enum dma_data_direction direction) | |
263 | { | |
264 | size_t left = size; | |
265 | ||
266 | do { | |
267 | size_t len = left; | |
268 | ||
269 | if (PageHighMem(page)) { | |
270 | void *addr; | |
271 | ||
272 | if (offset + len > PAGE_SIZE) { | |
273 | if (offset >= PAGE_SIZE) { | |
274 | page += offset >> PAGE_SHIFT; | |
275 | offset &= ~PAGE_MASK; | |
276 | } | |
277 | len = PAGE_SIZE - offset; | |
278 | } | |
279 | ||
280 | addr = kmap_atomic(page); | |
281 | __dma_sync_virtual(addr + offset, len, direction); | |
282 | kunmap_atomic(addr); | |
283 | } else | |
284 | __dma_sync_virtual(page_address(page) + offset, | |
285 | size, direction); | |
286 | offset = 0; | |
287 | page++; | |
288 | left -= len; | |
289 | } while (left); | |
290 | } | |
291 | ||
48e1fd5a DD |
292 | static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr, |
293 | size_t size, enum dma_data_direction direction, struct dma_attrs *attrs) | |
1da177e4 | 294 | { |
f86f55d3 | 295 | if (cpu_needs_post_dma_flush(dev)) |
e36863a5 DD |
296 | __dma_sync(dma_addr_to_page(dev, dma_addr), |
297 | dma_addr & ~PAGE_MASK, size, direction); | |
0acbfc66 | 298 | plat_post_dma_flush(dev); |
d3f634b9 | 299 | plat_unmap_dma_mem(dev, dma_addr, size, direction); |
1da177e4 LT |
300 | } |
301 | ||
1e51714c | 302 | static int mips_dma_map_sg(struct device *dev, struct scatterlist *sglist, |
48e1fd5a | 303 | int nents, enum dma_data_direction direction, struct dma_attrs *attrs) |
1da177e4 LT |
304 | { |
305 | int i; | |
1e51714c | 306 | struct scatterlist *sg; |
1da177e4 | 307 | |
1e51714c | 308 | for_each_sg(sglist, sg, nents, i) { |
e36863a5 DD |
309 | if (!plat_device_is_coherent(dev)) |
310 | __dma_sync(sg_page(sg), sg->offset, sg->length, | |
311 | direction); | |
4954a9a2 J |
312 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
313 | sg->dma_length = sg->length; | |
314 | #endif | |
e36863a5 DD |
315 | sg->dma_address = plat_map_dma_mem_page(dev, sg_page(sg)) + |
316 | sg->offset; | |
1da177e4 LT |
317 | } |
318 | ||
319 | return nents; | |
320 | } | |
321 | ||
48e1fd5a DD |
322 | static dma_addr_t mips_dma_map_page(struct device *dev, struct page *page, |
323 | unsigned long offset, size_t size, enum dma_data_direction direction, | |
324 | struct dma_attrs *attrs) | |
1da177e4 | 325 | { |
48e1fd5a | 326 | if (!plat_device_is_coherent(dev)) |
e36863a5 | 327 | __dma_sync(page, offset, size, direction); |
1da177e4 | 328 | |
e36863a5 | 329 | return plat_map_dma_mem_page(dev, page) + offset; |
1da177e4 LT |
330 | } |
331 | ||
1e51714c | 332 | static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sglist, |
48e1fd5a DD |
333 | int nhwentries, enum dma_data_direction direction, |
334 | struct dma_attrs *attrs) | |
1da177e4 | 335 | { |
1da177e4 | 336 | int i; |
1e51714c | 337 | struct scatterlist *sg; |
1da177e4 | 338 | |
1e51714c | 339 | for_each_sg(sglist, sg, nhwentries, i) { |
9a88cbb5 | 340 | if (!plat_device_is_coherent(dev) && |
e36863a5 DD |
341 | direction != DMA_TO_DEVICE) |
342 | __dma_sync(sg_page(sg), sg->offset, sg->length, | |
343 | direction); | |
d3f634b9 | 344 | plat_unmap_dma_mem(dev, sg->dma_address, sg->length, direction); |
1da177e4 LT |
345 | } |
346 | } | |
347 | ||
48e1fd5a DD |
348 | static void mips_dma_sync_single_for_cpu(struct device *dev, |
349 | dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) | |
1da177e4 | 350 | { |
f86f55d3 | 351 | if (cpu_needs_post_dma_flush(dev)) |
e36863a5 DD |
352 | __dma_sync(dma_addr_to_page(dev, dma_handle), |
353 | dma_handle & ~PAGE_MASK, size, direction); | |
0acbfc66 | 354 | plat_post_dma_flush(dev); |
1da177e4 LT |
355 | } |
356 | ||
48e1fd5a DD |
357 | static void mips_dma_sync_single_for_device(struct device *dev, |
358 | dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) | |
1da177e4 | 359 | { |
e36863a5 DD |
360 | if (!plat_device_is_coherent(dev)) |
361 | __dma_sync(dma_addr_to_page(dev, dma_handle), | |
362 | dma_handle & ~PAGE_MASK, size, direction); | |
1da177e4 LT |
363 | } |
364 | ||
48e1fd5a | 365 | static void mips_dma_sync_sg_for_cpu(struct device *dev, |
1e51714c AM |
366 | struct scatterlist *sglist, int nelems, |
367 | enum dma_data_direction direction) | |
1da177e4 LT |
368 | { |
369 | int i; | |
1e51714c | 370 | struct scatterlist *sg; |
42a3b4f2 | 371 | |
1e51714c AM |
372 | if (cpu_needs_post_dma_flush(dev)) { |
373 | for_each_sg(sglist, sg, nelems, i) { | |
e36863a5 DD |
374 | __dma_sync(sg_page(sg), sg->offset, sg->length, |
375 | direction); | |
1e51714c AM |
376 | } |
377 | } | |
0acbfc66 | 378 | plat_post_dma_flush(dev); |
1da177e4 LT |
379 | } |
380 | ||
48e1fd5a | 381 | static void mips_dma_sync_sg_for_device(struct device *dev, |
1e51714c AM |
382 | struct scatterlist *sglist, int nelems, |
383 | enum dma_data_direction direction) | |
1da177e4 LT |
384 | { |
385 | int i; | |
1e51714c | 386 | struct scatterlist *sg; |
1da177e4 | 387 | |
1e51714c AM |
388 | if (!plat_device_is_coherent(dev)) { |
389 | for_each_sg(sglist, sg, nelems, i) { | |
e36863a5 DD |
390 | __dma_sync(sg_page(sg), sg->offset, sg->length, |
391 | direction); | |
1e51714c AM |
392 | } |
393 | } | |
1da177e4 LT |
394 | } |
395 | ||
48e1fd5a | 396 | int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) |
1da177e4 | 397 | { |
4e7f7266 | 398 | return 0; |
1da177e4 LT |
399 | } |
400 | ||
48e1fd5a | 401 | int mips_dma_supported(struct device *dev, u64 mask) |
1da177e4 | 402 | { |
843aef49 | 403 | return plat_dma_supported(dev, mask); |
1da177e4 LT |
404 | } |
405 | ||
a3aad4aa | 406 | void dma_cache_sync(struct device *dev, void *vaddr, size_t size, |
48e1fd5a | 407 | enum dma_data_direction direction) |
1da177e4 | 408 | { |
9a88cbb5 | 409 | BUG_ON(direction == DMA_NONE); |
1da177e4 | 410 | |
9a88cbb5 | 411 | if (!plat_device_is_coherent(dev)) |
e36863a5 | 412 | __dma_sync_virtual(vaddr, size, direction); |
1da177e4 LT |
413 | } |
414 | ||
a3aad4aa RB |
415 | EXPORT_SYMBOL(dma_cache_sync); |
416 | ||
48e1fd5a | 417 | static struct dma_map_ops mips_default_dma_map_ops = { |
e8d51e54 AP |
418 | .alloc = mips_dma_alloc_coherent, |
419 | .free = mips_dma_free_coherent, | |
8c172467 | 420 | .mmap = mips_dma_mmap, |
48e1fd5a DD |
421 | .map_page = mips_dma_map_page, |
422 | .unmap_page = mips_dma_unmap_page, | |
423 | .map_sg = mips_dma_map_sg, | |
424 | .unmap_sg = mips_dma_unmap_sg, | |
425 | .sync_single_for_cpu = mips_dma_sync_single_for_cpu, | |
426 | .sync_single_for_device = mips_dma_sync_single_for_device, | |
427 | .sync_sg_for_cpu = mips_dma_sync_sg_for_cpu, | |
428 | .sync_sg_for_device = mips_dma_sync_sg_for_device, | |
429 | .mapping_error = mips_dma_mapping_error, | |
430 | .dma_supported = mips_dma_supported | |
431 | }; | |
432 | ||
433 | struct dma_map_ops *mips_dma_map_ops = &mips_default_dma_map_ops; | |
434 | EXPORT_SYMBOL(mips_dma_map_ops); | |
435 | ||
436 | #define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16) | |
437 | ||
438 | static int __init mips_dma_init(void) | |
439 | { | |
440 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
441 | ||
442 | return 0; | |
443 | } | |
444 | fs_initcall(mips_dma_init); |