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MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT
[mirror_ubuntu-artful-kernel.git] / arch / mips / mm / init.c
CommitLineData
1da177e4
LT
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 2000 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
9 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
10 */
b868868a 11#include <linux/bug.h>
1da177e4
LT
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
631330f5 16#include <linux/smp.h>
1da177e4
LT
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/string.h>
20#include <linux/types.h>
21#include <linux/pagemap.h>
22#include <linux/ptrace.h>
23#include <linux/mman.h>
24#include <linux/mm.h>
25#include <linux/bootmem.h>
26#include <linux/highmem.h>
27#include <linux/swap.h>
3d503753 28#include <linux/proc_fs.h>
22a9835c 29#include <linux/pfn.h>
0f334a3e 30#include <linux/hardirq.h>
5a0e3ad6 31#include <linux/gfp.h>
2f96b8c1 32#include <linux/kcore.h>
1da177e4 33
9975e77d 34#include <asm/asm-offsets.h>
1da177e4
LT
35#include <asm/bootinfo.h>
36#include <asm/cachectl.h>
37#include <asm/cpu.h>
38#include <asm/dma.h>
f8829cae 39#include <asm/kmap_types.h>
1da177e4
LT
40#include <asm/mmu_context.h>
41#include <asm/sections.h>
42#include <asm/pgtable.h>
43#include <asm/pgalloc.h>
44#include <asm/tlb.h>
f8829cae
RB
45#include <asm/fixmap.h>
46
1da177e4
LT
47/*
48 * We have up to 8 empty zeroed pages so we can map one of the right colour
70342287 49 * when needed. This is necessary only on R4000 / R4400 SC and MC versions
1da177e4
LT
50 * where we have to avoid VCED / VECI exceptions for good performance at
51 * any price. Since page is never written to after the initialization we
52 * don't have to care about aliases on other CPUs.
53 */
54unsigned long empty_zero_page, zero_page_mask;
497d2adc 55EXPORT_SYMBOL_GPL(empty_zero_page);
0b70068e 56EXPORT_SYMBOL(zero_page_mask);
1da177e4
LT
57
58/*
59 * Not static inline because used by IP27 special magic initialization code
60 */
31605922 61void setup_zero_pages(void)
1da177e4 62{
31605922 63 unsigned int order, i;
1da177e4
LT
64 struct page *page;
65
66 if (cpu_has_vce)
67 order = 3;
68 else
69 order = 0;
70
71 empty_zero_page = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
72 if (!empty_zero_page)
73 panic("Oh boy, that early out of memory?");
74
99e3b942 75 page = virt_to_page((void *)empty_zero_page);
8dfcc9ba 76 split_page(page, order);
31605922
JL
77 for (i = 0; i < (1 << order); i++, page++)
78 mark_page_reserved(page);
1da177e4 79
31605922 80 zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK;
1da177e4
LT
81}
82
e2a9e5ad 83static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot)
f8829cae
RB
84{
85 enum fixed_addresses idx;
86 unsigned long vaddr, flags, entrylo;
87 unsigned long old_ctx;
88 pte_t pte;
89 int tlbidx;
90
b868868a
RB
91 BUG_ON(Page_dcache_dirty(page));
92
bdb43806 93 pagefault_disable();
f8829cae 94 idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
0f334a3e 95 idx += in_interrupt() ? FIX_N_COLOURS : 0;
f8829cae 96 vaddr = __fix_to_virt(FIX_CMAP_END - idx);
e2a9e5ad 97 pte = mk_pte(page, prot);
34adb28d 98#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
f8829cae
RB
99 entrylo = pte.pte_high;
100#else
6dd9344c 101 entrylo = pte_to_entrylo(pte_val(pte));
f8829cae
RB
102#endif
103
b633648c 104 local_irq_save(flags);
f8829cae
RB
105 old_ctx = read_c0_entryhi();
106 write_c0_entryhi(vaddr & (PAGE_MASK << 1));
107 write_c0_entrylo0(entrylo);
108 write_c0_entrylo1(entrylo);
f8829cae
RB
109 tlbidx = read_c0_wired();
110 write_c0_wired(tlbidx + 1);
111 write_c0_index(tlbidx);
112 mtc0_tlbw_hazard();
113 tlb_write_indexed();
f8829cae
RB
114 tlbw_use_hazard();
115 write_c0_entryhi(old_ctx);
b633648c 116 local_irq_restore(flags);
f8829cae
RB
117
118 return (void*) vaddr;
119}
120
e2a9e5ad
PB
121void *kmap_coherent(struct page *page, unsigned long addr)
122{
123 return __kmap_pgprot(page, addr, PAGE_KERNEL);
124}
125
126void *kmap_noncoherent(struct page *page, unsigned long addr)
127{
128 return __kmap_pgprot(page, addr, PAGE_KERNEL_NC);
129}
130
eacb9d61 131void kunmap_coherent(void)
f8829cae 132{
f8829cae
RB
133 unsigned int wired;
134 unsigned long flags, old_ctx;
135
b633648c 136 local_irq_save(flags);
f8829cae
RB
137 old_ctx = read_c0_entryhi();
138 wired = read_c0_wired() - 1;
139 write_c0_wired(wired);
140 write_c0_index(wired);
141 write_c0_entryhi(UNIQUE_ENTRYHI(wired));
142 write_c0_entrylo0(0);
143 write_c0_entrylo1(0);
144 mtc0_tlbw_hazard();
145 tlb_write_indexed();
146 tlbw_use_hazard();
147 write_c0_entryhi(old_ctx);
b633648c 148 local_irq_restore(flags);
bdb43806 149 pagefault_enable();
f8829cae
RB
150}
151
bcd02280
AN
152void copy_user_highpage(struct page *to, struct page *from,
153 unsigned long vaddr, struct vm_area_struct *vma)
154{
155 void *vfrom, *vto;
156
9c02048f 157 vto = kmap_atomic(to);
9a74b3eb
RB
158 if (cpu_has_dc_aliases &&
159 page_mapped(from) && !Page_dcache_dirty(from)) {
bcd02280
AN
160 vfrom = kmap_coherent(from, vaddr);
161 copy_page(vto, vfrom);
eacb9d61 162 kunmap_coherent();
bcd02280 163 } else {
9c02048f 164 vfrom = kmap_atomic(from);
bcd02280 165 copy_page(vto, vfrom);
9c02048f 166 kunmap_atomic(vfrom);
bcd02280 167 }
39b8d525 168 if ((!cpu_has_ic_fills_f_dc) ||
bcd02280
AN
169 pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
170 flush_data_cache_page((unsigned long)vto);
9c02048f 171 kunmap_atomic(vto);
bcd02280
AN
172 /* Make sure this page is cleared on other CPU's too before using it */
173 smp_wmb();
174}
175
f8829cae
RB
176void copy_to_user_page(struct vm_area_struct *vma,
177 struct page *page, unsigned long vaddr, void *dst, const void *src,
178 unsigned long len)
179{
9a74b3eb
RB
180 if (cpu_has_dc_aliases &&
181 page_mapped(page) && !Page_dcache_dirty(page)) {
f8829cae
RB
182 void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
183 memcpy(vto, src, len);
eacb9d61 184 kunmap_coherent();
985c30ef 185 } else {
f8829cae 186 memcpy(dst, src, len);
985c30ef
RB
187 if (cpu_has_dc_aliases)
188 SetPageDcacheDirty(page);
189 }
f8829cae
RB
190 if ((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc)
191 flush_cache_page(vma, vaddr, page_to_pfn(page));
192}
193
f8829cae
RB
194void copy_from_user_page(struct vm_area_struct *vma,
195 struct page *page, unsigned long vaddr, void *dst, const void *src,
196 unsigned long len)
197{
9a74b3eb
RB
198 if (cpu_has_dc_aliases &&
199 page_mapped(page) && !Page_dcache_dirty(page)) {
985c30ef 200 void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
f8829cae 201 memcpy(dst, vfrom, len);
eacb9d61 202 kunmap_coherent();
985c30ef 203 } else {
f8829cae 204 memcpy(dst, src, len);
985c30ef
RB
205 if (cpu_has_dc_aliases)
206 SetPageDcacheDirty(page);
207 }
f8829cae 208}
bf9621aa 209EXPORT_SYMBOL_GPL(copy_from_user_page);
f8829cae 210
84fd089a 211void __init fixrange_init(unsigned long start, unsigned long end,
1da177e4
LT
212 pgd_t *pgd_base)
213{
b633648c 214#ifdef CONFIG_HIGHMEM
1da177e4 215 pgd_t *pgd;
c6e8b587 216 pud_t *pud;
1da177e4
LT
217 pmd_t *pmd;
218 pte_t *pte;
c6e8b587 219 int i, j, k;
1da177e4
LT
220 unsigned long vaddr;
221
222 vaddr = start;
223 i = __pgd_offset(vaddr);
c6e8b587
RB
224 j = __pud_offset(vaddr);
225 k = __pmd_offset(vaddr);
1da177e4
LT
226 pgd = pgd_base + i;
227
464fd83e 228 for ( ; (i < PTRS_PER_PGD) && (vaddr < end); pgd++, i++) {
c6e8b587 229 pud = (pud_t *)pgd;
464fd83e 230 for ( ; (j < PTRS_PER_PUD) && (vaddr < end); pud++, j++) {
c6e8b587 231 pmd = (pmd_t *)pud;
464fd83e 232 for (; (k < PTRS_PER_PMD) && (vaddr < end); pmd++, k++) {
c6e8b587
RB
233 if (pmd_none(*pmd)) {
234 pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
f8829cae 235 set_pmd(pmd, __pmd((unsigned long)pte));
b72b7092 236 BUG_ON(pte != pte_offset_kernel(pmd, 0));
c6e8b587
RB
237 }
238 vaddr += PMD_SIZE;
1da177e4 239 }
c6e8b587 240 k = 0;
1da177e4
LT
241 }
242 j = 0;
243 }
f8829cae 244#endif
1da177e4 245}
1da177e4 246
b4819b59 247#ifndef CONFIG_NEED_MULTIPLE_NODES
61ef2489 248int page_is_ram(unsigned long pagenr)
565200a1
AN
249{
250 int i;
251
252 for (i = 0; i < boot_mem_map.nr_map; i++) {
253 unsigned long addr, end;
254
43064c0c
DD
255 switch (boot_mem_map.map[i].type) {
256 case BOOT_MEM_RAM:
257 case BOOT_MEM_INIT_RAM:
258 break;
259 default:
565200a1
AN
260 /* not usable memory */
261 continue;
43064c0c 262 }
565200a1
AN
263
264 addr = PFN_UP(boot_mem_map.map[i].addr);
265 end = PFN_DOWN(boot_mem_map.map[i].addr +
266 boot_mem_map.map[i].size);
267
268 if (pagenr >= addr && pagenr < end)
269 return 1;
270 }
271
272 return 0;
273}
274
1da177e4
LT
275void __init paging_init(void)
276{
cce335ae 277 unsigned long max_zone_pfns[MAX_NR_ZONES];
d3ce0e98 278 unsigned long lastpfn __maybe_unused;
1da177e4
LT
279
280 pagetable_init();
281
282#ifdef CONFIG_HIGHMEM
283 kmap_init();
284#endif
05502339 285#ifdef CONFIG_ZONE_DMA
cce335ae 286 max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
1da177e4 287#endif
cce335ae
RB
288#ifdef CONFIG_ZONE_DMA32
289 max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
290#endif
291 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
292 lastpfn = max_low_pfn;
1da177e4 293#ifdef CONFIG_HIGHMEM
cce335ae
RB
294 max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
295 lastpfn = highend_pfn;
cbb8fc07 296
cce335ae 297 if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
cbb8fc07 298 printk(KERN_WARNING "This processor doesn't support highmem."
cce335ae
RB
299 " %ldk highmem ignored\n",
300 (highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
301 max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
302 lastpfn = max_low_pfn;
cbb8fc07 303 }
1da177e4
LT
304#endif
305
cce335ae 306 free_area_init_nodes(max_zone_pfns);
1da177e4
LT
307}
308
3d503753
DJ
309#ifdef CONFIG_64BIT
310static struct kcore_list kcore_kseg0;
311#endif
312
1132137e 313static inline void mem_init_free_highmem(void)
1da177e4 314{
1132137e
JL
315#ifdef CONFIG_HIGHMEM
316 unsigned long tmp;
1da177e4 317
1132137e
JL
318 for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
319 struct page *page = pfn_to_page(tmp);
320
321 if (!page_is_ram(tmp))
322 SetPageReserved(page);
323 else
324 free_highmem_page(page);
325 }
326#endif
327}
328
ab9988a3
PB
329unsigned __weak platform_maar_init(unsigned num_maars)
330{
331 return 0;
332}
333
334static void maar_init(void)
335{
336 unsigned num_maars, used, i;
337
338 if (!cpu_has_maar)
339 return;
340
341 /* Detect the number of MAARs */
342 write_c0_maari(~0);
343 back_to_back_c0_hazard();
344 num_maars = read_c0_maari() + 1;
345
346 /* MAARs should be in pairs */
347 WARN_ON(num_maars % 2);
348
349 /* Configure the required MAARs */
350 used = platform_maar_init(num_maars / 2);
351
352 /* Disable any further MAARs */
353 for (i = (used * 2); i < num_maars; i++) {
354 write_c0_maari(i);
355 back_to_back_c0_hazard();
356 write_c0_maar(0);
357 back_to_back_c0_hazard();
358 }
359}
360
1132137e
JL
361void __init mem_init(void)
362{
1da177e4
LT
363#ifdef CONFIG_HIGHMEM
364#ifdef CONFIG_DISCONTIGMEM
365#error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet"
366#endif
b6da0ffb 367 max_mapnr = highend_pfn ? highend_pfn : max_low_pfn;
1da177e4 368#else
565200a1 369 max_mapnr = max_low_pfn;
1da177e4
LT
370#endif
371 high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
372
ab9988a3 373 maar_init();
0c988534 374 free_all_bootmem();
31605922 375 setup_zero_pages(); /* Setup zeroed pages. */
1132137e
JL
376 mem_init_free_highmem();
377 mem_init_print_info(NULL);
1da177e4 378
3d503753
DJ
379#ifdef CONFIG_64BIT
380 if ((unsigned long) &_text > (unsigned long) CKSEG0)
381 /* The -4 is a hack so that user tools don't have to handle
382 the overflow. */
c30bb2a2
KH
383 kclist_add(&kcore_kseg0, (void *) CKSEG0,
384 0x80000000 - 4, KCORE_TEXT);
3d503753 385#endif
1da177e4 386}
b4819b59 387#endif /* !CONFIG_NEED_MULTIPLE_NODES */
1da177e4 388
c44e8d5e 389void free_init_pages(const char *what, unsigned long begin, unsigned long end)
6fd11a21 390{
acd86b86 391 unsigned long pfn;
6fd11a21 392
acd86b86
FBH
393 for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
394 struct page *page = pfn_to_page(pfn);
395 void *addr = phys_to_virt(PFN_PHYS(pfn));
396
acd86b86 397 memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
31605922 398 free_reserved_page(page);
6fd11a21
RB
399 }
400 printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
401}
402
1da177e4
LT
403#ifdef CONFIG_BLK_DEV_INITRD
404void free_initrd_mem(unsigned long start, unsigned long end)
405{
11199692
JL
406 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
407 "initrd");
1da177e4
LT
408}
409#endif
410
0893d3fb
MC
411void (*free_init_pages_eva)(void *begin, void *end) = NULL;
412
fb4bb133 413void __init_refok free_initmem(void)
1da177e4 414{
c44e8d5e 415 prom_free_prom_memory();
0893d3fb
MC
416 /*
417 * Let the platform define a specific function to free the
418 * init section since EVA may have used any possible mapping
419 * between virtual and physical addresses.
420 */
421 if (free_init_pages_eva)
422 free_init_pages_eva((void *)&__init_begin, (void *)&__init_end);
423 else
424 free_initmem_default(POISON_FREE_INITMEM);
1da177e4 425}
69a6c312 426
82622284 427#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
69a6c312 428unsigned long pgd_current[NR_CPUS];
82622284 429#endif
9975e77d
RB
430
431/*
432 * gcc 3.3 and older have trouble determining that PTRS_PER_PGD and PGD_ORDER
433 * are constants. So we use the variants from asm-offset.h until that gcc
434 * will officially be retired.
485172b3
DD
435 *
436 * Align swapper_pg_dir in to 64K, allows its address to be loaded
437 * with a single LUI instruction in the TLB handlers. If we used
438 * __aligned(64K), its size would get rounded up to the alignment
439 * size, and waste space. So we place it in its own section and align
440 * it in the linker script.
9975e77d 441 */
485172b3 442pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(.bss..swapper_pg_dir);
325f8a0a 443#ifndef __PAGETABLE_PMD_FOLDED
485172b3 444pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
69a6c312 445#endif
485172b3 446pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;