[mirror_ubuntu-artful-kernel.git] / arch / mips / mm / init.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 - 2000 Ralf Baechle
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/pagemap.h>
#include <linux/ptrace.h>
#include <linux/mman.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <linux/highmem.h>
#include <linux/swap.h>
#include <linux/proc_fs.h>
#include <linux/pfn.h>
#include <linux/hardirq.h>
#include <linux/gfp.h>
#include <linux/kcore.h>

#include <asm/asm-offsets.h>
#include <asm/bootinfo.h>
#include <asm/cachectl.h>
#include <asm/cpu.h>
#include <asm/dma.h>
#include <asm/kmap_types.h>
#include <asm/mmu_context.h>
#include <asm/sections.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/tlb.h>
#include <asm/fixmap.h>

/* Atomicity and interruptability */
#ifdef CONFIG_MIPS_MT_SMTC

#include <asm/mipsmtregs.h>

#define ENTER_CRITICAL(flags) \
	{ \
	unsigned int mvpflags; \
	local_irq_save(flags);\
	mvpflags = dvpe()
#define EXIT_CRITICAL(flags) \
	evpe(mvpflags); \
	local_irq_restore(flags); \
	}
#else

#define ENTER_CRITICAL(flags) local_irq_save(flags)
#define EXIT_CRITICAL(flags) local_irq_restore(flags)

#endif /* CONFIG_MIPS_MT_SMTC */

/*
 * We have up to 8 empty zeroed pages so we can map one of the right colour
 * when needed.	 This is necessary only on R4000 / R4400 SC and MC versions
 * where we have to avoid VCED / VECI exceptions for good performance at
 * any price.  Since page is never written to after the initialization we
 * don't have to care about aliases on other CPUs.
 */
unsigned long empty_zero_page, zero_page_mask;
EXPORT_SYMBOL_GPL(empty_zero_page);

/*
 * Not static inline because used by IP27 special magic initialization code
 */
void setup_zero_pages(void)
{
	unsigned int order, i;
	struct page *page;

	if (cpu_has_vce)
		order = 3;
	else
		order = 0;

	empty_zero_page = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
	if (!empty_zero_page)
		panic("Oh boy, that early out of memory?");

	page = virt_to_page((void *)empty_zero_page);
	split_page(page, order);
	for (i = 0; i < (1 << order); i++, page++)
		mark_page_reserved(page);

	zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK;
}

#ifdef CONFIG_MIPS_MT_SMTC
static pte_t *kmap_coherent_pte;
static void __init kmap_coherent_init(void)
{
	unsigned long vaddr;

	/* cache the first coherent kmap pte */
	vaddr = __fix_to_virt(FIX_CMAP_BEGIN);
	kmap_coherent_pte = kmap_get_fixmap_pte(vaddr);
}
#else
static inline void kmap_coherent_init(void) {}
#endif

void *kmap_coherent(struct page *page, unsigned long addr)
{
	enum fixed_addresses idx;
	unsigned long vaddr, flags, entrylo;
	unsigned long old_ctx;
	pte_t pte;
	int tlbidx;

	BUG_ON(Page_dcache_dirty(page));

	inc_preempt_count();
	idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
#ifdef CONFIG_MIPS_MT_SMTC
	idx += FIX_N_COLOURS * smp_processor_id() +
		(in_interrupt() ? (FIX_N_COLOURS * NR_CPUS) : 0);
#else
	idx += in_interrupt() ? FIX_N_COLOURS : 0;
#endif
	vaddr = __fix_to_virt(FIX_CMAP_END - idx);
	pte = mk_pte(page, PAGE_KERNEL);
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
	entrylo = pte.pte_high;
#else
	entrylo = pte_to_entrylo(pte_val(pte));
#endif

	ENTER_CRITICAL(flags);
	old_ctx = read_c0_entryhi();
	write_c0_entryhi(vaddr & (PAGE_MASK << 1));
	write_c0_entrylo0(entrylo);
	write_c0_entrylo1(entrylo);
#ifdef CONFIG_MIPS_MT_SMTC
	set_pte(kmap_coherent_pte - (FIX_CMAP_END - idx), pte);
	/* preload TLB instead of local_flush_tlb_one() */
	mtc0_tlbw_hazard();
	tlb_probe();
	tlb_probe_hazard();
	tlbidx = read_c0_index();
	mtc0_tlbw_hazard();
	if (tlbidx < 0)
		tlb_write_random();
	else
		tlb_write_indexed();
#else
	tlbidx = read_c0_wired();
	write_c0_wired(tlbidx + 1);
	write_c0_index(tlbidx);
	mtc0_tlbw_hazard();
	tlb_write_indexed();
#endif
	tlbw_use_hazard();
	write_c0_entryhi(old_ctx);
	EXIT_CRITICAL(flags);

	return (void*) vaddr;
}

#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))

void kunmap_coherent(void)
{
#ifndef CONFIG_MIPS_MT_SMTC
	unsigned int wired;
	unsigned long flags, old_ctx;

	ENTER_CRITICAL(flags);
	old_ctx = read_c0_entryhi();
	wired = read_c0_wired() - 1;
	write_c0_wired(wired);
	write_c0_index(wired);
	write_c0_entryhi(UNIQUE_ENTRYHI(wired));
	write_c0_entrylo0(0);
	write_c0_entrylo1(0);
	mtc0_tlbw_hazard();
	tlb_write_indexed();
	tlbw_use_hazard();
	write_c0_entryhi(old_ctx);
	EXIT_CRITICAL(flags);
#endif
	dec_preempt_count();
	preempt_check_resched();
}

void copy_user_highpage(struct page *to, struct page *from,
	unsigned long vaddr, struct vm_area_struct *vma)
{
	void *vfrom, *vto;

	vto = kmap_atomic(to);
	if (cpu_has_dc_aliases &&
	    page_mapped(from) && !Page_dcache_dirty(from)) {
		vfrom = kmap_coherent(from, vaddr);
		copy_page(vto, vfrom);
		kunmap_coherent();
	} else {
		vfrom = kmap_atomic(from);
		copy_page(vto, vfrom);
		kunmap_atomic(vfrom);
	}
	if ((!cpu_has_ic_fills_f_dc) ||
	    pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
		flush_data_cache_page((unsigned long)vto);
	kunmap_atomic(vto);
	/* Make sure this page is cleared on other CPU's too before using it */
	smp_wmb();
}

void copy_to_user_page(struct vm_area_struct *vma,
	struct page *page, unsigned long vaddr, void *dst, const void *src,
	unsigned long len)
{
	if (cpu_has_dc_aliases &&
	    page_mapped(page) && !Page_dcache_dirty(page)) {
		void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
		memcpy(vto, src, len);
		kunmap_coherent();
	} else {
		memcpy(dst, src, len);
		if (cpu_has_dc_aliases)
			SetPageDcacheDirty(page);
	}
	if ((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc)
		flush_cache_page(vma, vaddr, page_to_pfn(page));
}

void copy_from_user_page(struct vm_area_struct *vma,
	struct page *page, unsigned long vaddr, void *dst, const void *src,
	unsigned long len)
{
	if (cpu_has_dc_aliases &&
	    page_mapped(page) && !Page_dcache_dirty(page)) {
		void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
		memcpy(dst, vfrom, len);
		kunmap_coherent();
	} else {
		memcpy(dst, src, len);
		if (cpu_has_dc_aliases)
			SetPageDcacheDirty(page);
	}
}

void __init fixrange_init(unsigned long start, unsigned long end,
	pgd_t *pgd_base)
{
#if defined(CONFIG_HIGHMEM) || defined(CONFIG_MIPS_MT_SMTC)
	pgd_t *pgd;
	pud_t *pud;
	pmd_t *pmd;
	pte_t *pte;
	int i, j, k;
	unsigned long vaddr;

	vaddr = start;
	i = __pgd_offset(vaddr);
	j = __pud_offset(vaddr);
	k = __pmd_offset(vaddr);
	pgd = pgd_base + i;

	for ( ; (i < PTRS_PER_PGD) && (vaddr < end); pgd++, i++) {
		pud = (pud_t *)pgd;
		for ( ; (j < PTRS_PER_PUD) && (vaddr < end); pud++, j++) {
			pmd = (pmd_t *)pud;
			for (; (k < PTRS_PER_PMD) && (vaddr < end); pmd++, k++) {
				if (pmd_none(*pmd)) {
					pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
					set_pmd(pmd, __pmd((unsigned long)pte));
					BUG_ON(pte != pte_offset_kernel(pmd, 0));
				}
				vaddr += PMD_SIZE;
			}
			k = 0;
		}
		j = 0;
	}
#endif
}

#ifndef CONFIG_NEED_MULTIPLE_NODES
int page_is_ram(unsigned long pagenr)
{
	int i;

	for (i = 0; i < boot_mem_map.nr_map; i++) {
		unsigned long addr, end;

		switch (boot_mem_map.map[i].type) {
		case BOOT_MEM_RAM:
		case BOOT_MEM_INIT_RAM:
			break;
		default:
			/* not usable memory */
			continue;
		}

		addr = PFN_UP(boot_mem_map.map[i].addr);
		end = PFN_DOWN(boot_mem_map.map[i].addr +
			       boot_mem_map.map[i].size);

		if (pagenr >= addr && pagenr < end)
			return 1;
	}

	return 0;
}

void __init paging_init(void)
{
	unsigned long max_zone_pfns[MAX_NR_ZONES];
	unsigned long lastpfn __maybe_unused;

	pagetable_init();

#ifdef CONFIG_HIGHMEM
	kmap_init();
#endif
	kmap_coherent_init();

#ifdef CONFIG_ZONE_DMA
	max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
#endif
#ifdef CONFIG_ZONE_DMA32
	max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
#endif
	max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
	lastpfn = max_low_pfn;
#ifdef CONFIG_HIGHMEM
	max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
	lastpfn = highend_pfn;

	if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
		printk(KERN_WARNING "This processor doesn't support highmem."
		       " %ldk highmem ignored\n",
		       (highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
		max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
		lastpfn = max_low_pfn;
	}
#endif

	free_area_init_nodes(max_zone_pfns);
}

#ifdef CONFIG_64BIT
static struct kcore_list kcore_kseg0;
#endif

static inline void mem_init_free_highmem(void)
{
#ifdef CONFIG_HIGHMEM
	unsigned long tmp;

	for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
		struct page *page = pfn_to_page(tmp);

		if (!page_is_ram(tmp))
			SetPageReserved(page);
		else
			free_highmem_page(page);
	}
#endif
}

void __init mem_init(void)
{
#ifdef CONFIG_HIGHMEM
#ifdef CONFIG_DISCONTIGMEM
#error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet"
#endif
	max_mapnr = highend_pfn ? highend_pfn : max_low_pfn;
#else
	max_mapnr = max_low_pfn;
#endif
	high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);

	free_all_bootmem();
	setup_zero_pages();	/* Setup zeroed pages.  */
	mem_init_free_highmem();
	mem_init_print_info(NULL);

#ifdef CONFIG_64BIT
	if ((unsigned long) &_text > (unsigned long) CKSEG0)
		/* The -4 is a hack so that user tools don't have to handle
		   the overflow.  */
		kclist_add(&kcore_kseg0, (void *) CKSEG0,
				0x80000000 - 4, KCORE_TEXT);
#endif
}
#endif /* !CONFIG_NEED_MULTIPLE_NODES */

void free_init_pages(const char *what, unsigned long begin, unsigned long end)
{
	unsigned long pfn;

	for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
		struct page *page = pfn_to_page(pfn);
		void *addr = phys_to_virt(PFN_PHYS(pfn));

		memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
		free_reserved_page(page);
	}
	printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
}

#ifdef CONFIG_BLK_DEV_INITRD
void free_initrd_mem(unsigned long start, unsigned long end)
{
	free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
			   "initrd");
}
#endif

void __init_refok free_initmem(void)
{
	prom_free_prom_memory();
	free_initmem_default(POISON_FREE_INITMEM);
}

#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
unsigned long pgd_current[NR_CPUS];
#endif

/*
 * gcc 3.3 and older have trouble determining that PTRS_PER_PGD and PGD_ORDER
 * are constants.  So we use the variants from asm-offset.h until that gcc
 * will officially be retired.
 *
 * Align swapper_pg_dir in to 64K, allows its address to be loaded
 * with a single LUI instruction in the TLB handlers.  If we used
 * __aligned(64K), its size would get rounded up to the alignment
 * size, and waste space.  So we place it in its own section and align
 * it in the linker script.
 */
pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(.bss..swapper_pg_dir);
#ifndef __PAGETABLE_PMD_FOLDED
pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
#endif
pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994 - 2000 Ralf Baechle
	7	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
	8	* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
	9	* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
	10	*/
b868868a	11	#include <linux/bug.h>
1da177e4 LT	12	#include <linux/init.h>
	13	#include <linux/module.h>
	14	#include <linux/signal.h>
	15	#include <linux/sched.h>
631330f5	16	#include <linux/smp.h>
1da177e4 LT	17	#include <linux/kernel.h>
	18	#include <linux/errno.h>
	19	#include <linux/string.h>
	20	#include <linux/types.h>
	21	#include <linux/pagemap.h>
	22	#include <linux/ptrace.h>
	23	#include <linux/mman.h>
	24	#include <linux/mm.h>
	25	#include <linux/bootmem.h>
	26	#include <linux/highmem.h>
	27	#include <linux/swap.h>
3d503753	28	#include <linux/proc_fs.h>
22a9835c	29	#include <linux/pfn.h>
0f334a3e	30	#include <linux/hardirq.h>
5a0e3ad6	31	#include <linux/gfp.h>
2f96b8c1	32	#include <linux/kcore.h>
1da177e4	33
9975e77d	34	#include <asm/asm-offsets.h>
1da177e4 LT	35	#include <asm/bootinfo.h>
	36	#include <asm/cachectl.h>
	37	#include <asm/cpu.h>
	38	#include <asm/dma.h>
f8829cae	39	#include <asm/kmap_types.h>
1da177e4 LT	40	#include <asm/mmu_context.h>
	41	#include <asm/sections.h>
	42	#include <asm/pgtable.h>
	43	#include <asm/pgalloc.h>
	44	#include <asm/tlb.h>
f8829cae RB	45	#include <asm/fixmap.h>
	46
	47	/* Atomicity and interruptability */
	48	#ifdef CONFIG_MIPS_MT_SMTC
	49
	50	#include <asm/mipsmtregs.h>
	51
	52	#define ENTER_CRITICAL(flags) \
	53	{ \
	54	unsigned int mvpflags; \
	55	local_irq_save(flags);\
	56	mvpflags = dvpe()
	57	#define EXIT_CRITICAL(flags) \
	58	evpe(mvpflags); \
	59	local_irq_restore(flags); \
	60	}
	61	#else
	62
	63	#define ENTER_CRITICAL(flags) local_irq_save(flags)
	64	#define EXIT_CRITICAL(flags) local_irq_restore(flags)
	65
	66	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4	67
1da177e4 LT	68	/*
1da177e4 LT	69	* We have up to 8 empty zeroed pages so we can map one of the right colour
70342287	70	* when needed. This is necessary only on R4000 / R4400 SC and MC versions
1da177e4 LT	71	* where we have to avoid VCED / VECI exceptions for good performance at
	72	* any price. Since page is never written to after the initialization we
	73	* don't have to care about aliases on other CPUs.
	74	*/
	75	unsigned long empty_zero_page, zero_page_mask;
497d2adc	76	EXPORT_SYMBOL_GPL(empty_zero_page);
1da177e4 LT	77
	78	/*
	79	* Not static inline because used by IP27 special magic initialization code
	80	*/
31605922	81	void setup_zero_pages(void)
1da177e4	82	{
31605922	83	unsigned int order, i;
1da177e4 LT	84	struct page *page;
	85
	86	if (cpu_has_vce)
	87	order = 3;
	88	else
	89	order = 0;
	90
	91	empty_zero_page = __get_free_pages(GFP_KERNEL \| __GFP_ZERO, order);
	92	if (!empty_zero_page)
	93	panic("Oh boy, that early out of memory?");
	94
99e3b942	95	page = virt_to_page((void *)empty_zero_page);
8dfcc9ba	96	split_page(page, order);
31605922 JL	97	for (i = 0; i < (1 << order); i++, page++)
31605922 JL	98	mark_page_reserved(page);
1da177e4	99
31605922	100	zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK;
1da177e4 LT	101	}
1da177e4 LT	102
f8829cae RB	103	#ifdef CONFIG_MIPS_MT_SMTC
	104	static pte_t *kmap_coherent_pte;
	105	static void __init kmap_coherent_init(void)
	106	{
	107	unsigned long vaddr;
	108
	109	/* cache the first coherent kmap pte */
	110	vaddr = __fix_to_virt(FIX_CMAP_BEGIN);
	111	kmap_coherent_pte = kmap_get_fixmap_pte(vaddr);
	112	}
	113	#else
	114	static inline void kmap_coherent_init(void) {}
	115	#endif
	116
7575a49f	117	void kmap_coherent(struct page page, unsigned long addr)
f8829cae RB	118	{
	119	enum fixed_addresses idx;
	120	unsigned long vaddr, flags, entrylo;
	121	unsigned long old_ctx;
	122	pte_t pte;
	123	int tlbidx;
	124
b868868a RB	125	BUG_ON(Page_dcache_dirty(page));
b868868a RB	126
f8829cae RB	127	inc_preempt_count();
	128	idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
	129	#ifdef CONFIG_MIPS_MT_SMTC
0f334a3e KC	130	idx += FIX_N_COLOURS * smp_processor_id() +
	131	(in_interrupt() ? (FIX_N_COLOURS * NR_CPUS) : 0);
	132	#else
	133	idx += in_interrupt() ? FIX_N_COLOURS : 0;
f8829cae RB	134	#endif
	135	vaddr = __fix_to_virt(FIX_CMAP_END - idx);
	136	pte = mk_pte(page, PAGE_KERNEL);
962f480e	137	#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
f8829cae RB	138	entrylo = pte.pte_high;
f8829cae RB	139	#else
6dd9344c	140	entrylo = pte_to_entrylo(pte_val(pte));
f8829cae RB	141	#endif
	142
	143	ENTER_CRITICAL(flags);
	144	old_ctx = read_c0_entryhi();
	145	write_c0_entryhi(vaddr & (PAGE_MASK << 1));
	146	write_c0_entrylo0(entrylo);
	147	write_c0_entrylo1(entrylo);
	148	#ifdef CONFIG_MIPS_MT_SMTC
	149	set_pte(kmap_coherent_pte - (FIX_CMAP_END - idx), pte);
	150	/* preload TLB instead of local_flush_tlb_one() */
	151	mtc0_tlbw_hazard();
	152	tlb_probe();
	153	tlb_probe_hazard();
	154	tlbidx = read_c0_index();
	155	mtc0_tlbw_hazard();
	156	if (tlbidx < 0)
	157	tlb_write_random();
	158	else
	159	tlb_write_indexed();
	160	#else
	161	tlbidx = read_c0_wired();
	162	write_c0_wired(tlbidx + 1);
	163	write_c0_index(tlbidx);
	164	mtc0_tlbw_hazard();
	165	tlb_write_indexed();
	166	#endif
	167	tlbw_use_hazard();
	168	write_c0_entryhi(old_ctx);
	169	EXIT_CRITICAL(flags);
	170
	171	return (void*) vaddr;
	172	}
	173
	174	#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
	175
eacb9d61	176	void kunmap_coherent(void)
f8829cae RB	177	{
	178	#ifndef CONFIG_MIPS_MT_SMTC
	179	unsigned int wired;
	180	unsigned long flags, old_ctx;
	181
	182	ENTER_CRITICAL(flags);
	183	old_ctx = read_c0_entryhi();
	184	wired = read_c0_wired() - 1;
	185	write_c0_wired(wired);
	186	write_c0_index(wired);
	187	write_c0_entryhi(UNIQUE_ENTRYHI(wired));
	188	write_c0_entrylo0(0);
	189	write_c0_entrylo1(0);
	190	mtc0_tlbw_hazard();
	191	tlb_write_indexed();
	192	tlbw_use_hazard();
	193	write_c0_entryhi(old_ctx);
	194	EXIT_CRITICAL(flags);
	195	#endif
	196	dec_preempt_count();
	197	preempt_check_resched();
	198	}
	199
bcd02280 AN	200	void copy_user_highpage(struct page to, struct page from,
	201	unsigned long vaddr, struct vm_area_struct *vma)
	202	{
	203	void vfrom, vto;
	204
9c02048f	205	vto = kmap_atomic(to);
9a74b3eb RB	206	if (cpu_has_dc_aliases &&
9a74b3eb RB	207	page_mapped(from) && !Page_dcache_dirty(from)) {
bcd02280 AN	208	vfrom = kmap_coherent(from, vaddr);
bcd02280 AN	209	copy_page(vto, vfrom);
eacb9d61	210	kunmap_coherent();
bcd02280	211	} else {
9c02048f	212	vfrom = kmap_atomic(from);
bcd02280	213	copy_page(vto, vfrom);
9c02048f	214	kunmap_atomic(vfrom);
bcd02280	215	}
39b8d525	216	if ((!cpu_has_ic_fills_f_dc) \|\|
bcd02280 AN	217	pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
bcd02280 AN	218	flush_data_cache_page((unsigned long)vto);
9c02048f	219	kunmap_atomic(vto);
bcd02280 AN	220	/* Make sure this page is cleared on other CPU's too before using it */
	221	smp_wmb();
	222	}
	223
f8829cae RB	224	void copy_to_user_page(struct vm_area_struct *vma,
	225	struct page page, unsigned long vaddr, void dst, const void *src,
	226	unsigned long len)
	227	{
9a74b3eb RB	228	if (cpu_has_dc_aliases &&
9a74b3eb RB	229	page_mapped(page) && !Page_dcache_dirty(page)) {
f8829cae RB	230	void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
f8829cae RB	231	memcpy(vto, src, len);
eacb9d61	232	kunmap_coherent();
985c30ef	233	} else {
f8829cae	234	memcpy(dst, src, len);
985c30ef RB	235	if (cpu_has_dc_aliases)
	236	SetPageDcacheDirty(page);
	237	}
f8829cae RB	238	if ((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc)
	239	flush_cache_page(vma, vaddr, page_to_pfn(page));
	240	}
	241
f8829cae RB	242	void copy_from_user_page(struct vm_area_struct *vma,
	243	struct page page, unsigned long vaddr, void dst, const void *src,
	244	unsigned long len)
	245	{
9a74b3eb RB	246	if (cpu_has_dc_aliases &&
9a74b3eb RB	247	page_mapped(page) && !Page_dcache_dirty(page)) {
985c30ef	248	void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
f8829cae	249	memcpy(dst, vfrom, len);
eacb9d61	250	kunmap_coherent();
985c30ef	251	} else {
f8829cae	252	memcpy(dst, src, len);
985c30ef RB	253	if (cpu_has_dc_aliases)
	254	SetPageDcacheDirty(page);
	255	}
f8829cae RB	256	}
f8829cae RB	257
84fd089a	258	void __init fixrange_init(unsigned long start, unsigned long end,
1da177e4 LT	259	pgd_t *pgd_base)
1da177e4 LT	260	{
f8829cae	261	#if defined(CONFIG_HIGHMEM) \|\| defined(CONFIG_MIPS_MT_SMTC)
1da177e4	262	pgd_t *pgd;
c6e8b587	263	pud_t *pud;
1da177e4 LT	264	pmd_t *pmd;
1da177e4 LT	265	pte_t *pte;
c6e8b587	266	int i, j, k;
1da177e4 LT	267	unsigned long vaddr;
	268
	269	vaddr = start;
	270	i = __pgd_offset(vaddr);
c6e8b587 RB	271	j = __pud_offset(vaddr);
c6e8b587 RB	272	k = __pmd_offset(vaddr);
1da177e4 LT	273	pgd = pgd_base + i;
1da177e4 LT	274
464fd83e	275	for ( ; (i < PTRS_PER_PGD) && (vaddr < end); pgd++, i++) {
c6e8b587	276	pud = (pud_t *)pgd;
464fd83e	277	for ( ; (j < PTRS_PER_PUD) && (vaddr < end); pud++, j++) {
c6e8b587	278	pmd = (pmd_t *)pud;
464fd83e	279	for (; (k < PTRS_PER_PMD) && (vaddr < end); pmd++, k++) {
c6e8b587 RB	280	if (pmd_none(*pmd)) {
c6e8b587 RB	281	pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
f8829cae	282	set_pmd(pmd, __pmd((unsigned long)pte));
b72b7092	283	BUG_ON(pte != pte_offset_kernel(pmd, 0));
c6e8b587 RB	284	}
c6e8b587 RB	285	vaddr += PMD_SIZE;
1da177e4	286	}
c6e8b587	287	k = 0;
1da177e4 LT	288	}
	289	j = 0;
	290	}
f8829cae	291	#endif
1da177e4	292	}
1da177e4	293
b4819b59	294	#ifndef CONFIG_NEED_MULTIPLE_NODES
61ef2489	295	int page_is_ram(unsigned long pagenr)
565200a1 AN	296	{
	297	int i;
	298
	299	for (i = 0; i < boot_mem_map.nr_map; i++) {
	300	unsigned long addr, end;
	301
43064c0c DD	302	switch (boot_mem_map.map[i].type) {
	303	case BOOT_MEM_RAM:
	304	case BOOT_MEM_INIT_RAM:
	305	break;
	306	default:
565200a1 AN	307	/* not usable memory */
565200a1 AN	308	continue;
43064c0c	309	}
565200a1 AN	310
	311	addr = PFN_UP(boot_mem_map.map[i].addr);
	312	end = PFN_DOWN(boot_mem_map.map[i].addr +
	313	boot_mem_map.map[i].size);
	314
	315	if (pagenr >= addr && pagenr < end)
	316	return 1;
	317	}
	318
	319	return 0;
	320	}
	321
1da177e4 LT	322	void __init paging_init(void)
1da177e4 LT	323	{
cce335ae	324	unsigned long max_zone_pfns[MAX_NR_ZONES];
d3ce0e98	325	unsigned long lastpfn __maybe_unused;
1da177e4 LT	326
	327	pagetable_init();
	328
	329	#ifdef CONFIG_HIGHMEM
	330	kmap_init();
	331	#endif
f8829cae	332	kmap_coherent_init();
1da177e4	333
05502339	334	#ifdef CONFIG_ZONE_DMA
cce335ae	335	max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
1da177e4	336	#endif
cce335ae RB	337	#ifdef CONFIG_ZONE_DMA32
	338	max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
	339	#endif
	340	max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
	341	lastpfn = max_low_pfn;
1da177e4	342	#ifdef CONFIG_HIGHMEM
cce335ae RB	343	max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
cce335ae RB	344	lastpfn = highend_pfn;
cbb8fc07	345
cce335ae	346	if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
cbb8fc07	347	printk(KERN_WARNING "This processor doesn't support highmem."
cce335ae RB	348	" %ldk highmem ignored\n",
	349	(highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
	350	max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
	351	lastpfn = max_low_pfn;
cbb8fc07	352	}
1da177e4 LT	353	#endif
1da177e4 LT	354
cce335ae	355	free_area_init_nodes(max_zone_pfns);
1da177e4 LT	356	}
1da177e4 LT	357
3d503753 DJ	358	#ifdef CONFIG_64BIT
	359	static struct kcore_list kcore_kseg0;
	360	#endif
	361
1132137e	362	static inline void mem_init_free_highmem(void)
1da177e4	363	{
1132137e JL	364	#ifdef CONFIG_HIGHMEM
1132137e JL	365	unsigned long tmp;
1da177e4	366
1132137e JL	367	for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
	368	struct page *page = pfn_to_page(tmp);
	369
	370	if (!page_is_ram(tmp))
	371	SetPageReserved(page);
	372	else
	373	free_highmem_page(page);
	374	}
	375	#endif
	376	}
	377
	378	void __init mem_init(void)
	379	{
1da177e4 LT	380	#ifdef CONFIG_HIGHMEM
	381	#ifdef CONFIG_DISCONTIGMEM
	382	#error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet"
	383	#endif
b6da0ffb	384	max_mapnr = highend_pfn ? highend_pfn : max_low_pfn;
1da177e4	385	#else
565200a1	386	max_mapnr = max_low_pfn;
1da177e4 LT	387	#endif
	388	high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
	389
0c988534	390	free_all_bootmem();
31605922	391	setup_zero_pages(); /* Setup zeroed pages. */
1132137e JL	392	mem_init_free_highmem();
1132137e JL	393	mem_init_print_info(NULL);
1da177e4	394
3d503753 DJ	395	#ifdef CONFIG_64BIT
	396	if ((unsigned long) &_text > (unsigned long) CKSEG0)
	397	/* The -4 is a hack so that user tools don't have to handle
	398	the overflow. */
c30bb2a2 KH	399	kclist_add(&kcore_kseg0, (void *) CKSEG0,
c30bb2a2 KH	400	0x80000000 - 4, KCORE_TEXT);
3d503753	401	#endif
1da177e4	402	}
b4819b59	403	#endif /* !CONFIG_NEED_MULTIPLE_NODES */
1da177e4	404
c44e8d5e	405	void free_init_pages(const char *what, unsigned long begin, unsigned long end)
6fd11a21	406	{
acd86b86	407	unsigned long pfn;
6fd11a21	408
acd86b86 FBH	409	for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
	410	struct page *page = pfn_to_page(pfn);
	411	void *addr = phys_to_virt(PFN_PHYS(pfn));
	412
acd86b86	413	memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
31605922	414	free_reserved_page(page);
6fd11a21 RB	415	}
	416	printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
	417	}
	418
1da177e4 LT	419	#ifdef CONFIG_BLK_DEV_INITRD
	420	void free_initrd_mem(unsigned long start, unsigned long end)
	421	{
11199692 JL	422	free_reserved_area((void )start, (void )end, POISON_FREE_INITMEM,
11199692 JL	423	"initrd");
1da177e4 LT	424	}
	425	#endif
	426
fb4bb133	427	void __init_refok free_initmem(void)
1da177e4	428	{
c44e8d5e	429	prom_free_prom_memory();
31605922	430	free_initmem_default(POISON_FREE_INITMEM);
1da177e4	431	}
69a6c312	432
82622284	433	#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
69a6c312	434	unsigned long pgd_current[NR_CPUS];
82622284	435	#endif
9975e77d RB	436
	437	/*
	438	* gcc 3.3 and older have trouble determining that PTRS_PER_PGD and PGD_ORDER
	439	* are constants. So we use the variants from asm-offset.h until that gcc
	440	* will officially be retired.
485172b3 DD	441	*
	442	* Align swapper_pg_dir in to 64K, allows its address to be loaded
	443	* with a single LUI instruction in the TLB handlers. If we used
	444	* __aligned(64K), its size would get rounded up to the alignment
	445	* size, and waste space. So we place it in its own section and align
	446	* it in the linker script.
9975e77d	447	*/
485172b3	448	pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(.bss..swapper_pg_dir);
325f8a0a	449	#ifndef __PAGETABLE_PMD_FOLDED
485172b3	450	pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
69a6c312	451	#endif
485172b3	452	pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;