[mirror_ubuntu-artful-kernel.git] / arch / mips / mm / sc-mips.c

/*
 * Copyright (C) 2006 Chris Dearman (chris@mips.com),
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>

#include <asm/cpu-type.h>
#include <asm/mipsregs.h>
#include <asm/bcache.h>
#include <asm/cacheops.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mmu_context.h>
#include <asm/r4kcache.h>
#include <asm/mips-cm.h>

/*
 * MIPS32/MIPS64 L2 cache handling
 */

/*
 * Writeback and invalidate the secondary cache before DMA.
 */
static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
{
	blast_scache_range(addr, addr + size);
}

/*
 * Invalidate the secondary cache before DMA.
 */
static void mips_sc_inv(unsigned long addr, unsigned long size)
{
	unsigned long lsize = cpu_scache_line_size();
	unsigned long almask = ~(lsize - 1);

	cache_op(Hit_Writeback_Inv_SD, addr & almask);
	cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
	blast_inv_scache_range(addr, addr + size);
}

static void mips_sc_enable(void)
{
	/* L2 cache is permanently enabled */
}

static void mips_sc_disable(void)
{
	/* L2 cache is permanently enabled */
}

static void mips_sc_prefetch_enable(void)
{
	unsigned long pftctl;

	if (mips_cm_revision() < CM_REV_CM2_5)
		return;

	/*
	 * If there is one or more L2 prefetch unit present then enable
	 * prefetching for both code & data, for all ports.
	 */
	pftctl = read_gcr_l2_pft_control();
	if (pftctl & CM_GCR_L2_PFT_CONTROL_NPFT_MSK) {
		pftctl &= ~CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK;
		pftctl |= PAGE_MASK & CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK;
		pftctl |= CM_GCR_L2_PFT_CONTROL_PFTEN_MSK;
		write_gcr_l2_pft_control(pftctl);

		pftctl = read_gcr_l2_pft_control_b();
		pftctl |= CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK;
		pftctl |= CM_GCR_L2_PFT_CONTROL_B_CEN_MSK;
		write_gcr_l2_pft_control_b(pftctl);
	}
}

static void mips_sc_prefetch_disable(void)
{
	unsigned long pftctl;

	if (mips_cm_revision() < CM_REV_CM2_5)
		return;

	pftctl = read_gcr_l2_pft_control();
	pftctl &= ~CM_GCR_L2_PFT_CONTROL_PFTEN_MSK;
	write_gcr_l2_pft_control(pftctl);

	pftctl = read_gcr_l2_pft_control_b();
	pftctl &= ~CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK;
	pftctl &= ~CM_GCR_L2_PFT_CONTROL_B_CEN_MSK;
	write_gcr_l2_pft_control_b(pftctl);
}

static bool mips_sc_prefetch_is_enabled(void)
{
	unsigned long pftctl;

	if (mips_cm_revision() < CM_REV_CM2_5)
		return false;

	pftctl = read_gcr_l2_pft_control();
	if (!(pftctl & CM_GCR_L2_PFT_CONTROL_NPFT_MSK))
		return false;
	return !!(pftctl & CM_GCR_L2_PFT_CONTROL_PFTEN_MSK);
}

static struct bcache_ops mips_sc_ops = {
	.bc_enable = mips_sc_enable,
	.bc_disable = mips_sc_disable,
	.bc_wback_inv = mips_sc_wback_inv,
	.bc_inv = mips_sc_inv,
	.bc_prefetch_enable = mips_sc_prefetch_enable,
	.bc_prefetch_disable = mips_sc_prefetch_disable,
	.bc_prefetch_is_enabled = mips_sc_prefetch_is_enabled,
};

/*
 * Check if the L2 cache controller is activated on a particular platform.
 * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
 * cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
 * cache being disabled.  However there is no guarantee for this to be
 * true on all platforms.  In an act of stupidity the spec defined bits
 * 12..15 as implementation defined so below function will eventually have
 * to be replaced by a platform specific probe.
 */
static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
{
	unsigned int config2 = read_c0_config2();
	unsigned int tmp;

	/* Check the bypass bit (L2B) */
	switch (current_cpu_type()) {
	case CPU_34K:
	case CPU_74K:
	case CPU_1004K:
	case CPU_1074K:
	case CPU_INTERAPTIV:
	case CPU_PROAPTIV:
	case CPU_P5600:
	case CPU_BMIPS5000:
	case CPU_QEMU_GENERIC:
	case CPU_P6600:
		if (config2 & (1 << 12))
			return 0;
	}

	tmp = (config2 >> 4) & 0x0f;
	if (0 < tmp && tmp <= 7)
		c->scache.linesz = 2 << tmp;
	else
		return 0;
	return 1;
}

static int __init mips_sc_probe_cm3(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;
	unsigned long cfg = read_gcr_l2_config();
	unsigned long sets, line_sz, assoc;

	if (cfg & CM_GCR_L2_CONFIG_BYPASS_MSK)
		return 0;

	sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE_MSK;
	sets >>= CM_GCR_L2_CONFIG_SET_SIZE_SHF;
	if (sets)
		c->scache.sets = 64 << sets;

	line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
	line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
	if (line_sz)
		c->scache.linesz = 2 << line_sz;

	assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK;
	assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF;
	c->scache.ways = assoc + 1;
	c->scache.waysize = c->scache.sets * c->scache.linesz;
	c->scache.waybit = __ffs(c->scache.waysize);

	if (c->scache.linesz) {
		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
		c->options |= MIPS_CPU_INCLUSIVE_CACHES;
		return 1;
	}

	return 0;
}

static inline int __init mips_sc_probe(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;
	unsigned int config1, config2;
	unsigned int tmp;

	/* Mark as not present until probe completed */
	c->scache.flags |= MIPS_CACHE_NOT_PRESENT;

	if (mips_cm_revision() >= CM_REV_CM3)
		return mips_sc_probe_cm3();

	/* Ignore anything but MIPSxx processors */
	if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
			      MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
			      MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)))
		return 0;

	/* Does this MIPS32/MIPS64 CPU have a config2 register? */
	config1 = read_c0_config1();
	if (!(config1 & MIPS_CONF_M))
		return 0;

	config2 = read_c0_config2();

	if (!mips_sc_is_activated(c))
		return 0;

	tmp = (config2 >> 8) & 0x0f;
	if (tmp <= 7)
		c->scache.sets = 64 << tmp;
	else
		return 0;

	tmp = (config2 >> 0) & 0x0f;
	if (tmp <= 7)
		c->scache.ways = tmp + 1;
	else
		return 0;

	c->scache.waysize = c->scache.sets * c->scache.linesz;
	c->scache.waybit = __ffs(c->scache.waysize);

	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;

	return 1;
}

int mips_sc_init(void)
{
	int found = mips_sc_probe();
	if (found) {
		mips_sc_enable();
		mips_sc_prefetch_enable();
		bcops = &mips_sc_ops;
	}
	return found;
}
Commit	Line	Data
9318c51a CD	1	/*
	2	* Copyright (C) 2006 Chris Dearman (chris@mips.com),
	3	*/
	4	#include <linux/init.h>
	5	#include <linux/kernel.h>
	6	#include <linux/sched.h>
	7	#include <linux/mm.h>
	8
69f24d17	9	#include <asm/cpu-type.h>
9318c51a CD	10	#include <asm/mipsregs.h>
	11	#include <asm/bcache.h>
	12	#include <asm/cacheops.h>
	13	#include <asm/page.h>
	14	#include <asm/pgtable.h>
9318c51a CD	15	#include <asm/mmu_context.h>
9318c51a CD	16	#include <asm/r4kcache.h>
7d53e9c4	17	#include <asm/mips-cm.h>
9318c51a CD	18
	19	/*
	20	* MIPS32/MIPS64 L2 cache handling
	21	*/
	22
	23	/*
	24	* Writeback and invalidate the secondary cache before DMA.
	25	*/
	26	static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
	27	{
a2c2bc4b	28	blast_scache_range(addr, addr + size);
9318c51a CD	29	}
	30
	31	/*
	32	* Invalidate the secondary cache before DMA.
	33	*/
	34	static void mips_sc_inv(unsigned long addr, unsigned long size)
	35	{
96983ffe KC	36	unsigned long lsize = cpu_scache_line_size();
	37	unsigned long almask = ~(lsize - 1);
	38
	39	cache_op(Hit_Writeback_Inv_SD, addr & almask);
	40	cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
a2c2bc4b	41	blast_inv_scache_range(addr, addr + size);
9318c51a CD	42	}
	43
	44	static void mips_sc_enable(void)
	45	{
	46	/* L2 cache is permanently enabled */
	47	}
	48
	49	static void mips_sc_disable(void)
	50	{
	51	/* L2 cache is permanently enabled */
	52	}
	53
4d035516 PB	54	static void mips_sc_prefetch_enable(void)
	55	{
	56	unsigned long pftctl;
	57
	58	if (mips_cm_revision() < CM_REV_CM2_5)
	59	return;
	60
	61	/*
	62	* If there is one or more L2 prefetch unit present then enable
	63	* prefetching for both code & data, for all ports.
	64	*/
	65	pftctl = read_gcr_l2_pft_control();
	66	if (pftctl & CM_GCR_L2_PFT_CONTROL_NPFT_MSK) {
	67	pftctl &= ~CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK;
	68	pftctl \|= PAGE_MASK & CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK;
	69	pftctl \|= CM_GCR_L2_PFT_CONTROL_PFTEN_MSK;
	70	write_gcr_l2_pft_control(pftctl);
	71
	72	pftctl = read_gcr_l2_pft_control_b();
	73	pftctl \|= CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK;
	74	pftctl \|= CM_GCR_L2_PFT_CONTROL_B_CEN_MSK;
	75	write_gcr_l2_pft_control_b(pftctl);
	76	}
	77	}
	78
	79	static void mips_sc_prefetch_disable(void)
	80	{
	81	unsigned long pftctl;
	82
	83	if (mips_cm_revision() < CM_REV_CM2_5)
	84	return;
	85
	86	pftctl = read_gcr_l2_pft_control();
	87	pftctl &= ~CM_GCR_L2_PFT_CONTROL_PFTEN_MSK;
	88	write_gcr_l2_pft_control(pftctl);
	89
	90	pftctl = read_gcr_l2_pft_control_b();
	91	pftctl &= ~CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK;
	92	pftctl &= ~CM_GCR_L2_PFT_CONTROL_B_CEN_MSK;
	93	write_gcr_l2_pft_control_b(pftctl);
	94	}
	95
	96	static bool mips_sc_prefetch_is_enabled(void)
	97	{
	98	unsigned long pftctl;
	99
	100	if (mips_cm_revision() < CM_REV_CM2_5)
	101	return false;
	102
	103	pftctl = read_gcr_l2_pft_control();
	104	if (!(pftctl & CM_GCR_L2_PFT_CONTROL_NPFT_MSK))
	105	return false;
	106	return !!(pftctl & CM_GCR_L2_PFT_CONTROL_PFTEN_MSK);
	107	}
	108
9318c51a CD	109	static struct bcache_ops mips_sc_ops = {
	110	.bc_enable = mips_sc_enable,
	111	.bc_disable = mips_sc_disable,
	112	.bc_wback_inv = mips_sc_wback_inv,
4d035516 PB	113	.bc_inv = mips_sc_inv,
	114	.bc_prefetch_enable = mips_sc_prefetch_enable,
	115	.bc_prefetch_disable = mips_sc_prefetch_disable,
	116	.bc_prefetch_is_enabled = mips_sc_prefetch_is_enabled,
9318c51a CD	117	};
9318c51a CD	118
ea31a6b2 KC	119	/*
	120	* Check if the L2 cache controller is activated on a particular platform.
	121	* MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
	122	* cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
	123	* cache being disabled. However there is no guarantee for this to be
	124	* true on all platforms. In an act of stupidity the spec defined bits
	125	* 12..15 as implementation defined so below function will eventually have
	126	* to be replaced by a platform specific probe.
	127	*/
	128	static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
	129	{
081d835f KC	130	unsigned int config2 = read_c0_config2();
	131	unsigned int tmp;
	132
ea31a6b2	133	/* Check the bypass bit (L2B) */
69f24d17	134	switch (current_cpu_type()) {
ea31a6b2 KC	135	case CPU_34K:
	136	case CPU_74K:
	137	case CPU_1004K:
442e14a2	138	case CPU_1074K:
26ab96df	139	case CPU_INTERAPTIV:
708ac4b8	140	case CPU_PROAPTIV:
aced4cbd	141	case CPU_P5600:
ea31a6b2	142	case CPU_BMIPS5000:
4695089f	143	case CPU_QEMU_GENERIC:
1091bfa2	144	case CPU_P6600:
ea31a6b2 KC	145	if (config2 & (1 << 12))
	146	return 0;
	147	}
	148
	149	tmp = (config2 >> 4) & 0x0f;
	150	if (0 < tmp && tmp <= 7)
	151	c->scache.linesz = 2 << tmp;
	152	else
	153	return 0;
081d835f	154	return 1;
ea31a6b2 KC	155	}
ea31a6b2 KC	156
7d53e9c4 PB	157	static int __init mips_sc_probe_cm3(void)
	158	{
	159	struct cpuinfo_mips *c = &current_cpu_data;
	160	unsigned long cfg = read_gcr_l2_config();
	161	unsigned long sets, line_sz, assoc;
	162
	163	if (cfg & CM_GCR_L2_CONFIG_BYPASS_MSK)
	164	return 0;
	165
	166	sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE_MSK;
	167	sets >>= CM_GCR_L2_CONFIG_SET_SIZE_SHF;
56fa81fc GR	168	if (sets)
56fa81fc GR	169	c->scache.sets = 64 << sets;
7d53e9c4 PB	170
	171	line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
	172	line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
56fa81fc GR	173	if (line_sz)
56fa81fc GR	174	c->scache.linesz = 2 << line_sz;
7d53e9c4 PB	175
	176	assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK;
	177	assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF;
	178	c->scache.ways = assoc + 1;
	179	c->scache.waysize = c->scache.sets * c->scache.linesz;
	180	c->scache.waybit = __ffs(c->scache.waysize);
	181
56fa81fc GR	182	if (c->scache.linesz) {
56fa81fc GR	183	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
48ed33c1	184	c->options \|= MIPS_CPU_INCLUSIVE_CACHES;
56fa81fc GR	185	return 1;
56fa81fc GR	186	}
7d53e9c4	187
56fa81fc	188	return 0;
7d53e9c4 PB	189	}
7d53e9c4 PB	190
9318c51a CD	191	static inline int __init mips_sc_probe(void)
	192	{
	193	struct cpuinfo_mips *c = &current_cpu_data;
	194	unsigned int config1, config2;
	195	unsigned int tmp;
	196
	197	/* Mark as not present until probe completed */
	198	c->scache.flags \|= MIPS_CACHE_NOT_PRESENT;
	199
7d53e9c4 PB	200	if (mips_cm_revision() >= CM_REV_CM3)
	201	return mips_sc_probe_cm3();
	202
9318c51a	203	/* Ignore anything but MIPSxx processors */
adb37892	204	if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 \| MIPS_CPU_ISA_M32R2 \|
b5ad2c21 MC	205	MIPS_CPU_ISA_M32R6 \| MIPS_CPU_ISA_M64R1 \|
b5ad2c21 MC	206	MIPS_CPU_ISA_M64R2 \| MIPS_CPU_ISA_M64R6)))
9318c51a CD	207	return 0;
	208
	209	/* Does this MIPS32/MIPS64 CPU have a config2 register? */
	210	config1 = read_c0_config1();
	211	if (!(config1 & MIPS_CONF_M))
	212	return 0;
	213
	214	config2 = read_c0_config2();
ea31a6b2 KC	215
ea31a6b2 KC	216	if (!mips_sc_is_activated(c))
9318c51a CD	217	return 0;
	218
	219	tmp = (config2 >> 8) & 0x0f;
05513992	220	if (tmp <= 7)
9318c51a CD	221	c->scache.sets = 64 << tmp;
	222	else
	223	return 0;
	224
	225	tmp = (config2 >> 0) & 0x0f;
05513992	226	if (tmp <= 7)
9318c51a CD	227	c->scache.ways = tmp + 1;
	228	else
	229	return 0;
	230
	231	c->scache.waysize = c->scache.sets * c->scache.linesz;
a2c2bc4b	232	c->scache.waybit = __ffs(c->scache.waysize);
9318c51a CD	233
	234	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
	235
	236	return 1;
	237	}
	238
078a55fc	239	int mips_sc_init(void)
9318c51a	240	{
49a89efb	241	int found = mips_sc_probe();
9318c51a CD	242	if (found) {
9318c51a CD	243	mips_sc_enable();
4d035516	244	mips_sc_prefetch_enable();
9318c51a CD	245	bcops = &mips_sc_ops;
	246	}
	247	return found;
	248	}