]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
79add627 | 6 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
7 | * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org |
8 | * Carsten Langgaard, carstenl@mips.com | |
9 | * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. | |
10 | */ | |
eaa38d63 | 11 | #include <linux/cpu_pm.h> |
1da177e4 LT |
12 | #include <linux/init.h> |
13 | #include <linux/sched.h> | |
631330f5 | 14 | #include <linux/smp.h> |
1da177e4 | 15 | #include <linux/mm.h> |
fd062c84 | 16 | #include <linux/hugetlb.h> |
d9ba5778 | 17 | #include <linux/export.h> |
1da177e4 LT |
18 | |
19 | #include <asm/cpu.h> | |
69f24d17 | 20 | #include <asm/cpu-type.h> |
1da177e4 | 21 | #include <asm/bootinfo.h> |
091bc3a4 | 22 | #include <asm/hazards.h> |
1da177e4 | 23 | #include <asm/mmu_context.h> |
c01905ee | 24 | #include <asm/tlb.h> |
3d18c983 | 25 | #include <asm/tlbmisc.h> |
1da177e4 LT |
26 | |
27 | extern void build_tlb_refill_handler(void); | |
28 | ||
2a21c730 | 29 | /* |
06e4814e HC |
30 | * LOONGSON-2 has a 4 entry itlb which is a subset of jtlb, LOONGSON-3 has |
31 | * a 4 entry itlb and a 4 entry dtlb which are subsets of jtlb. Unfortunately, | |
32 | * itlb/dtlb are not totally transparent to software. | |
2a21c730 | 33 | */ |
06e4814e | 34 | static inline void flush_micro_tlb(void) |
14bd8c08 RB |
35 | { |
36 | switch (current_cpu_type()) { | |
268a2d60 | 37 | case CPU_LOONGSON2EF: |
06e4814e HC |
38 | write_c0_diag(LOONGSON_DIAG_ITLB); |
39 | break; | |
268a2d60 | 40 | case CPU_LOONGSON64: |
06e4814e | 41 | write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB); |
14bd8c08 RB |
42 | break; |
43 | default: | |
44 | break; | |
45 | } | |
46 | } | |
2a21c730 | 47 | |
06e4814e | 48 | static inline void flush_micro_tlb_vm(struct vm_area_struct *vma) |
14bd8c08 RB |
49 | { |
50 | if (vma->vm_flags & VM_EXEC) | |
06e4814e | 51 | flush_micro_tlb(); |
14bd8c08 | 52 | } |
2a21c730 | 53 | |
1da177e4 LT |
54 | void local_flush_tlb_all(void) |
55 | { | |
56 | unsigned long flags; | |
57 | unsigned long old_ctx; | |
75b5b5e0 | 58 | int entry, ftlbhighset; |
1da177e4 | 59 | |
b633648c | 60 | local_irq_save(flags); |
1da177e4 LT |
61 | /* Save old context and create impossible VPN2 value */ |
62 | old_ctx = read_c0_entryhi(); | |
f1014d1b | 63 | htw_stop(); |
1da177e4 LT |
64 | write_c0_entrylo0(0); |
65 | write_c0_entrylo1(0); | |
66 | ||
10313980 | 67 | entry = num_wired_entries(); |
1da177e4 | 68 | |
e710d666 MR |
69 | /* |
70 | * Blast 'em all away. | |
71 | * If there are any wired entries, fall back to iterating | |
72 | */ | |
73 | if (cpu_has_tlbinv && !entry) { | |
75b5b5e0 LY |
74 | if (current_cpu_data.tlbsizevtlb) { |
75 | write_c0_index(0); | |
76 | mtc0_tlbw_hazard(); | |
77 | tlbinvf(); /* invalidate VTLB */ | |
78 | } | |
79 | ftlbhighset = current_cpu_data.tlbsizevtlb + | |
80 | current_cpu_data.tlbsizeftlbsets; | |
81 | for (entry = current_cpu_data.tlbsizevtlb; | |
82 | entry < ftlbhighset; | |
83 | entry++) { | |
84 | write_c0_index(entry); | |
85 | mtc0_tlbw_hazard(); | |
86 | tlbinvf(); /* invalidate one FTLB set */ | |
87 | } | |
601cfa7b LY |
88 | } else { |
89 | while (entry < current_cpu_data.tlbsize) { | |
90 | /* Make sure all entries differ. */ | |
91 | write_c0_entryhi(UNIQUE_ENTRYHI(entry)); | |
92 | write_c0_index(entry); | |
93 | mtc0_tlbw_hazard(); | |
94 | tlb_write_indexed(); | |
95 | entry++; | |
96 | } | |
1da177e4 LT |
97 | } |
98 | tlbw_use_hazard(); | |
99 | write_c0_entryhi(old_ctx); | |
f1014d1b | 100 | htw_start(); |
06e4814e | 101 | flush_micro_tlb(); |
b633648c | 102 | local_irq_restore(flags); |
1da177e4 | 103 | } |
f2e3656d | 104 | EXPORT_SYMBOL(local_flush_tlb_all); |
1da177e4 | 105 | |
1da177e4 LT |
106 | void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, |
107 | unsigned long end) | |
108 | { | |
109 | struct mm_struct *mm = vma->vm_mm; | |
110 | int cpu = smp_processor_id(); | |
111 | ||
112 | if (cpu_context(cpu, mm) != 0) { | |
a5e696e5 | 113 | unsigned long size, flags; |
1da177e4 | 114 | |
b633648c | 115 | local_irq_save(flags); |
ac53c4fc DD |
116 | start = round_down(start, PAGE_SIZE << 1); |
117 | end = round_up(end, PAGE_SIZE << 1); | |
118 | size = (end - start) >> (PAGE_SHIFT + 1); | |
75b5b5e0 LY |
119 | if (size <= (current_cpu_data.tlbsizeftlbsets ? |
120 | current_cpu_data.tlbsize / 8 : | |
121 | current_cpu_data.tlbsize / 2)) { | |
3f649ab7 | 122 | unsigned long old_entryhi, old_mmid; |
1da177e4 LT |
123 | int newpid = cpu_asid(cpu, mm); |
124 | ||
c8790d65 PB |
125 | old_entryhi = read_c0_entryhi(); |
126 | if (cpu_has_mmid) { | |
127 | old_mmid = read_c0_memorymapid(); | |
128 | write_c0_memorymapid(newpid); | |
129 | } | |
130 | ||
f1014d1b | 131 | htw_stop(); |
1da177e4 LT |
132 | while (start < end) { |
133 | int idx; | |
134 | ||
c8790d65 PB |
135 | if (cpu_has_mmid) |
136 | write_c0_entryhi(start); | |
137 | else | |
138 | write_c0_entryhi(start | newpid); | |
ac53c4fc | 139 | start += (PAGE_SIZE << 1); |
1da177e4 LT |
140 | mtc0_tlbw_hazard(); |
141 | tlb_probe(); | |
432bef2a | 142 | tlb_probe_hazard(); |
1da177e4 LT |
143 | idx = read_c0_index(); |
144 | write_c0_entrylo0(0); | |
145 | write_c0_entrylo1(0); | |
146 | if (idx < 0) | |
147 | continue; | |
148 | /* Make sure all entries differ. */ | |
172546bf | 149 | write_c0_entryhi(UNIQUE_ENTRYHI(idx)); |
1da177e4 LT |
150 | mtc0_tlbw_hazard(); |
151 | tlb_write_indexed(); | |
152 | } | |
153 | tlbw_use_hazard(); | |
c8790d65 PB |
154 | write_c0_entryhi(old_entryhi); |
155 | if (cpu_has_mmid) | |
156 | write_c0_memorymapid(old_mmid); | |
f1014d1b | 157 | htw_start(); |
1da177e4 | 158 | } else { |
9a27324f | 159 | drop_mmu_context(mm); |
1da177e4 | 160 | } |
06e4814e | 161 | flush_micro_tlb(); |
b633648c | 162 | local_irq_restore(flags); |
1da177e4 LT |
163 | } |
164 | } | |
165 | ||
166 | void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
167 | { | |
a5e696e5 | 168 | unsigned long size, flags; |
1da177e4 | 169 | |
b633648c | 170 | local_irq_save(flags); |
1da177e4 LT |
171 | size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; |
172 | size = (size + 1) >> 1; | |
75b5b5e0 LY |
173 | if (size <= (current_cpu_data.tlbsizeftlbsets ? |
174 | current_cpu_data.tlbsize / 8 : | |
175 | current_cpu_data.tlbsize / 2)) { | |
1da177e4 LT |
176 | int pid = read_c0_entryhi(); |
177 | ||
178 | start &= (PAGE_MASK << 1); | |
179 | end += ((PAGE_SIZE << 1) - 1); | |
180 | end &= (PAGE_MASK << 1); | |
f1014d1b | 181 | htw_stop(); |
1da177e4 LT |
182 | |
183 | while (start < end) { | |
184 | int idx; | |
185 | ||
186 | write_c0_entryhi(start); | |
187 | start += (PAGE_SIZE << 1); | |
188 | mtc0_tlbw_hazard(); | |
189 | tlb_probe(); | |
432bef2a | 190 | tlb_probe_hazard(); |
1da177e4 LT |
191 | idx = read_c0_index(); |
192 | write_c0_entrylo0(0); | |
193 | write_c0_entrylo1(0); | |
194 | if (idx < 0) | |
195 | continue; | |
196 | /* Make sure all entries differ. */ | |
172546bf | 197 | write_c0_entryhi(UNIQUE_ENTRYHI(idx)); |
1da177e4 LT |
198 | mtc0_tlbw_hazard(); |
199 | tlb_write_indexed(); | |
200 | } | |
201 | tlbw_use_hazard(); | |
202 | write_c0_entryhi(pid); | |
f1014d1b | 203 | htw_start(); |
1da177e4 LT |
204 | } else { |
205 | local_flush_tlb_all(); | |
206 | } | |
06e4814e | 207 | flush_micro_tlb(); |
b633648c | 208 | local_irq_restore(flags); |
1da177e4 LT |
209 | } |
210 | ||
211 | void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
212 | { | |
213 | int cpu = smp_processor_id(); | |
214 | ||
215 | if (cpu_context(cpu, vma->vm_mm) != 0) { | |
3f649ab7 | 216 | unsigned long old_mmid; |
c8790d65 PB |
217 | unsigned long flags, old_entryhi; |
218 | int idx; | |
1da177e4 | 219 | |
1da177e4 | 220 | page &= (PAGE_MASK << 1); |
b633648c | 221 | local_irq_save(flags); |
c8790d65 | 222 | old_entryhi = read_c0_entryhi(); |
f1014d1b | 223 | htw_stop(); |
c8790d65 PB |
224 | if (cpu_has_mmid) { |
225 | old_mmid = read_c0_memorymapid(); | |
226 | write_c0_entryhi(page); | |
227 | write_c0_memorymapid(cpu_asid(cpu, vma->vm_mm)); | |
228 | } else { | |
229 | write_c0_entryhi(page | cpu_asid(cpu, vma->vm_mm)); | |
230 | } | |
1da177e4 LT |
231 | mtc0_tlbw_hazard(); |
232 | tlb_probe(); | |
432bef2a | 233 | tlb_probe_hazard(); |
1da177e4 LT |
234 | idx = read_c0_index(); |
235 | write_c0_entrylo0(0); | |
236 | write_c0_entrylo1(0); | |
237 | if (idx < 0) | |
238 | goto finish; | |
239 | /* Make sure all entries differ. */ | |
172546bf | 240 | write_c0_entryhi(UNIQUE_ENTRYHI(idx)); |
1da177e4 LT |
241 | mtc0_tlbw_hazard(); |
242 | tlb_write_indexed(); | |
243 | tlbw_use_hazard(); | |
244 | ||
245 | finish: | |
c8790d65 PB |
246 | write_c0_entryhi(old_entryhi); |
247 | if (cpu_has_mmid) | |
248 | write_c0_memorymapid(old_mmid); | |
f1014d1b | 249 | htw_start(); |
06e4814e | 250 | flush_micro_tlb_vm(vma); |
b633648c | 251 | local_irq_restore(flags); |
1da177e4 LT |
252 | } |
253 | } | |
254 | ||
255 | /* | |
256 | * This one is only used for pages with the global bit set so we don't care | |
257 | * much about the ASID. | |
258 | */ | |
259 | void local_flush_tlb_one(unsigned long page) | |
260 | { | |
261 | unsigned long flags; | |
262 | int oldpid, idx; | |
263 | ||
b633648c | 264 | local_irq_save(flags); |
1da177e4 | 265 | oldpid = read_c0_entryhi(); |
f1014d1b | 266 | htw_stop(); |
172546bf | 267 | page &= (PAGE_MASK << 1); |
1da177e4 LT |
268 | write_c0_entryhi(page); |
269 | mtc0_tlbw_hazard(); | |
270 | tlb_probe(); | |
432bef2a | 271 | tlb_probe_hazard(); |
1da177e4 LT |
272 | idx = read_c0_index(); |
273 | write_c0_entrylo0(0); | |
274 | write_c0_entrylo1(0); | |
275 | if (idx >= 0) { | |
276 | /* Make sure all entries differ. */ | |
172546bf | 277 | write_c0_entryhi(UNIQUE_ENTRYHI(idx)); |
1da177e4 LT |
278 | mtc0_tlbw_hazard(); |
279 | tlb_write_indexed(); | |
280 | tlbw_use_hazard(); | |
281 | } | |
282 | write_c0_entryhi(oldpid); | |
f1014d1b | 283 | htw_start(); |
06e4814e | 284 | flush_micro_tlb(); |
b633648c | 285 | local_irq_restore(flags); |
1da177e4 LT |
286 | } |
287 | ||
288 | /* | |
289 | * We will need multiple versions of update_mmu_cache(), one that just | |
290 | * updates the TLB with the new pte(s), and another which also checks | |
291 | * for the R4k "end of page" hardware bug and does the needy. | |
292 | */ | |
293 | void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) | |
294 | { | |
295 | unsigned long flags; | |
296 | pgd_t *pgdp; | |
2bee1b58 | 297 | p4d_t *p4dp; |
c6e8b587 | 298 | pud_t *pudp; |
1da177e4 LT |
299 | pmd_t *pmdp; |
300 | pte_t *ptep; | |
301 | int idx, pid; | |
302 | ||
303 | /* | |
304 | * Handle debugger faulting in for debugee. | |
305 | */ | |
306 | if (current->active_mm != vma->vm_mm) | |
307 | return; | |
308 | ||
b633648c | 309 | local_irq_save(flags); |
172546bf | 310 | |
6a8dff6a | 311 | htw_stop(); |
1da177e4 | 312 | address &= (PAGE_MASK << 1); |
c8790d65 PB |
313 | if (cpu_has_mmid) { |
314 | write_c0_entryhi(address); | |
315 | } else { | |
316 | pid = read_c0_entryhi() & cpu_asid_mask(¤t_cpu_data); | |
317 | write_c0_entryhi(address | pid); | |
318 | } | |
1da177e4 LT |
319 | pgdp = pgd_offset(vma->vm_mm, address); |
320 | mtc0_tlbw_hazard(); | |
321 | tlb_probe(); | |
432bef2a | 322 | tlb_probe_hazard(); |
2bee1b58 MR |
323 | p4dp = p4d_offset(pgdp, address); |
324 | pudp = pud_offset(p4dp, address); | |
c6e8b587 | 325 | pmdp = pmd_offset(pudp, address); |
1da177e4 | 326 | idx = read_c0_index(); |
aa1762f4 | 327 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
328 | /* this could be a huge page */ |
329 | if (pmd_huge(*pmdp)) { | |
330 | unsigned long lo; | |
331 | write_c0_pagemask(PM_HUGE_MASK); | |
332 | ptep = (pte_t *)pmdp; | |
6dd9344c | 333 | lo = pte_to_entrylo(pte_val(*ptep)); |
fd062c84 DD |
334 | write_c0_entrylo0(lo); |
335 | write_c0_entrylo1(lo + (HPAGE_SIZE >> 7)); | |
336 | ||
337 | mtc0_tlbw_hazard(); | |
338 | if (idx < 0) | |
339 | tlb_write_random(); | |
340 | else | |
341 | tlb_write_indexed(); | |
fb944c9b | 342 | tlbw_use_hazard(); |
fd062c84 DD |
343 | write_c0_pagemask(PM_DEFAULT_MASK); |
344 | } else | |
345 | #endif | |
346 | { | |
347 | ptep = pte_offset_map(pmdp, address); | |
1da177e4 | 348 | |
34adb28d | 349 | #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) |
c5b36783 SH |
350 | #ifdef CONFIG_XPA |
351 | write_c0_entrylo0(pte_to_entrylo(ptep->pte_high)); | |
4b6f99d3 JH |
352 | if (cpu_has_xpa) |
353 | writex_c0_entrylo0(ptep->pte_low & _PFNX_MASK); | |
c5b36783 SH |
354 | ptep++; |
355 | write_c0_entrylo1(pte_to_entrylo(ptep->pte_high)); | |
4b6f99d3 JH |
356 | if (cpu_has_xpa) |
357 | writex_c0_entrylo1(ptep->pte_low & _PFNX_MASK); | |
c5b36783 | 358 | #else |
fd062c84 DD |
359 | write_c0_entrylo0(ptep->pte_high); |
360 | ptep++; | |
361 | write_c0_entrylo1(ptep->pte_high); | |
c5b36783 | 362 | #endif |
1da177e4 | 363 | #else |
6dd9344c DD |
364 | write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++))); |
365 | write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep))); | |
1da177e4 | 366 | #endif |
fd062c84 DD |
367 | mtc0_tlbw_hazard(); |
368 | if (idx < 0) | |
369 | tlb_write_random(); | |
370 | else | |
371 | tlb_write_indexed(); | |
372 | } | |
1da177e4 | 373 | tlbw_use_hazard(); |
6a8dff6a | 374 | htw_start(); |
06e4814e | 375 | flush_micro_tlb_vm(vma); |
b633648c | 376 | local_irq_restore(flags); |
1da177e4 LT |
377 | } |
378 | ||
694b8c35 ML |
379 | void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, |
380 | unsigned long entryhi, unsigned long pagemask) | |
1da177e4 | 381 | { |
c5b36783 SH |
382 | #ifdef CONFIG_XPA |
383 | panic("Broken for XPA kernels"); | |
384 | #else | |
3f649ab7 | 385 | unsigned int old_mmid; |
1da177e4 LT |
386 | unsigned long flags; |
387 | unsigned long wired; | |
388 | unsigned long old_pagemask; | |
389 | unsigned long old_ctx; | |
390 | ||
b633648c | 391 | local_irq_save(flags); |
c8790d65 PB |
392 | if (cpu_has_mmid) { |
393 | old_mmid = read_c0_memorymapid(); | |
394 | write_c0_memorymapid(MMID_KERNEL_WIRED); | |
395 | } | |
1da177e4 LT |
396 | /* Save old context and create impossible VPN2 value */ |
397 | old_ctx = read_c0_entryhi(); | |
f1014d1b | 398 | htw_stop(); |
1da177e4 | 399 | old_pagemask = read_c0_pagemask(); |
10313980 | 400 | wired = num_wired_entries(); |
1da177e4 LT |
401 | write_c0_wired(wired + 1); |
402 | write_c0_index(wired); | |
432bef2a | 403 | tlbw_use_hazard(); /* What is the hazard here? */ |
1da177e4 LT |
404 | write_c0_pagemask(pagemask); |
405 | write_c0_entryhi(entryhi); | |
406 | write_c0_entrylo0(entrylo0); | |
407 | write_c0_entrylo1(entrylo1); | |
408 | mtc0_tlbw_hazard(); | |
409 | tlb_write_indexed(); | |
410 | tlbw_use_hazard(); | |
411 | ||
412 | write_c0_entryhi(old_ctx); | |
c8790d65 PB |
413 | if (cpu_has_mmid) |
414 | write_c0_memorymapid(old_mmid); | |
432bef2a | 415 | tlbw_use_hazard(); /* What is the hazard here? */ |
f1014d1b | 416 | htw_start(); |
1da177e4 LT |
417 | write_c0_pagemask(old_pagemask); |
418 | local_flush_tlb_all(); | |
b633648c | 419 | local_irq_restore(flags); |
c5b36783 | 420 | #endif |
1da177e4 LT |
421 | } |
422 | ||
970d032f RB |
423 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
424 | ||
fd8cfd30 | 425 | int has_transparent_hugepage(void) |
970d032f | 426 | { |
fd8cfd30 | 427 | static unsigned int mask = -1; |
970d032f | 428 | |
fd8cfd30 HD |
429 | if (mask == -1) { /* first call comes during __init */ |
430 | unsigned long flags; | |
970d032f | 431 | |
fd8cfd30 HD |
432 | local_irq_save(flags); |
433 | write_c0_pagemask(PM_HUGE_MASK); | |
434 | back_to_back_c0_hazard(); | |
435 | mask = read_c0_pagemask(); | |
436 | write_c0_pagemask(PM_DEFAULT_MASK); | |
437 | local_irq_restore(flags); | |
438 | } | |
970d032f RB |
439 | return mask == PM_HUGE_MASK; |
440 | } | |
441 | ||
442 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
443 | ||
d377732c RM |
444 | /* |
445 | * Used for loading TLB entries before trap_init() has started, when we | |
446 | * don't actually want to add a wired entry which remains throughout the | |
447 | * lifetime of the system | |
448 | */ | |
449 | ||
b1f7e112 | 450 | int temp_tlb_entry; |
d377732c RM |
451 | |
452 | __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, | |
453 | unsigned long entryhi, unsigned long pagemask) | |
454 | { | |
455 | int ret = 0; | |
456 | unsigned long flags; | |
457 | unsigned long wired; | |
458 | unsigned long old_pagemask; | |
459 | unsigned long old_ctx; | |
460 | ||
461 | local_irq_save(flags); | |
462 | /* Save old context and create impossible VPN2 value */ | |
6a8dff6a | 463 | htw_stop(); |
d377732c RM |
464 | old_ctx = read_c0_entryhi(); |
465 | old_pagemask = read_c0_pagemask(); | |
10313980 | 466 | wired = num_wired_entries(); |
d377732c RM |
467 | if (--temp_tlb_entry < wired) { |
468 | printk(KERN_WARNING | |
469 | "No TLB space left for add_temporary_entry\n"); | |
470 | ret = -ENOSPC; | |
471 | goto out; | |
472 | } | |
473 | ||
474 | write_c0_index(temp_tlb_entry); | |
475 | write_c0_pagemask(pagemask); | |
476 | write_c0_entryhi(entryhi); | |
477 | write_c0_entrylo0(entrylo0); | |
478 | write_c0_entrylo1(entrylo1); | |
479 | mtc0_tlbw_hazard(); | |
480 | tlb_write_indexed(); | |
481 | tlbw_use_hazard(); | |
482 | ||
483 | write_c0_entryhi(old_ctx); | |
484 | write_c0_pagemask(old_pagemask); | |
6a8dff6a | 485 | htw_start(); |
d377732c RM |
486 | out: |
487 | local_irq_restore(flags); | |
488 | return ret; | |
489 | } | |
490 | ||
078a55fc | 491 | static int ntlb; |
41c594ab RB |
492 | static int __init set_ntlb(char *str) |
493 | { | |
494 | get_option(&str, &ntlb); | |
495 | return 1; | |
496 | } | |
497 | ||
498 | __setup("ntlb=", set_ntlb); | |
499 | ||
eaa38d63 JH |
500 | /* |
501 | * Configure TLB (for init or after a CPU has been powered off). | |
502 | */ | |
503 | static void r4k_tlb_configure(void) | |
1da177e4 | 504 | { |
1da177e4 LT |
505 | /* |
506 | * You should never change this register: | |
507 | * - On R4600 1.7 the tlbp never hits for pages smaller than | |
508 | * the value in the c0_pagemask register. | |
509 | * - The entire mm handling assumes the c0_pagemask register to | |
a7c2996e | 510 | * be set to fixed-size pages. |
1da177e4 | 511 | */ |
1da177e4 | 512 | write_c0_pagemask(PM_DEFAULT_MASK); |
091bc3a4 PB |
513 | back_to_back_c0_hazard(); |
514 | if (read_c0_pagemask() != PM_DEFAULT_MASK) | |
515 | panic("MMU doesn't support PAGE_SIZE=0x%lx", PAGE_SIZE); | |
516 | ||
1da177e4 | 517 | write_c0_wired(0); |
cde15b59 RB |
518 | if (current_cpu_type() == CPU_R10000 || |
519 | current_cpu_type() == CPU_R12000 || | |
30577391 JK |
520 | current_cpu_type() == CPU_R14000 || |
521 | current_cpu_type() == CPU_R16000) | |
cde15b59 | 522 | write_c0_framemask(0); |
6dd9344c | 523 | |
05857c64 | 524 | if (cpu_has_rixi) { |
6dd9344c | 525 | /* |
e05cb568 | 526 | * Enable the no read, no exec bits, and enable large physical |
6dd9344c DD |
527 | * address. |
528 | */ | |
6dd9344c | 529 | #ifdef CONFIG_64BIT |
a5770df0 SH |
530 | set_c0_pagegrain(PG_RIE | PG_XIE | PG_ELPA); |
531 | #else | |
532 | set_c0_pagegrain(PG_RIE | PG_XIE); | |
6dd9344c | 533 | #endif |
6dd9344c DD |
534 | } |
535 | ||
d377732c RM |
536 | temp_tlb_entry = current_cpu_data.tlbsize - 1; |
537 | ||
70342287 | 538 | /* From this point on the ARC firmware is dead. */ |
1da177e4 LT |
539 | local_flush_tlb_all(); |
540 | ||
c6281edb | 541 | /* Did I tell you that ARC SUCKS? */ |
eaa38d63 JH |
542 | } |
543 | ||
544 | void tlb_init(void) | |
545 | { | |
546 | r4k_tlb_configure(); | |
c6281edb | 547 | |
41c594ab RB |
548 | if (ntlb) { |
549 | if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) { | |
550 | int wired = current_cpu_data.tlbsize - ntlb; | |
551 | write_c0_wired(wired); | |
552 | write_c0_index(wired-1); | |
49a89efb | 553 | printk("Restricting TLB to %d entries\n", ntlb); |
41c594ab RB |
554 | } else |
555 | printk("Ignoring invalid argument ntlb=%d\n", ntlb); | |
556 | } | |
557 | ||
1da177e4 LT |
558 | build_tlb_refill_handler(); |
559 | } | |
eaa38d63 JH |
560 | |
561 | static int r4k_tlb_pm_notifier(struct notifier_block *self, unsigned long cmd, | |
562 | void *v) | |
563 | { | |
564 | switch (cmd) { | |
565 | case CPU_PM_ENTER_FAILED: | |
566 | case CPU_PM_EXIT: | |
567 | r4k_tlb_configure(); | |
568 | break; | |
569 | } | |
570 | ||
571 | return NOTIFY_OK; | |
572 | } | |
573 | ||
574 | static struct notifier_block r4k_tlb_pm_notifier_block = { | |
575 | .notifier_call = r4k_tlb_pm_notifier, | |
576 | }; | |
577 | ||
578 | static int __init r4k_tlb_init_pm(void) | |
579 | { | |
580 | return cpu_pm_register_notifier(&r4k_tlb_pm_notifier_block); | |
581 | } | |
582 | arch_initcall(r4k_tlb_init_pm); |