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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
70342287 RB |
8 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki | |
41c594ab | 10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
fd062c84 | 11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. |
113c62d9 | 12 | * Copyright (C) 2011 MIPS Technologies, Inc. |
41c594ab RB |
13 | * |
14 | * ... and the days got worse and worse and now you see | |
92a76f6d | 15 | * I've gone completely out of my mind. |
41c594ab RB |
16 | * |
17 | * They're coming to take me a away haha | |
18 | * they're coming to take me a away hoho hihi haha | |
19 | * to the funny farm where code is beautiful all the time ... | |
20 | * | |
21 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
22 | */ |
23 | ||
95affdda | 24 | #include <linux/bug.h> |
ccf01516 | 25 | #include <linux/export.h> |
1da177e4 LT |
26 | #include <linux/kernel.h> |
27 | #include <linux/types.h> | |
631330f5 | 28 | #include <linux/smp.h> |
1da177e4 | 29 | #include <linux/string.h> |
3d8bfdd0 | 30 | #include <linux/cache.h> |
1da177e4 | 31 | |
3d8bfdd0 | 32 | #include <asm/cacheflush.h> |
69f24d17 | 33 | #include <asm/cpu-type.h> |
3d8bfdd0 | 34 | #include <asm/pgtable.h> |
1da177e4 | 35 | #include <asm/war.h> |
3482d713 | 36 | #include <asm/uasm.h> |
b81947c6 | 37 | #include <asm/setup.h> |
722b4544 | 38 | #include <asm/tlbex.h> |
e30ec452 | 39 | |
a2d25e63 | 40 | static int mips_xpa_disabled; |
c5b36783 SH |
41 | |
42 | static int __init xpa_disable(char *s) | |
43 | { | |
44 | mips_xpa_disabled = 1; | |
45 | ||
46 | return 1; | |
47 | } | |
48 | ||
49 | __setup("noxpa", xpa_disable); | |
50 | ||
1ec56329 DD |
51 | /* |
52 | * TLB load/store/modify handlers. | |
53 | * | |
54 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
55 | * do_page_fault remains normal asm. | |
56 | */ | |
57 | extern void tlb_do_page_fault_0(void); | |
58 | extern void tlb_do_page_fault_1(void); | |
59 | ||
bf28607f DD |
60 | struct work_registers { |
61 | int r1; | |
62 | int r2; | |
63 | int r3; | |
64 | }; | |
65 | ||
66 | struct tlb_reg_save { | |
67 | unsigned long a; | |
68 | unsigned long b; | |
69 | } ____cacheline_aligned_in_smp; | |
70 | ||
71 | static struct tlb_reg_save handler_reg_save[NR_CPUS]; | |
1ec56329 | 72 | |
aeffdbba | 73 | static inline int r45k_bvahwbug(void) |
1da177e4 LT |
74 | { |
75 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
76 | return 0; | |
77 | } | |
78 | ||
aeffdbba | 79 | static inline int r4k_250MHZhwbug(void) |
1da177e4 LT |
80 | { |
81 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
82 | return 0; | |
83 | } | |
84 | ||
aeffdbba | 85 | static inline int __maybe_unused bcm1250_m3_war(void) |
1da177e4 LT |
86 | { |
87 | return BCM1250_M3_WAR; | |
88 | } | |
89 | ||
aeffdbba | 90 | static inline int __maybe_unused r10000_llsc_war(void) |
1da177e4 LT |
91 | { |
92 | return R10000_LLSC_WAR; | |
93 | } | |
94 | ||
cc33ae43 DD |
95 | static int use_bbit_insns(void) |
96 | { | |
97 | switch (current_cpu_type()) { | |
98 | case CPU_CAVIUM_OCTEON: | |
99 | case CPU_CAVIUM_OCTEON_PLUS: | |
100 | case CPU_CAVIUM_OCTEON2: | |
4723b20a | 101 | case CPU_CAVIUM_OCTEON3: |
cc33ae43 DD |
102 | return 1; |
103 | default: | |
104 | return 0; | |
105 | } | |
106 | } | |
107 | ||
2c8c53e2 DD |
108 | static int use_lwx_insns(void) |
109 | { | |
110 | switch (current_cpu_type()) { | |
111 | case CPU_CAVIUM_OCTEON2: | |
4723b20a | 112 | case CPU_CAVIUM_OCTEON3: |
2c8c53e2 DD |
113 | return 1; |
114 | default: | |
115 | return 0; | |
116 | } | |
117 | } | |
118 | #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ | |
119 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 | |
120 | static bool scratchpad_available(void) | |
121 | { | |
122 | return true; | |
123 | } | |
124 | static int scratchpad_offset(int i) | |
125 | { | |
126 | /* | |
127 | * CVMSEG starts at address -32768 and extends for | |
128 | * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. | |
129 | */ | |
130 | i += 1; /* Kernel use starts at the top and works down. */ | |
131 | return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; | |
132 | } | |
133 | #else | |
134 | static bool scratchpad_available(void) | |
135 | { | |
136 | return false; | |
137 | } | |
138 | static int scratchpad_offset(int i) | |
139 | { | |
140 | BUG(); | |
e1c87d2a DD |
141 | /* Really unreachable, but evidently some GCC want this. */ |
142 | return 0; | |
2c8c53e2 DD |
143 | } |
144 | #endif | |
8df5beac MR |
145 | /* |
146 | * Found by experiment: At least some revisions of the 4kc throw under | |
147 | * some circumstances a machine check exception, triggered by invalid | |
148 | * values in the index register. Delaying the tlbp instruction until | |
149 | * after the next branch, plus adding an additional nop in front of | |
150 | * tlbwi/tlbwr avoids the invalid index register values. Nobody knows | |
151 | * why; it's not an issue caused by the core RTL. | |
152 | * | |
153 | */ | |
078a55fc | 154 | static int m4kc_tlbp_war(void) |
8df5beac MR |
155 | { |
156 | return (current_cpu_data.processor_id & 0xffff00) == | |
157 | (PRID_COMP_MIPS | PRID_IMP_4KC); | |
158 | } | |
159 | ||
e30ec452 | 160 | /* Handle labels (which must be positive integers). */ |
1da177e4 | 161 | enum label_id { |
e30ec452 | 162 | label_second_part = 1, |
1da177e4 LT |
163 | label_leave, |
164 | label_vmalloc, | |
165 | label_vmalloc_done, | |
02a54177 RB |
166 | label_tlbw_hazard_0, |
167 | label_split = label_tlbw_hazard_0 + 8, | |
6dd9344c DD |
168 | label_tlbl_goaround1, |
169 | label_tlbl_goaround2, | |
1da177e4 LT |
170 | label_nopage_tlbl, |
171 | label_nopage_tlbs, | |
172 | label_nopage_tlbm, | |
173 | label_smp_pgtable_change, | |
174 | label_r3000_write_probe_fail, | |
1ec56329 | 175 | label_large_segbits_fault, |
aa1762f4 | 176 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
177 | label_tlb_huge_update, |
178 | #endif | |
1da177e4 LT |
179 | }; |
180 | ||
e30ec452 TS |
181 | UASM_L_LA(_second_part) |
182 | UASM_L_LA(_leave) | |
e30ec452 TS |
183 | UASM_L_LA(_vmalloc) |
184 | UASM_L_LA(_vmalloc_done) | |
02a54177 | 185 | /* _tlbw_hazard_x is handled differently. */ |
e30ec452 | 186 | UASM_L_LA(_split) |
6dd9344c DD |
187 | UASM_L_LA(_tlbl_goaround1) |
188 | UASM_L_LA(_tlbl_goaround2) | |
e30ec452 TS |
189 | UASM_L_LA(_nopage_tlbl) |
190 | UASM_L_LA(_nopage_tlbs) | |
191 | UASM_L_LA(_nopage_tlbm) | |
192 | UASM_L_LA(_smp_pgtable_change) | |
193 | UASM_L_LA(_r3000_write_probe_fail) | |
1ec56329 | 194 | UASM_L_LA(_large_segbits_fault) |
aa1762f4 | 195 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
196 | UASM_L_LA(_tlb_huge_update) |
197 | #endif | |
656be92f | 198 | |
078a55fc | 199 | static int hazard_instance; |
02a54177 | 200 | |
078a55fc | 201 | static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) |
02a54177 RB |
202 | { |
203 | switch (instance) { | |
204 | case 0 ... 7: | |
205 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); | |
206 | return; | |
207 | default: | |
208 | BUG(); | |
209 | } | |
210 | } | |
211 | ||
078a55fc | 212 | static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) |
02a54177 RB |
213 | { |
214 | switch (instance) { | |
215 | case 0 ... 7: | |
216 | uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); | |
217 | break; | |
218 | default: | |
219 | BUG(); | |
220 | } | |
221 | } | |
222 | ||
92b1e6a6 | 223 | /* |
a2c763e0 RB |
224 | * pgtable bits are assigned dynamically depending on processor feature |
225 | * and statically based on kernel configuration. This spits out the actual | |
70342287 | 226 | * values the kernel is using. Required to make sense from disassembled |
a2c763e0 | 227 | * TLB exception handlers. |
92b1e6a6 | 228 | */ |
a2c763e0 RB |
229 | static void output_pgtable_bits_defines(void) |
230 | { | |
231 | #define pr_define(fmt, ...) \ | |
232 | pr_debug("#define " fmt, ##__VA_ARGS__) | |
233 | ||
234 | pr_debug("#include <asm/asm.h>\n"); | |
235 | pr_debug("#include <asm/regdef.h>\n"); | |
236 | pr_debug("\n"); | |
237 | ||
238 | pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); | |
780602d7 | 239 | pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); |
a2c763e0 RB |
240 | pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); |
241 | pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); | |
242 | pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); | |
970d032f | 243 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
a2c763e0 RB |
244 | pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); |
245 | #endif | |
a2c763e0 | 246 | #ifdef _PAGE_NO_EXEC_SHIFT |
780602d7 | 247 | if (cpu_has_rixi) |
a2c763e0 | 248 | pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); |
be0c37c9 | 249 | #endif |
a2c763e0 RB |
250 | pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); |
251 | pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); | |
252 | pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); | |
253 | pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); | |
254 | pr_debug("\n"); | |
255 | } | |
256 | ||
257 | static inline void dump_handler(const char *symbol, const u32 *handler, int count) | |
92b1e6a6 FBH |
258 | { |
259 | int i; | |
260 | ||
a2c763e0 RB |
261 | pr_debug("LEAF(%s)\n", symbol); |
262 | ||
92b1e6a6 FBH |
263 | pr_debug("\t.set push\n"); |
264 | pr_debug("\t.set noreorder\n"); | |
265 | ||
266 | for (i = 0; i < count; i++) | |
a2c763e0 | 267 | pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); |
92b1e6a6 | 268 | |
a2c763e0 RB |
269 | pr_debug("\t.set\tpop\n"); |
270 | ||
271 | pr_debug("\tEND(%s)\n", symbol); | |
92b1e6a6 FBH |
272 | } |
273 | ||
1da177e4 LT |
274 | /* The only general purpose registers allowed in TLB handlers. */ |
275 | #define K0 26 | |
276 | #define K1 27 | |
277 | ||
278 | /* Some CP0 registers */ | |
41c594ab RB |
279 | #define C0_INDEX 0, 0 |
280 | #define C0_ENTRYLO0 2, 0 | |
281 | #define C0_TCBIND 2, 2 | |
282 | #define C0_ENTRYLO1 3, 0 | |
283 | #define C0_CONTEXT 4, 0 | |
fd062c84 | 284 | #define C0_PAGEMASK 5, 0 |
380cd582 HC |
285 | #define C0_PWBASE 5, 5 |
286 | #define C0_PWFIELD 5, 6 | |
287 | #define C0_PWSIZE 5, 7 | |
288 | #define C0_PWCTL 6, 6 | |
41c594ab | 289 | #define C0_BADVADDR 8, 0 |
380cd582 | 290 | #define C0_PGD 9, 7 |
41c594ab RB |
291 | #define C0_ENTRYHI 10, 0 |
292 | #define C0_EPC 14, 0 | |
293 | #define C0_XCONTEXT 20, 0 | |
1da177e4 | 294 | |
875d43e7 | 295 | #ifdef CONFIG_64BIT |
e30ec452 | 296 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) |
1da177e4 | 297 | #else |
e30ec452 | 298 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) |
1da177e4 LT |
299 | #endif |
300 | ||
301 | /* The worst case length of the handler is around 18 instructions for | |
302 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
303 | * Maximum space available is 32 instructions for R3000 and 64 | |
304 | * instructions for R4000. | |
305 | * | |
306 | * We deliberately chose a buffer size of 128, so we won't scribble | |
307 | * over anything important on overflow before we panic. | |
308 | */ | |
078a55fc | 309 | static u32 tlb_handler[128]; |
1da177e4 LT |
310 | |
311 | /* simply assume worst case size for labels and relocs */ | |
078a55fc PG |
312 | static struct uasm_label labels[128]; |
313 | static struct uasm_reloc relocs[128]; | |
1da177e4 | 314 | |
078a55fc | 315 | static int check_for_high_segbits; |
00bf1c69 | 316 | static bool fill_includes_sw_bits; |
3d8bfdd0 | 317 | |
078a55fc | 318 | static unsigned int kscratch_used_mask; |
3d8bfdd0 | 319 | |
7777b939 J |
320 | static inline int __maybe_unused c0_kscratch(void) |
321 | { | |
322 | switch (current_cpu_type()) { | |
323 | case CPU_XLP: | |
324 | case CPU_XLR: | |
325 | return 22; | |
326 | default: | |
327 | return 31; | |
328 | } | |
329 | } | |
330 | ||
078a55fc | 331 | static int allocate_kscratch(void) |
3d8bfdd0 DD |
332 | { |
333 | int r; | |
334 | unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; | |
335 | ||
336 | r = ffs(a); | |
337 | ||
338 | if (r == 0) | |
339 | return -1; | |
340 | ||
341 | r--; /* make it zero based */ | |
342 | ||
343 | kscratch_used_mask |= (1 << r); | |
344 | ||
345 | return r; | |
346 | } | |
347 | ||
078a55fc | 348 | static int scratch_reg; |
722b4544 JH |
349 | int pgd_reg; |
350 | EXPORT_SYMBOL_GPL(pgd_reg); | |
2c8c53e2 DD |
351 | enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; |
352 | ||
078a55fc | 353 | static struct work_registers build_get_work_registers(u32 **p) |
bf28607f DD |
354 | { |
355 | struct work_registers r; | |
356 | ||
0e6ecc1a | 357 | if (scratch_reg >= 0) { |
bf28607f | 358 | /* Save in CPU local C0_KScratch? */ |
7777b939 | 359 | UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); |
bf28607f DD |
360 | r.r1 = K0; |
361 | r.r2 = K1; | |
362 | r.r3 = 1; | |
363 | return r; | |
364 | } | |
365 | ||
366 | if (num_possible_cpus() > 1) { | |
bf28607f | 367 | /* Get smp_processor_id */ |
c2377a42 J |
368 | UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); |
369 | UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); | |
bf28607f DD |
370 | |
371 | /* handler_reg_save index in K0 */ | |
372 | UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); | |
373 | ||
374 | UASM_i_LA(p, K1, (long)&handler_reg_save); | |
375 | UASM_i_ADDU(p, K0, K0, K1); | |
376 | } else { | |
377 | UASM_i_LA(p, K0, (long)&handler_reg_save); | |
378 | } | |
379 | /* K0 now points to save area, save $1 and $2 */ | |
380 | UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); | |
381 | UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); | |
382 | ||
383 | r.r1 = K1; | |
384 | r.r2 = 1; | |
385 | r.r3 = 2; | |
386 | return r; | |
387 | } | |
388 | ||
078a55fc | 389 | static void build_restore_work_registers(u32 **p) |
bf28607f | 390 | { |
0e6ecc1a | 391 | if (scratch_reg >= 0) { |
7777b939 | 392 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
bf28607f DD |
393 | return; |
394 | } | |
395 | /* K0 already points to save area, restore $1 and $2 */ | |
396 | UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); | |
397 | UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); | |
398 | } | |
399 | ||
2c8c53e2 | 400 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 | 401 | |
82622284 DD |
402 | /* |
403 | * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, | |
404 | * we cannot do r3000 under these circumstances. | |
3d8bfdd0 DD |
405 | * |
406 | * Declare pgd_current here instead of including mmu_context.h to avoid type | |
407 | * conflicts for tlbmiss_handler_setup_pgd | |
82622284 | 408 | */ |
3d8bfdd0 | 409 | extern unsigned long pgd_current[]; |
82622284 | 410 | |
1da177e4 LT |
411 | /* |
412 | * The R3000 TLB handler is simple. | |
413 | */ | |
078a55fc | 414 | static void build_r3000_tlb_refill_handler(void) |
1da177e4 LT |
415 | { |
416 | long pgdc = (long)pgd_current; | |
417 | u32 *p; | |
418 | ||
419 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
420 | p = tlb_handler; | |
421 | ||
e30ec452 TS |
422 | uasm_i_mfc0(&p, K0, C0_BADVADDR); |
423 | uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
424 | uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); | |
425 | uasm_i_srl(&p, K0, K0, 22); /* load delay */ | |
426 | uasm_i_sll(&p, K0, K0, 2); | |
427 | uasm_i_addu(&p, K1, K1, K0); | |
428 | uasm_i_mfc0(&p, K0, C0_CONTEXT); | |
429 | uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ | |
430 | uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ | |
431 | uasm_i_addu(&p, K1, K1, K0); | |
432 | uasm_i_lw(&p, K0, 0, K1); | |
433 | uasm_i_nop(&p); /* load delay */ | |
434 | uasm_i_mtc0(&p, K0, C0_ENTRYLO0); | |
435 | uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ | |
436 | uasm_i_tlbwr(&p); /* cp0 delay */ | |
437 | uasm_i_jr(&p, K1); | |
438 | uasm_i_rfe(&p); /* branch delay */ | |
1da177e4 LT |
439 | |
440 | if (p > tlb_handler + 32) | |
441 | panic("TLB refill handler space exceeded"); | |
442 | ||
e30ec452 TS |
443 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
444 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 445 | |
91b05e67 | 446 | memcpy((void *)ebase, tlb_handler, 0x80); |
1062080a | 447 | local_flush_icache_range(ebase, ebase + 0x80); |
92b1e6a6 | 448 | |
a2c763e0 | 449 | dump_handler("r3000_tlb_refill", (u32 *)ebase, 32); |
1da177e4 | 450 | } |
82622284 | 451 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
452 | |
453 | /* | |
454 | * The R4000 TLB handler is much more complicated. We have two | |
455 | * consecutive handler areas with 32 instructions space each. | |
456 | * Since they aren't used at the same time, we can overflow in the | |
457 | * other one.To keep things simple, we first assume linear space, | |
458 | * then we relocate it to the final handler layout as needed. | |
459 | */ | |
078a55fc | 460 | static u32 final_handler[64]; |
1da177e4 LT |
461 | |
462 | /* | |
463 | * Hazards | |
464 | * | |
465 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
466 | * 2. A timing hazard exists for the TLBP instruction. | |
467 | * | |
70342287 RB |
468 | * stalling_instruction |
469 | * TLBP | |
1da177e4 LT |
470 | * |
471 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
472 | * previous instruction. This is not really correct as the stalling instruction | |
473 | * can modify the address used to access the JTLB. The failure symptom is that | |
474 | * the TLBP instruction will use an address created for the stalling instruction | |
475 | * and not the address held in C0_ENHI and thus report the wrong results. | |
476 | * | |
477 | * The software work-around is to not allow the instruction preceding the TLBP | |
478 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
479 | * | |
70342287 | 480 | * Errata 2 will not be fixed. This errata is also on the R5000. |
1da177e4 LT |
481 | * |
482 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
483 | */ | |
078a55fc | 484 | static void __maybe_unused build_tlb_probe_entry(u32 **p) |
1da177e4 | 485 | { |
10cc3529 | 486 | switch (current_cpu_type()) { |
326e2e1a | 487 | /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ |
f5b4d956 | 488 | case CPU_R4600: |
326e2e1a | 489 | case CPU_R4700: |
1da177e4 | 490 | case CPU_R5000: |
1da177e4 | 491 | case CPU_NEVADA: |
e30ec452 TS |
492 | uasm_i_nop(p); |
493 | uasm_i_tlbp(p); | |
1da177e4 LT |
494 | break; |
495 | ||
496 | default: | |
e30ec452 | 497 | uasm_i_tlbp(p); |
1da177e4 LT |
498 | break; |
499 | } | |
500 | } | |
501 | ||
722b4544 JH |
502 | void build_tlb_write_entry(u32 **p, struct uasm_label **l, |
503 | struct uasm_reloc **r, | |
504 | enum tlb_write_entry wmode) | |
1da177e4 LT |
505 | { |
506 | void(*tlbw)(u32 **) = NULL; | |
507 | ||
508 | switch (wmode) { | |
e30ec452 TS |
509 | case tlb_random: tlbw = uasm_i_tlbwr; break; |
510 | case tlb_indexed: tlbw = uasm_i_tlbwi; break; | |
1da177e4 LT |
511 | } |
512 | ||
9eaffa84 RB |
513 | if (cpu_has_mips_r2_r6) { |
514 | if (cpu_has_mips_r2_exec_hazard) | |
41f0e4d0 | 515 | uasm_i_ehb(p); |
161548bf RB |
516 | tlbw(p); |
517 | return; | |
518 | } | |
519 | ||
10cc3529 | 520 | switch (current_cpu_type()) { |
1da177e4 LT |
521 | case CPU_R4000PC: |
522 | case CPU_R4000SC: | |
523 | case CPU_R4000MC: | |
524 | case CPU_R4400PC: | |
525 | case CPU_R4400SC: | |
526 | case CPU_R4400MC: | |
527 | /* | |
528 | * This branch uses up a mtc0 hazard nop slot and saves | |
529 | * two nops after the tlbw instruction. | |
530 | */ | |
02a54177 | 531 | uasm_bgezl_hazard(p, r, hazard_instance); |
1da177e4 | 532 | tlbw(p); |
02a54177 RB |
533 | uasm_bgezl_label(l, p, hazard_instance); |
534 | hazard_instance++; | |
e30ec452 | 535 | uasm_i_nop(p); |
1da177e4 LT |
536 | break; |
537 | ||
538 | case CPU_R4600: | |
539 | case CPU_R4700: | |
e30ec452 | 540 | uasm_i_nop(p); |
2c93e12c | 541 | tlbw(p); |
e30ec452 | 542 | uasm_i_nop(p); |
2c93e12c MR |
543 | break; |
544 | ||
359187d6 | 545 | case CPU_R5000: |
359187d6 RB |
546 | case CPU_NEVADA: |
547 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ | |
548 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ | |
549 | tlbw(p); | |
550 | break; | |
551 | ||
2c93e12c | 552 | case CPU_R4300: |
1da177e4 LT |
553 | case CPU_5KC: |
554 | case CPU_TX49XX: | |
bdf21b18 | 555 | case CPU_PR4450: |
efa0f81c | 556 | case CPU_XLR: |
e30ec452 | 557 | uasm_i_nop(p); |
1da177e4 LT |
558 | tlbw(p); |
559 | break; | |
560 | ||
561 | case CPU_R10000: | |
562 | case CPU_R12000: | |
44d921b2 | 563 | case CPU_R14000: |
30577391 | 564 | case CPU_R16000: |
1da177e4 | 565 | case CPU_4KC: |
b1ec4c8e | 566 | case CPU_4KEC: |
113c62d9 | 567 | case CPU_M14KC: |
f8fa4811 | 568 | case CPU_M14KEC: |
1da177e4 | 569 | case CPU_SB1: |
93ce2f52 | 570 | case CPU_SB1A: |
1da177e4 LT |
571 | case CPU_4KSC: |
572 | case CPU_20KC: | |
573 | case CPU_25KF: | |
602977b0 KC |
574 | case CPU_BMIPS32: |
575 | case CPU_BMIPS3300: | |
576 | case CPU_BMIPS4350: | |
577 | case CPU_BMIPS4380: | |
578 | case CPU_BMIPS5000: | |
2a21c730 | 579 | case CPU_LOONGSON2: |
c579d310 | 580 | case CPU_LOONGSON3: |
a644b277 | 581 | case CPU_R5500: |
8df5beac | 582 | if (m4kc_tlbp_war()) |
e30ec452 | 583 | uasm_i_nop(p); |
2f794d09 | 584 | case CPU_ALCHEMY: |
1da177e4 LT |
585 | tlbw(p); |
586 | break; | |
587 | ||
1da177e4 | 588 | case CPU_RM7000: |
e30ec452 TS |
589 | uasm_i_nop(p); |
590 | uasm_i_nop(p); | |
591 | uasm_i_nop(p); | |
592 | uasm_i_nop(p); | |
1da177e4 LT |
593 | tlbw(p); |
594 | break; | |
595 | ||
1da177e4 LT |
596 | case CPU_VR4111: |
597 | case CPU_VR4121: | |
598 | case CPU_VR4122: | |
599 | case CPU_VR4181: | |
600 | case CPU_VR4181A: | |
e30ec452 TS |
601 | uasm_i_nop(p); |
602 | uasm_i_nop(p); | |
1da177e4 | 603 | tlbw(p); |
e30ec452 TS |
604 | uasm_i_nop(p); |
605 | uasm_i_nop(p); | |
1da177e4 LT |
606 | break; |
607 | ||
608 | case CPU_VR4131: | |
609 | case CPU_VR4133: | |
7623debf | 610 | case CPU_R5432: |
e30ec452 TS |
611 | uasm_i_nop(p); |
612 | uasm_i_nop(p); | |
1da177e4 LT |
613 | tlbw(p); |
614 | break; | |
615 | ||
83ccf69d LPC |
616 | case CPU_JZRISC: |
617 | tlbw(p); | |
618 | uasm_i_nop(p); | |
619 | break; | |
620 | ||
1da177e4 LT |
621 | default: |
622 | panic("No TLB refill handler yet (CPU type: %d)", | |
d7b12056 | 623 | current_cpu_type()); |
1da177e4 LT |
624 | break; |
625 | } | |
626 | } | |
722b4544 | 627 | EXPORT_SYMBOL_GPL(build_tlb_write_entry); |
1da177e4 | 628 | |
078a55fc PG |
629 | static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, |
630 | unsigned int reg) | |
fd062c84 | 631 | { |
2caa89b4 PB |
632 | if (_PAGE_GLOBAL_SHIFT == 0) { |
633 | /* pte_t is already in EntryLo format */ | |
634 | return; | |
635 | } | |
636 | ||
00bf1c69 PB |
637 | if (cpu_has_rixi && _PAGE_NO_EXEC) { |
638 | if (fill_includes_sw_bits) { | |
639 | UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); | |
640 | } else { | |
641 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); | |
642 | UASM_i_ROTR(p, reg, reg, | |
643 | ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
644 | } | |
6dd9344c | 645 | } else { |
34adb28d | 646 | #ifdef CONFIG_PHYS_ADDR_T_64BIT |
3be6022c | 647 | uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
648 | #else |
649 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); | |
650 | #endif | |
651 | } | |
652 | } | |
fd062c84 | 653 | |
aa1762f4 | 654 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 655 | |
078a55fc PG |
656 | static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, |
657 | unsigned int tmp, enum label_id lid, | |
658 | int restore_scratch) | |
6dd9344c | 659 | { |
2c8c53e2 DD |
660 | if (restore_scratch) { |
661 | /* Reset default page size */ | |
662 | if (PM_DEFAULT_MASK >> 16) { | |
663 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
664 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
665 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
666 | uasm_il_b(p, r, lid); | |
667 | } else if (PM_DEFAULT_MASK) { | |
668 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
669 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
670 | uasm_il_b(p, r, lid); | |
671 | } else { | |
672 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
673 | uasm_il_b(p, r, lid); | |
674 | } | |
0e6ecc1a | 675 | if (scratch_reg >= 0) |
7777b939 | 676 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
2c8c53e2 DD |
677 | else |
678 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); | |
fd062c84 | 679 | } else { |
2c8c53e2 DD |
680 | /* Reset default page size */ |
681 | if (PM_DEFAULT_MASK >> 16) { | |
682 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
683 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
684 | uasm_il_b(p, r, lid); | |
685 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
686 | } else if (PM_DEFAULT_MASK) { | |
687 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
688 | uasm_il_b(p, r, lid); | |
689 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
690 | } else { | |
691 | uasm_il_b(p, r, lid); | |
692 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
693 | } | |
fd062c84 DD |
694 | } |
695 | } | |
696 | ||
078a55fc PG |
697 | static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, |
698 | struct uasm_reloc **r, | |
699 | unsigned int tmp, | |
700 | enum tlb_write_entry wmode, | |
701 | int restore_scratch) | |
6dd9344c DD |
702 | { |
703 | /* Set huge page tlb entry size */ | |
704 | uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); | |
705 | uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); | |
706 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
707 | ||
708 | build_tlb_write_entry(p, l, r, wmode); | |
709 | ||
2c8c53e2 | 710 | build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); |
6dd9344c DD |
711 | } |
712 | ||
fd062c84 DD |
713 | /* |
714 | * Check if Huge PTE is present, if so then jump to LABEL. | |
715 | */ | |
078a55fc | 716 | static void |
fd062c84 | 717 | build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, |
078a55fc | 718 | unsigned int pmd, int lid) |
fd062c84 DD |
719 | { |
720 | UASM_i_LW(p, tmp, 0, pmd); | |
cc33ae43 DD |
721 | if (use_bbit_insns()) { |
722 | uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); | |
723 | } else { | |
724 | uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); | |
725 | uasm_il_bnez(p, r, tmp, lid); | |
726 | } | |
fd062c84 DD |
727 | } |
728 | ||
078a55fc PG |
729 | static void build_huge_update_entries(u32 **p, unsigned int pte, |
730 | unsigned int tmp) | |
fd062c84 DD |
731 | { |
732 | int small_sequence; | |
733 | ||
734 | /* | |
735 | * A huge PTE describes an area the size of the | |
736 | * configured huge page size. This is twice the | |
737 | * of the large TLB entry size we intend to use. | |
738 | * A TLB entry half the size of the configured | |
739 | * huge page size is configured into entrylo0 | |
740 | * and entrylo1 to cover the contiguous huge PTE | |
741 | * address space. | |
742 | */ | |
743 | small_sequence = (HPAGE_SIZE >> 7) < 0x10000; | |
744 | ||
70342287 | 745 | /* We can clobber tmp. It isn't used after this.*/ |
fd062c84 DD |
746 | if (!small_sequence) |
747 | uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); | |
748 | ||
6dd9344c | 749 | build_convert_pte_to_entrylo(p, pte); |
9b8c3891 | 750 | UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ |
fd062c84 DD |
751 | /* convert to entrylo1 */ |
752 | if (small_sequence) | |
753 | UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); | |
754 | else | |
755 | UASM_i_ADDU(p, pte, pte, tmp); | |
756 | ||
9b8c3891 | 757 | UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ |
fd062c84 DD |
758 | } |
759 | ||
078a55fc PG |
760 | static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, |
761 | struct uasm_label **l, | |
762 | unsigned int pte, | |
763 | unsigned int ptr) | |
fd062c84 DD |
764 | { |
765 | #ifdef CONFIG_SMP | |
766 | UASM_i_SC(p, pte, 0, ptr); | |
767 | uasm_il_beqz(p, r, pte, label_tlb_huge_update); | |
768 | UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ | |
769 | #else | |
770 | UASM_i_SW(p, pte, 0, ptr); | |
771 | #endif | |
772 | build_huge_update_entries(p, pte, ptr); | |
2c8c53e2 | 773 | build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); |
fd062c84 | 774 | } |
aa1762f4 | 775 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
fd062c84 | 776 | |
875d43e7 | 777 | #ifdef CONFIG_64BIT |
1da177e4 LT |
778 | /* |
779 | * TMP and PTR are scratch. | |
780 | * TMP will be clobbered, PTR will hold the pmd entry. | |
781 | */ | |
722b4544 JH |
782 | void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
783 | unsigned int tmp, unsigned int ptr) | |
1da177e4 | 784 | { |
82622284 | 785 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 | 786 | long pgdc = (long)pgd_current; |
82622284 | 787 | #endif |
1da177e4 LT |
788 | /* |
789 | * The vmalloc handling is not in the hotpath. | |
790 | */ | |
e30ec452 | 791 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
1ec56329 DD |
792 | |
793 | if (check_for_high_segbits) { | |
794 | /* | |
795 | * The kernel currently implicitely assumes that the | |
796 | * MIPS SEGBITS parameter for the processor is | |
797 | * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never | |
798 | * allocate virtual addresses outside the maximum | |
799 | * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But | |
800 | * that doesn't prevent user code from accessing the | |
801 | * higher xuseg addresses. Here, we make sure that | |
802 | * everything but the lower xuseg addresses goes down | |
803 | * the module_alloc/vmalloc path. | |
804 | */ | |
805 | uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
806 | uasm_il_bnez(p, r, ptr, label_vmalloc); | |
807 | } else { | |
808 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
809 | } | |
e30ec452 | 810 | /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ |
1da177e4 | 811 | |
3d8bfdd0 DD |
812 | if (pgd_reg != -1) { |
813 | /* pgd is in pgd_reg */ | |
380cd582 HC |
814 | if (cpu_has_ldpte) |
815 | UASM_i_MFC0(p, ptr, C0_PWBASE); | |
816 | else | |
817 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); | |
3d8bfdd0 | 818 | } else { |
f4ae17aa | 819 | #if defined(CONFIG_MIPS_PGD_C0_CONTEXT) |
3d8bfdd0 DD |
820 | /* |
821 | * &pgd << 11 stored in CONTEXT [23..63]. | |
822 | */ | |
823 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
824 | ||
825 | /* Clear lower 23 bits of context. */ | |
826 | uasm_i_dins(p, ptr, 0, 0, 23); | |
827 | ||
70342287 | 828 | /* 1 0 1 0 1 << 6 xkphys cached */ |
3d8bfdd0 DD |
829 | uasm_i_ori(p, ptr, ptr, 0x540); |
830 | uasm_i_drotr(p, ptr, ptr, 11); | |
82622284 | 831 | #elif defined(CONFIG_SMP) |
f4ae17aa J |
832 | UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); |
833 | uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); | |
834 | UASM_i_LA_mostly(p, tmp, pgdc); | |
835 | uasm_i_daddu(p, ptr, ptr, tmp); | |
836 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); | |
837 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 838 | #else |
f4ae17aa J |
839 | UASM_i_LA_mostly(p, ptr, pgdc); |
840 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 841 | #endif |
f4ae17aa | 842 | } |
1da177e4 | 843 | |
e30ec452 | 844 | uasm_l_vmalloc_done(l, *p); |
242954b5 | 845 | |
3be6022c DD |
846 | /* get pgd offset in bytes */ |
847 | uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); | |
e30ec452 TS |
848 | |
849 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); | |
850 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
325f8a0a | 851 | #ifndef __PAGETABLE_PMD_FOLDED |
e30ec452 TS |
852 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
853 | uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
3be6022c | 854 | uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ |
e30ec452 TS |
855 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); |
856 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
325f8a0a | 857 | #endif |
1da177e4 | 858 | } |
722b4544 | 859 | EXPORT_SYMBOL_GPL(build_get_pmde64); |
1da177e4 LT |
860 | |
861 | /* | |
862 | * BVADDR is the faulting address, PTR is scratch. | |
863 | * PTR will hold the pgd for vmalloc. | |
864 | */ | |
078a55fc | 865 | static void |
e30ec452 | 866 | build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1ec56329 DD |
867 | unsigned int bvaddr, unsigned int ptr, |
868 | enum vmalloc64_mode mode) | |
1da177e4 LT |
869 | { |
870 | long swpd = (long)swapper_pg_dir; | |
1ec56329 DD |
871 | int single_insn_swpd; |
872 | int did_vmalloc_branch = 0; | |
873 | ||
874 | single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); | |
1da177e4 | 875 | |
e30ec452 | 876 | uasm_l_vmalloc(l, *p); |
1da177e4 | 877 | |
2c8c53e2 | 878 | if (mode != not_refill && check_for_high_segbits) { |
1ec56329 DD |
879 | if (single_insn_swpd) { |
880 | uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); | |
881 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
882 | did_vmalloc_branch = 1; | |
883 | /* fall through */ | |
884 | } else { | |
885 | uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); | |
886 | } | |
887 | } | |
888 | if (!did_vmalloc_branch) { | |
2f8f8c04 | 889 | if (single_insn_swpd) { |
1ec56329 DD |
890 | uasm_il_b(p, r, label_vmalloc_done); |
891 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
892 | } else { | |
893 | UASM_i_LA_mostly(p, ptr, swpd); | |
894 | uasm_il_b(p, r, label_vmalloc_done); | |
895 | if (uasm_in_compat_space_p(swpd)) | |
896 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
897 | else | |
898 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
899 | } | |
900 | } | |
2c8c53e2 | 901 | if (mode != not_refill && check_for_high_segbits) { |
1ec56329 DD |
902 | uasm_l_large_segbits_fault(l, *p); |
903 | /* | |
904 | * We get here if we are an xsseg address, or if we are | |
905 | * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. | |
906 | * | |
907 | * Ignoring xsseg (assume disabled so would generate | |
908 | * (address errors?), the only remaining possibility | |
909 | * is the upper xuseg addresses. On processors with | |
910 | * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these | |
911 | * addresses would have taken an address error. We try | |
912 | * to mimic that here by taking a load/istream page | |
913 | * fault. | |
914 | */ | |
915 | UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); | |
916 | uasm_i_jr(p, ptr); | |
2c8c53e2 DD |
917 | |
918 | if (mode == refill_scratch) { | |
0e6ecc1a | 919 | if (scratch_reg >= 0) |
7777b939 | 920 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
2c8c53e2 DD |
921 | else |
922 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); | |
923 | } else { | |
924 | uasm_i_nop(p); | |
925 | } | |
1da177e4 LT |
926 | } |
927 | } | |
928 | ||
875d43e7 | 929 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
930 | |
931 | /* | |
932 | * TMP and PTR are scratch. | |
933 | * TMP will be clobbered, PTR will hold the pgd entry. | |
934 | */ | |
722b4544 | 935 | void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 | 936 | { |
f4ae17aa J |
937 | if (pgd_reg != -1) { |
938 | /* pgd is in pgd_reg */ | |
939 | uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); | |
940 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ | |
941 | } else { | |
942 | long pgdc = (long)pgd_current; | |
1da177e4 | 943 | |
f4ae17aa | 944 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ |
1da177e4 | 945 | #ifdef CONFIG_SMP |
f4ae17aa J |
946 | uasm_i_mfc0(p, ptr, SMP_CPUID_REG); |
947 | UASM_i_LA_mostly(p, tmp, pgdc); | |
948 | uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); | |
949 | uasm_i_addu(p, ptr, tmp, ptr); | |
1da177e4 | 950 | #else |
f4ae17aa | 951 | UASM_i_LA_mostly(p, ptr, pgdc); |
1da177e4 | 952 | #endif |
f4ae17aa J |
953 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
954 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
955 | } | |
e30ec452 TS |
956 | uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ |
957 | uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); | |
958 | uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1da177e4 | 959 | } |
722b4544 | 960 | EXPORT_SYMBOL_GPL(build_get_pgde32); |
1da177e4 | 961 | |
875d43e7 | 962 | #endif /* !CONFIG_64BIT */ |
1da177e4 | 963 | |
078a55fc | 964 | static void build_adjust_context(u32 **p, unsigned int ctx) |
1da177e4 | 965 | { |
242954b5 | 966 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1da177e4 LT |
967 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
968 | ||
10cc3529 | 969 | switch (current_cpu_type()) { |
1da177e4 LT |
970 | case CPU_VR41XX: |
971 | case CPU_VR4111: | |
972 | case CPU_VR4121: | |
973 | case CPU_VR4122: | |
974 | case CPU_VR4131: | |
975 | case CPU_VR4181: | |
976 | case CPU_VR4181A: | |
977 | case CPU_VR4133: | |
978 | shift += 2; | |
979 | break; | |
980 | ||
981 | default: | |
982 | break; | |
983 | } | |
984 | ||
985 | if (shift) | |
e30ec452 TS |
986 | UASM_i_SRL(p, ctx, ctx, shift); |
987 | uasm_i_andi(p, ctx, ctx, mask); | |
1da177e4 LT |
988 | } |
989 | ||
722b4544 | 990 | void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 LT |
991 | { |
992 | /* | |
993 | * Bug workaround for the Nevada. It seems as if under certain | |
994 | * circumstances the move from cp0_context might produce a | |
995 | * bogus result when the mfc0 instruction and its consumer are | |
996 | * in a different cacheline or a load instruction, probably any | |
997 | * memory reference, is between them. | |
998 | */ | |
10cc3529 | 999 | switch (current_cpu_type()) { |
1da177e4 | 1000 | case CPU_NEVADA: |
e30ec452 | 1001 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
1002 | GET_CONTEXT(p, tmp); /* get context reg */ |
1003 | break; | |
1004 | ||
1005 | default: | |
1006 | GET_CONTEXT(p, tmp); /* get context reg */ | |
e30ec452 | 1007 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
1008 | break; |
1009 | } | |
1010 | ||
1011 | build_adjust_context(p, tmp); | |
e30ec452 | 1012 | UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ |
1da177e4 | 1013 | } |
722b4544 | 1014 | EXPORT_SYMBOL_GPL(build_get_ptep); |
1da177e4 | 1015 | |
722b4544 | 1016 | void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) |
1da177e4 | 1017 | { |
2caa89b4 PB |
1018 | int pte_off_even = 0; |
1019 | int pte_off_odd = sizeof(pte_t); | |
7b2cb64f | 1020 | |
2caa89b4 PB |
1021 | #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT) |
1022 | /* The low 32 bits of EntryLo is stored in pte_high */ | |
1023 | pte_off_even += offsetof(pte_t, pte_high); | |
1024 | pte_off_odd += offsetof(pte_t, pte_high); | |
1025 | #endif | |
1026 | ||
97f2645f | 1027 | if (IS_ENABLED(CONFIG_XPA)) { |
c5b36783 | 1028 | uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */ |
c5b36783 | 1029 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); |
c5b36783 | 1030 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); |
7b2cb64f | 1031 | |
4b6f99d3 JH |
1032 | if (cpu_has_xpa && !mips_xpa_disabled) { |
1033 | uasm_i_lw(p, tmp, 0, ptep); | |
1034 | uasm_i_ext(p, tmp, tmp, 0, 24); | |
1035 | uasm_i_mthc0(p, tmp, C0_ENTRYLO0); | |
1036 | } | |
f3832196 JH |
1037 | |
1038 | uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */ | |
1039 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); | |
1040 | UASM_i_MTC0(p, tmp, C0_ENTRYLO1); | |
1041 | ||
4b6f99d3 JH |
1042 | if (cpu_has_xpa && !mips_xpa_disabled) { |
1043 | uasm_i_lw(p, tmp, sizeof(pte_t), ptep); | |
1044 | uasm_i_ext(p, tmp, tmp, 0, 24); | |
1045 | uasm_i_mthc0(p, tmp, C0_ENTRYLO1); | |
1046 | } | |
7b2cb64f PB |
1047 | return; |
1048 | } | |
1049 | ||
2caa89b4 PB |
1050 | UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */ |
1051 | UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */ | |
1da177e4 LT |
1052 | if (r45k_bvahwbug()) |
1053 | build_tlb_probe_entry(p); | |
974a0b6a PB |
1054 | build_convert_pte_to_entrylo(p, tmp); |
1055 | if (r4k_250MHZhwbug()) | |
1056 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
1057 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
1058 | build_convert_pte_to_entrylo(p, ptep); | |
1059 | if (r45k_bvahwbug()) | |
1060 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1da177e4 | 1061 | if (r4k_250MHZhwbug()) |
9b8c3891 DD |
1062 | UASM_i_MTC0(p, 0, C0_ENTRYLO1); |
1063 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 | 1064 | } |
722b4544 | 1065 | EXPORT_SYMBOL_GPL(build_update_entries); |
1da177e4 | 1066 | |
2c8c53e2 DD |
1067 | struct mips_huge_tlb_info { |
1068 | int huge_pte; | |
1069 | int restore_scratch; | |
9e0f162a | 1070 | bool need_reload_pte; |
2c8c53e2 DD |
1071 | }; |
1072 | ||
078a55fc | 1073 | static struct mips_huge_tlb_info |
2c8c53e2 DD |
1074 | build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, |
1075 | struct uasm_reloc **r, unsigned int tmp, | |
7777b939 | 1076 | unsigned int ptr, int c0_scratch_reg) |
2c8c53e2 DD |
1077 | { |
1078 | struct mips_huge_tlb_info rv; | |
1079 | unsigned int even, odd; | |
1080 | int vmalloc_branch_delay_filled = 0; | |
1081 | const int scratch = 1; /* Our extra working register */ | |
1082 | ||
1083 | rv.huge_pte = scratch; | |
1084 | rv.restore_scratch = 0; | |
9e0f162a | 1085 | rv.need_reload_pte = false; |
2c8c53e2 DD |
1086 | |
1087 | if (check_for_high_segbits) { | |
1088 | UASM_i_MFC0(p, tmp, C0_BADVADDR); | |
1089 | ||
1090 | if (pgd_reg != -1) | |
7777b939 | 1091 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
2c8c53e2 DD |
1092 | else |
1093 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
1094 | ||
7777b939 J |
1095 | if (c0_scratch_reg >= 0) |
1096 | UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1097 | else |
1098 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); | |
1099 | ||
1100 | uasm_i_dsrl_safe(p, scratch, tmp, | |
1101 | PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
1102 | uasm_il_bnez(p, r, scratch, label_vmalloc); | |
1103 | ||
1104 | if (pgd_reg == -1) { | |
1105 | vmalloc_branch_delay_filled = 1; | |
1106 | /* Clear lower 23 bits of context. */ | |
1107 | uasm_i_dins(p, ptr, 0, 0, 23); | |
1108 | } | |
1109 | } else { | |
1110 | if (pgd_reg != -1) | |
7777b939 | 1111 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
2c8c53e2 DD |
1112 | else |
1113 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
1114 | ||
1115 | UASM_i_MFC0(p, tmp, C0_BADVADDR); | |
1116 | ||
7777b939 J |
1117 | if (c0_scratch_reg >= 0) |
1118 | UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1119 | else |
1120 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); | |
1121 | ||
1122 | if (pgd_reg == -1) | |
1123 | /* Clear lower 23 bits of context. */ | |
1124 | uasm_i_dins(p, ptr, 0, 0, 23); | |
1125 | ||
1126 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
1127 | } | |
1128 | ||
1129 | if (pgd_reg == -1) { | |
1130 | vmalloc_branch_delay_filled = 1; | |
70342287 | 1131 | /* 1 0 1 0 1 << 6 xkphys cached */ |
2c8c53e2 DD |
1132 | uasm_i_ori(p, ptr, ptr, 0x540); |
1133 | uasm_i_drotr(p, ptr, ptr, 11); | |
1134 | } | |
1135 | ||
1136 | #ifdef __PAGETABLE_PMD_FOLDED | |
1137 | #define LOC_PTEP scratch | |
1138 | #else | |
1139 | #define LOC_PTEP ptr | |
1140 | #endif | |
1141 | ||
1142 | if (!vmalloc_branch_delay_filled) | |
1143 | /* get pgd offset in bytes */ | |
1144 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); | |
1145 | ||
1146 | uasm_l_vmalloc_done(l, *p); | |
1147 | ||
1148 | /* | |
70342287 RB |
1149 | * tmp ptr |
1150 | * fall-through case = badvaddr *pgd_current | |
1151 | * vmalloc case = badvaddr swapper_pg_dir | |
2c8c53e2 DD |
1152 | */ |
1153 | ||
1154 | if (vmalloc_branch_delay_filled) | |
1155 | /* get pgd offset in bytes */ | |
1156 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); | |
1157 | ||
1158 | #ifdef __PAGETABLE_PMD_FOLDED | |
1159 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1160 | #endif | |
1161 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); | |
1162 | ||
1163 | if (use_lwx_insns()) { | |
1164 | UASM_i_LWX(p, LOC_PTEP, scratch, ptr); | |
1165 | } else { | |
1166 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ | |
1167 | uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ | |
1168 | } | |
1169 | ||
1170 | #ifndef __PAGETABLE_PMD_FOLDED | |
1171 | /* get pmd offset in bytes */ | |
1172 | uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); | |
1173 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); | |
1174 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1175 | ||
1176 | if (use_lwx_insns()) { | |
1177 | UASM_i_LWX(p, scratch, scratch, ptr); | |
1178 | } else { | |
1179 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ | |
1180 | UASM_i_LW(p, scratch, 0, ptr); | |
1181 | } | |
1182 | #endif | |
1183 | /* Adjust the context during the load latency. */ | |
1184 | build_adjust_context(p, tmp); | |
1185 | ||
aa1762f4 | 1186 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
2c8c53e2 DD |
1187 | uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); |
1188 | /* | |
1189 | * The in the LWX case we don't want to do the load in the | |
70342287 | 1190 | * delay slot. It cannot issue in the same cycle and may be |
2c8c53e2 DD |
1191 | * speculative and unneeded. |
1192 | */ | |
1193 | if (use_lwx_insns()) | |
1194 | uasm_i_nop(p); | |
aa1762f4 | 1195 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
2c8c53e2 DD |
1196 | |
1197 | ||
1198 | /* build_update_entries */ | |
1199 | if (use_lwx_insns()) { | |
1200 | even = ptr; | |
1201 | odd = tmp; | |
1202 | UASM_i_LWX(p, even, scratch, tmp); | |
1203 | UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); | |
1204 | UASM_i_LWX(p, odd, scratch, tmp); | |
1205 | } else { | |
1206 | UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ | |
1207 | even = tmp; | |
1208 | odd = ptr; | |
1209 | UASM_i_LW(p, even, 0, ptr); /* get even pte */ | |
1210 | UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ | |
1211 | } | |
05857c64 | 1212 | if (cpu_has_rixi) { |
748e787e | 1213 | uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); |
2c8c53e2 | 1214 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ |
748e787e | 1215 | uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); |
2c8c53e2 DD |
1216 | } else { |
1217 | uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); | |
1218 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ | |
1219 | uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); | |
1220 | } | |
1221 | UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ | |
1222 | ||
7777b939 J |
1223 | if (c0_scratch_reg >= 0) { |
1224 | UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1225 | build_tlb_write_entry(p, l, r, tlb_random); |
1226 | uasm_l_leave(l, *p); | |
1227 | rv.restore_scratch = 1; | |
1228 | } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { | |
1229 | build_tlb_write_entry(p, l, r, tlb_random); | |
1230 | uasm_l_leave(l, *p); | |
1231 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); | |
1232 | } else { | |
1233 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); | |
1234 | build_tlb_write_entry(p, l, r, tlb_random); | |
1235 | uasm_l_leave(l, *p); | |
1236 | rv.restore_scratch = 1; | |
1237 | } | |
1238 | ||
1239 | uasm_i_eret(p); /* return from trap */ | |
1240 | ||
1241 | return rv; | |
1242 | } | |
1243 | ||
e6f72d3a DD |
1244 | /* |
1245 | * For a 64-bit kernel, we are using the 64-bit XTLB refill exception | |
1246 | * because EXL == 0. If we wrap, we can also use the 32 instruction | |
1247 | * slots before the XTLB refill exception handler which belong to the | |
1248 | * unused TLB refill exception. | |
1249 | */ | |
1250 | #define MIPS64_REFILL_INSNS 32 | |
1251 | ||
078a55fc | 1252 | static void build_r4000_tlb_refill_handler(void) |
1da177e4 LT |
1253 | { |
1254 | u32 *p = tlb_handler; | |
e30ec452 TS |
1255 | struct uasm_label *l = labels; |
1256 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1257 | u32 *f; |
1258 | unsigned int final_len; | |
4a9040f4 RB |
1259 | struct mips_huge_tlb_info htlb_info __maybe_unused; |
1260 | enum vmalloc64_mode vmalloc_mode __maybe_unused; | |
18280eda | 1261 | |
1da177e4 LT |
1262 | memset(tlb_handler, 0, sizeof(tlb_handler)); |
1263 | memset(labels, 0, sizeof(labels)); | |
1264 | memset(relocs, 0, sizeof(relocs)); | |
1265 | memset(final_handler, 0, sizeof(final_handler)); | |
1266 | ||
18280eda | 1267 | if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { |
2c8c53e2 DD |
1268 | htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, |
1269 | scratch_reg); | |
1270 | vmalloc_mode = refill_scratch; | |
1271 | } else { | |
1272 | htlb_info.huge_pte = K0; | |
1273 | htlb_info.restore_scratch = 0; | |
9e0f162a | 1274 | htlb_info.need_reload_pte = true; |
2c8c53e2 DD |
1275 | vmalloc_mode = refill_noscratch; |
1276 | /* | |
1277 | * create the plain linear handler | |
1278 | */ | |
1279 | if (bcm1250_m3_war()) { | |
1280 | unsigned int segbits = 44; | |
1281 | ||
1282 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1283 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
1284 | uasm_i_xor(&p, K0, K0, K1); | |
1285 | uasm_i_dsrl_safe(&p, K1, K0, 62); | |
1286 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
1287 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
1288 | uasm_i_or(&p, K0, K0, K1); | |
1289 | uasm_il_bnez(&p, &r, K0, label_leave); | |
1290 | /* No need for uasm_i_nop */ | |
1291 | } | |
1da177e4 | 1292 | |
875d43e7 | 1293 | #ifdef CONFIG_64BIT |
2c8c53e2 | 1294 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
1da177e4 | 1295 | #else |
2c8c53e2 | 1296 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ |
1da177e4 LT |
1297 | #endif |
1298 | ||
aa1762f4 | 1299 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
2c8c53e2 | 1300 | build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); |
fd062c84 DD |
1301 | #endif |
1302 | ||
2c8c53e2 DD |
1303 | build_get_ptep(&p, K0, K1); |
1304 | build_update_entries(&p, K0, K1); | |
1305 | build_tlb_write_entry(&p, &l, &r, tlb_random); | |
1306 | uasm_l_leave(&l, p); | |
1307 | uasm_i_eret(&p); /* return from trap */ | |
1308 | } | |
aa1762f4 | 1309 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 1310 | uasm_l_tlb_huge_update(&l, p); |
9e0f162a DD |
1311 | if (htlb_info.need_reload_pte) |
1312 | UASM_i_LW(&p, htlb_info.huge_pte, 0, K1); | |
2c8c53e2 DD |
1313 | build_huge_update_entries(&p, htlb_info.huge_pte, K1); |
1314 | build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, | |
1315 | htlb_info.restore_scratch); | |
fd062c84 DD |
1316 | #endif |
1317 | ||
875d43e7 | 1318 | #ifdef CONFIG_64BIT |
2c8c53e2 | 1319 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); |
1da177e4 LT |
1320 | #endif |
1321 | ||
1322 | /* | |
1323 | * Overflow check: For the 64bit handler, we need at least one | |
1324 | * free instruction slot for the wrap-around branch. In worst | |
1325 | * case, if the intended insertion point is a delay slot, we | |
4b3f686d | 1326 | * need three, with the second nop'ed and the third being |
1da177e4 LT |
1327 | * unused. |
1328 | */ | |
14bd8c08 RB |
1329 | switch (boot_cpu_type()) { |
1330 | default: | |
1331 | if (sizeof(long) == 4) { | |
1332 | case CPU_LOONGSON2: | |
1333 | /* Loongson2 ebase is different than r4k, we have more space */ | |
1334 | if ((p - tlb_handler) > 64) | |
1335 | panic("TLB refill handler space exceeded"); | |
95affdda | 1336 | /* |
14bd8c08 | 1337 | * Now fold the handler in the TLB refill handler space. |
95affdda | 1338 | */ |
14bd8c08 RB |
1339 | f = final_handler; |
1340 | /* Simplest case, just copy the handler. */ | |
1341 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); | |
1342 | final_len = p - tlb_handler; | |
1343 | break; | |
1344 | } else { | |
1345 | if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) | |
1346 | || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) | |
1347 | && uasm_insn_has_bdelay(relocs, | |
1348 | tlb_handler + MIPS64_REFILL_INSNS - 3))) | |
1349 | panic("TLB refill handler space exceeded"); | |
95affdda | 1350 | /* |
14bd8c08 | 1351 | * Now fold the handler in the TLB refill handler space. |
95affdda | 1352 | */ |
14bd8c08 RB |
1353 | f = final_handler + MIPS64_REFILL_INSNS; |
1354 | if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { | |
1355 | /* Just copy the handler. */ | |
1356 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); | |
1357 | final_len = p - tlb_handler; | |
1358 | } else { | |
1359 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT | |
1360 | const enum label_id ls = label_tlb_huge_update; | |
1361 | #else | |
1362 | const enum label_id ls = label_vmalloc; | |
1363 | #endif | |
1364 | u32 *split; | |
1365 | int ov = 0; | |
1366 | int i; | |
1367 | ||
1368 | for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) | |
1369 | ; | |
1370 | BUG_ON(i == ARRAY_SIZE(labels)); | |
1371 | split = labels[i].addr; | |
1372 | ||
1373 | /* | |
1374 | * See if we have overflown one way or the other. | |
1375 | */ | |
1376 | if (split > tlb_handler + MIPS64_REFILL_INSNS || | |
1377 | split < p - MIPS64_REFILL_INSNS) | |
1378 | ov = 1; | |
1379 | ||
1380 | if (ov) { | |
1381 | /* | |
1382 | * Split two instructions before the end. One | |
1383 | * for the branch and one for the instruction | |
1384 | * in the delay slot. | |
1385 | */ | |
1386 | split = tlb_handler + MIPS64_REFILL_INSNS - 2; | |
1387 | ||
1388 | /* | |
1389 | * If the branch would fall in a delay slot, | |
1390 | * we must back up an additional instruction | |
1391 | * so that it is no longer in a delay slot. | |
1392 | */ | |
1393 | if (uasm_insn_has_bdelay(relocs, split - 1)) | |
1394 | split--; | |
1395 | } | |
1396 | /* Copy first part of the handler. */ | |
1397 | uasm_copy_handler(relocs, labels, tlb_handler, split, f); | |
1398 | f += split - tlb_handler; | |
1399 | ||
1400 | if (ov) { | |
1401 | /* Insert branch. */ | |
1402 | uasm_l_split(&l, final_handler); | |
1403 | uasm_il_b(&f, &r, label_split); | |
1404 | if (uasm_insn_has_bdelay(relocs, split)) | |
1405 | uasm_i_nop(&f); | |
1406 | else { | |
1407 | uasm_copy_handler(relocs, labels, | |
1408 | split, split + 1, f); | |
1409 | uasm_move_labels(labels, f, f + 1, -1); | |
1410 | f++; | |
1411 | split++; | |
1412 | } | |
1413 | } | |
1414 | ||
1415 | /* Copy the rest of the handler. */ | |
1416 | uasm_copy_handler(relocs, labels, split, p, final_handler); | |
1417 | final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + | |
1418 | (p - split); | |
95affdda | 1419 | } |
1da177e4 | 1420 | } |
14bd8c08 | 1421 | break; |
1da177e4 | 1422 | } |
1da177e4 | 1423 | |
e30ec452 TS |
1424 | uasm_resolve_relocs(relocs, labels); |
1425 | pr_debug("Wrote TLB refill handler (%u instructions).\n", | |
1426 | final_len); | |
1da177e4 | 1427 | |
91b05e67 | 1428 | memcpy((void *)ebase, final_handler, 0x100); |
1062080a | 1429 | local_flush_icache_range(ebase, ebase + 0x100); |
92b1e6a6 | 1430 | |
a2c763e0 | 1431 | dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); |
1da177e4 LT |
1432 | } |
1433 | ||
380cd582 HC |
1434 | static void setup_pw(void) |
1435 | { | |
1436 | unsigned long pgd_i, pgd_w; | |
1437 | #ifndef __PAGETABLE_PMD_FOLDED | |
1438 | unsigned long pmd_i, pmd_w; | |
1439 | #endif | |
1440 | unsigned long pt_i, pt_w; | |
1441 | unsigned long pte_i, pte_w; | |
1442 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT | |
1443 | unsigned long psn; | |
1444 | ||
1445 | psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */ | |
1446 | #endif | |
1447 | pgd_i = PGDIR_SHIFT; /* 1st level PGD */ | |
1448 | #ifndef __PAGETABLE_PMD_FOLDED | |
1449 | pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER; | |
1450 | ||
1451 | pmd_i = PMD_SHIFT; /* 2nd level PMD */ | |
1452 | pmd_w = PMD_SHIFT - PAGE_SHIFT; | |
1453 | #else | |
1454 | pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER; | |
1455 | #endif | |
1456 | ||
1457 | pt_i = PAGE_SHIFT; /* 3rd level PTE */ | |
1458 | pt_w = PAGE_SHIFT - 3; | |
1459 | ||
1460 | pte_i = ilog2(_PAGE_GLOBAL); | |
1461 | pte_w = 0; | |
1462 | ||
1463 | #ifndef __PAGETABLE_PMD_FOLDED | |
1464 | write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i); | |
1465 | write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w); | |
1466 | #else | |
1467 | write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i); | |
1468 | write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w); | |
1469 | #endif | |
1470 | ||
1471 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT | |
1472 | write_c0_pwctl(1 << 6 | psn); | |
1473 | #endif | |
1474 | write_c0_kpgd(swapper_pg_dir); | |
1475 | kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */ | |
1476 | } | |
1477 | ||
1478 | static void build_loongson3_tlb_refill_handler(void) | |
1479 | { | |
1480 | u32 *p = tlb_handler; | |
1481 | struct uasm_label *l = labels; | |
1482 | struct uasm_reloc *r = relocs; | |
1483 | ||
1484 | memset(labels, 0, sizeof(labels)); | |
1485 | memset(relocs, 0, sizeof(relocs)); | |
1486 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
1487 | ||
1488 | if (check_for_high_segbits) { | |
1489 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1490 | uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
1491 | uasm_il_beqz(&p, &r, K1, label_vmalloc); | |
1492 | uasm_i_nop(&p); | |
1493 | ||
1494 | uasm_il_bgez(&p, &r, K0, label_large_segbits_fault); | |
1495 | uasm_i_nop(&p); | |
1496 | uasm_l_vmalloc(&l, p); | |
1497 | } | |
1498 | ||
1499 | uasm_i_dmfc0(&p, K1, C0_PGD); | |
1500 | ||
1501 | uasm_i_lddir(&p, K0, K1, 3); /* global page dir */ | |
1502 | #ifndef __PAGETABLE_PMD_FOLDED | |
1503 | uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */ | |
1504 | #endif | |
1505 | uasm_i_ldpte(&p, K1, 0); /* even */ | |
1506 | uasm_i_ldpte(&p, K1, 1); /* odd */ | |
1507 | uasm_i_tlbwr(&p); | |
1508 | ||
1509 | /* restore page mask */ | |
1510 | if (PM_DEFAULT_MASK >> 16) { | |
1511 | uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16); | |
1512 | uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff); | |
1513 | uasm_i_mtc0(&p, K0, C0_PAGEMASK); | |
1514 | } else if (PM_DEFAULT_MASK) { | |
1515 | uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK); | |
1516 | uasm_i_mtc0(&p, K0, C0_PAGEMASK); | |
1517 | } else { | |
1518 | uasm_i_mtc0(&p, 0, C0_PAGEMASK); | |
1519 | } | |
1520 | ||
1521 | uasm_i_eret(&p); | |
1522 | ||
1523 | if (check_for_high_segbits) { | |
1524 | uasm_l_large_segbits_fault(&l, p); | |
1525 | UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0); | |
1526 | uasm_i_jr(&p, K1); | |
1527 | uasm_i_nop(&p); | |
1528 | } | |
1529 | ||
1530 | uasm_resolve_relocs(relocs, labels); | |
1531 | memcpy((void *)(ebase + 0x80), tlb_handler, 0x80); | |
1532 | local_flush_icache_range(ebase + 0x80, ebase + 0x100); | |
1533 | dump_handler("loongson3_tlb_refill", (u32 *)(ebase + 0x80), 32); | |
1534 | } | |
1535 | ||
6ba045f9 J |
1536 | extern u32 handle_tlbl[], handle_tlbl_end[]; |
1537 | extern u32 handle_tlbs[], handle_tlbs_end[]; | |
1538 | extern u32 handle_tlbm[], handle_tlbm_end[]; | |
ccf01516 JH |
1539 | extern u32 tlbmiss_handler_setup_pgd_start[]; |
1540 | extern u32 tlbmiss_handler_setup_pgd[]; | |
1541 | EXPORT_SYMBOL_GPL(tlbmiss_handler_setup_pgd); | |
7bb39409 | 1542 | extern u32 tlbmiss_handler_setup_pgd_end[]; |
3d8bfdd0 | 1543 | |
f4ae17aa | 1544 | static void build_setup_pgd(void) |
3d8bfdd0 DD |
1545 | { |
1546 | const int a0 = 4; | |
f4ae17aa J |
1547 | const int __maybe_unused a1 = 5; |
1548 | const int __maybe_unused a2 = 6; | |
7bb39409 | 1549 | u32 *p = tlbmiss_handler_setup_pgd_start; |
6ba045f9 | 1550 | const int tlbmiss_handler_setup_pgd_size = |
7bb39409 | 1551 | tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start; |
f4ae17aa J |
1552 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1553 | long pgdc = (long)pgd_current; | |
1554 | #endif | |
3d8bfdd0 | 1555 | |
6ba045f9 J |
1556 | memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * |
1557 | sizeof(tlbmiss_handler_setup_pgd[0])); | |
3d8bfdd0 DD |
1558 | memset(labels, 0, sizeof(labels)); |
1559 | memset(relocs, 0, sizeof(relocs)); | |
3d8bfdd0 | 1560 | pgd_reg = allocate_kscratch(); |
f4ae17aa | 1561 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 | 1562 | if (pgd_reg == -1) { |
f4ae17aa J |
1563 | struct uasm_label *l = labels; |
1564 | struct uasm_reloc *r = relocs; | |
1565 | ||
3d8bfdd0 DD |
1566 | /* PGD << 11 in c0_Context */ |
1567 | /* | |
1568 | * If it is a ckseg0 address, convert to a physical | |
1569 | * address. Shifting right by 29 and adding 4 will | |
1570 | * result in zero for these addresses. | |
1571 | * | |
1572 | */ | |
1573 | UASM_i_SRA(&p, a1, a0, 29); | |
1574 | UASM_i_ADDIU(&p, a1, a1, 4); | |
1575 | uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); | |
1576 | uasm_i_nop(&p); | |
1577 | uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); | |
1578 | uasm_l_tlbl_goaround1(&l, p); | |
1579 | UASM_i_SLL(&p, a0, a0, 11); | |
1580 | uasm_i_jr(&p, 31); | |
1581 | UASM_i_MTC0(&p, a0, C0_CONTEXT); | |
1582 | } else { | |
1583 | /* PGD in c0_KScratch */ | |
1584 | uasm_i_jr(&p, 31); | |
380cd582 HC |
1585 | if (cpu_has_ldpte) |
1586 | UASM_i_MTC0(&p, a0, C0_PWBASE); | |
1587 | else | |
1588 | UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); | |
3d8bfdd0 | 1589 | } |
f4ae17aa J |
1590 | #else |
1591 | #ifdef CONFIG_SMP | |
1592 | /* Save PGD to pgd_current[smp_processor_id()] */ | |
1593 | UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); | |
1594 | UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); | |
1595 | UASM_i_LA_mostly(&p, a2, pgdc); | |
1596 | UASM_i_ADDU(&p, a2, a2, a1); | |
1597 | UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); | |
1598 | #else | |
1599 | UASM_i_LA_mostly(&p, a2, pgdc); | |
1600 | UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); | |
1601 | #endif /* SMP */ | |
1602 | uasm_i_jr(&p, 31); | |
1603 | ||
1604 | /* if pgd_reg is allocated, save PGD also to scratch register */ | |
1605 | if (pgd_reg != -1) | |
1606 | UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); | |
1607 | else | |
1608 | uasm_i_nop(&p); | |
1609 | #endif | |
6ba045f9 J |
1610 | if (p >= tlbmiss_handler_setup_pgd_end) |
1611 | panic("tlbmiss_handler_setup_pgd space exceeded"); | |
1612 | ||
3d8bfdd0 | 1613 | uasm_resolve_relocs(relocs, labels); |
6ba045f9 J |
1614 | pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", |
1615 | (unsigned int)(p - tlbmiss_handler_setup_pgd)); | |
3d8bfdd0 | 1616 | |
6ba045f9 J |
1617 | dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, |
1618 | tlbmiss_handler_setup_pgd_size); | |
3d8bfdd0 | 1619 | } |
1da177e4 | 1620 | |
078a55fc | 1621 | static void |
bd1437e4 | 1622 | iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
1623 | { |
1624 | #ifdef CONFIG_SMP | |
34adb28d | 1625 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1626 | if (cpu_has_64bits) |
e30ec452 | 1627 | uasm_i_lld(p, pte, 0, ptr); |
1da177e4 LT |
1628 | else |
1629 | # endif | |
e30ec452 | 1630 | UASM_i_LL(p, pte, 0, ptr); |
1da177e4 | 1631 | #else |
34adb28d | 1632 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1633 | if (cpu_has_64bits) |
e30ec452 | 1634 | uasm_i_ld(p, pte, 0, ptr); |
1da177e4 LT |
1635 | else |
1636 | # endif | |
e30ec452 | 1637 | UASM_i_LW(p, pte, 0, ptr); |
1da177e4 LT |
1638 | #endif |
1639 | } | |
1640 | ||
078a55fc | 1641 | static void |
e30ec452 | 1642 | iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, |
bbeeffec | 1643 | unsigned int mode, unsigned int scratch) |
1da177e4 | 1644 | { |
63b2d2f4 | 1645 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); |
b4ebbb87 | 1646 | unsigned int swmode = mode & ~hwmode; |
63b2d2f4 | 1647 | |
97f2645f | 1648 | if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) { |
b4ebbb87 | 1649 | uasm_i_lui(p, scratch, swmode >> 16); |
c5b36783 | 1650 | uasm_i_or(p, pte, pte, scratch); |
b4ebbb87 PB |
1651 | BUG_ON(swmode & 0xffff); |
1652 | } else { | |
1653 | uasm_i_ori(p, pte, pte, mode); | |
1654 | } | |
1655 | ||
1da177e4 | 1656 | #ifdef CONFIG_SMP |
34adb28d | 1657 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1658 | if (cpu_has_64bits) |
e30ec452 | 1659 | uasm_i_scd(p, pte, 0, ptr); |
1da177e4 LT |
1660 | else |
1661 | # endif | |
e30ec452 | 1662 | UASM_i_SC(p, pte, 0, ptr); |
1da177e4 LT |
1663 | |
1664 | if (r10000_llsc_war()) | |
e30ec452 | 1665 | uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 1666 | else |
e30ec452 | 1667 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 1668 | |
34adb28d | 1669 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1670 | if (!cpu_has_64bits) { |
e30ec452 TS |
1671 | /* no uasm_i_nop needed */ |
1672 | uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
1673 | uasm_i_ori(p, pte, pte, hwmode); | |
b4ebbb87 | 1674 | BUG_ON(hwmode & ~0xffff); |
e30ec452 TS |
1675 | uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); |
1676 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); | |
1677 | /* no uasm_i_nop needed */ | |
1678 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 | 1679 | } else |
e30ec452 | 1680 | uasm_i_nop(p); |
1da177e4 | 1681 | # else |
e30ec452 | 1682 | uasm_i_nop(p); |
1da177e4 LT |
1683 | # endif |
1684 | #else | |
34adb28d | 1685 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1686 | if (cpu_has_64bits) |
e30ec452 | 1687 | uasm_i_sd(p, pte, 0, ptr); |
1da177e4 LT |
1688 | else |
1689 | # endif | |
e30ec452 | 1690 | UASM_i_SW(p, pte, 0, ptr); |
1da177e4 | 1691 | |
34adb28d | 1692 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1693 | if (!cpu_has_64bits) { |
e30ec452 TS |
1694 | uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); |
1695 | uasm_i_ori(p, pte, pte, hwmode); | |
b4ebbb87 | 1696 | BUG_ON(hwmode & ~0xffff); |
e30ec452 TS |
1697 | uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); |
1698 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 LT |
1699 | } |
1700 | # endif | |
1701 | #endif | |
1702 | } | |
1703 | ||
1704 | /* | |
1705 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
1706 | * the page table where this PTE is located, PTE will be re-loaded | |
1707 | * with it's original value. | |
1708 | */ | |
078a55fc | 1709 | static void |
bd1437e4 | 1710 | build_pte_present(u32 **p, struct uasm_reloc **r, |
bf28607f | 1711 | int pte, int ptr, int scratch, enum label_id lid) |
1da177e4 | 1712 | { |
bf28607f | 1713 | int t = scratch >= 0 ? scratch : pte; |
8fe4908b | 1714 | int cur = pte; |
bf28607f | 1715 | |
05857c64 | 1716 | if (cpu_has_rixi) { |
cc33ae43 DD |
1717 | if (use_bbit_insns()) { |
1718 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); | |
1719 | uasm_i_nop(p); | |
1720 | } else { | |
8fe4908b JH |
1721 | if (_PAGE_PRESENT_SHIFT) { |
1722 | uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); | |
1723 | cur = t; | |
1724 | } | |
1725 | uasm_i_andi(p, t, cur, 1); | |
bf28607f DD |
1726 | uasm_il_beqz(p, r, t, lid); |
1727 | if (pte == t) | |
1728 | /* You lose the SMP race :-(*/ | |
1729 | iPTE_LW(p, pte, ptr); | |
cc33ae43 | 1730 | } |
6dd9344c | 1731 | } else { |
8fe4908b JH |
1732 | if (_PAGE_PRESENT_SHIFT) { |
1733 | uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); | |
1734 | cur = t; | |
1735 | } | |
1736 | uasm_i_andi(p, t, cur, | |
780602d7 PB |
1737 | (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT); |
1738 | uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT); | |
bf28607f DD |
1739 | uasm_il_bnez(p, r, t, lid); |
1740 | if (pte == t) | |
1741 | /* You lose the SMP race :-(*/ | |
1742 | iPTE_LW(p, pte, ptr); | |
6dd9344c | 1743 | } |
1da177e4 LT |
1744 | } |
1745 | ||
1746 | /* Make PTE valid, store result in PTR. */ | |
078a55fc | 1747 | static void |
e30ec452 | 1748 | build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, |
bbeeffec | 1749 | unsigned int ptr, unsigned int scratch) |
1da177e4 | 1750 | { |
63b2d2f4 TS |
1751 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
1752 | ||
bbeeffec | 1753 | iPTE_SW(p, r, pte, ptr, mode, scratch); |
1da177e4 LT |
1754 | } |
1755 | ||
1756 | /* | |
1757 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
1758 | * restore PTE with value from PTR when done. | |
1759 | */ | |
078a55fc | 1760 | static void |
bd1437e4 | 1761 | build_pte_writable(u32 **p, struct uasm_reloc **r, |
bf28607f DD |
1762 | unsigned int pte, unsigned int ptr, int scratch, |
1763 | enum label_id lid) | |
1da177e4 | 1764 | { |
bf28607f | 1765 | int t = scratch >= 0 ? scratch : pte; |
8fe4908b | 1766 | int cur = pte; |
bf28607f | 1767 | |
8fe4908b JH |
1768 | if (_PAGE_PRESENT_SHIFT) { |
1769 | uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); | |
1770 | cur = t; | |
1771 | } | |
1772 | uasm_i_andi(p, t, cur, | |
a3ae565a JH |
1773 | (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); |
1774 | uasm_i_xori(p, t, t, | |
1775 | (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); | |
bf28607f DD |
1776 | uasm_il_bnez(p, r, t, lid); |
1777 | if (pte == t) | |
1778 | /* You lose the SMP race :-(*/ | |
cc33ae43 | 1779 | iPTE_LW(p, pte, ptr); |
bf28607f DD |
1780 | else |
1781 | uasm_i_nop(p); | |
1da177e4 LT |
1782 | } |
1783 | ||
1784 | /* Make PTE writable, update software status bits as well, then store | |
1785 | * at PTR. | |
1786 | */ | |
078a55fc | 1787 | static void |
e30ec452 | 1788 | build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, |
bbeeffec | 1789 | unsigned int ptr, unsigned int scratch) |
1da177e4 | 1790 | { |
63b2d2f4 TS |
1791 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
1792 | | _PAGE_DIRTY); | |
1793 | ||
bbeeffec | 1794 | iPTE_SW(p, r, pte, ptr, mode, scratch); |
1da177e4 LT |
1795 | } |
1796 | ||
1797 | /* | |
1798 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
1799 | * restore PTE with value from PTR when done. | |
1800 | */ | |
078a55fc | 1801 | static void |
bd1437e4 | 1802 | build_pte_modifiable(u32 **p, struct uasm_reloc **r, |
bf28607f DD |
1803 | unsigned int pte, unsigned int ptr, int scratch, |
1804 | enum label_id lid) | |
1da177e4 | 1805 | { |
cc33ae43 DD |
1806 | if (use_bbit_insns()) { |
1807 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); | |
1808 | uasm_i_nop(p); | |
1809 | } else { | |
bf28607f | 1810 | int t = scratch >= 0 ? scratch : pte; |
c5b36783 SH |
1811 | uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT); |
1812 | uasm_i_andi(p, t, t, 1); | |
bf28607f DD |
1813 | uasm_il_beqz(p, r, t, lid); |
1814 | if (pte == t) | |
1815 | /* You lose the SMP race :-(*/ | |
1816 | iPTE_LW(p, pte, ptr); | |
cc33ae43 | 1817 | } |
1da177e4 LT |
1818 | } |
1819 | ||
82622284 | 1820 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 DD |
1821 | |
1822 | ||
1da177e4 LT |
1823 | /* |
1824 | * R3000 style TLB load/store/modify handlers. | |
1825 | */ | |
1826 | ||
fded2e50 MR |
1827 | /* |
1828 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
1829 | * Then it returns. | |
1830 | */ | |
078a55fc | 1831 | static void |
fded2e50 | 1832 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 1833 | { |
e30ec452 TS |
1834 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1835 | uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
1836 | uasm_i_tlbwi(p); | |
1837 | uasm_i_jr(p, tmp); | |
1838 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1839 | } |
1840 | ||
1841 | /* | |
fded2e50 MR |
1842 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
1843 | * or tlbwr as appropriate. This is because the index register | |
1844 | * may have the probe fail bit set as a result of a trap on a | |
1845 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 | 1846 | */ |
078a55fc | 1847 | static void |
e30ec452 TS |
1848 | build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, |
1849 | struct uasm_reloc **r, unsigned int pte, | |
1850 | unsigned int tmp) | |
1851 | { | |
1852 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1853 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ | |
1854 | uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
1855 | uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
1856 | uasm_i_tlbwi(p); /* cp0 delay */ | |
1857 | uasm_i_jr(p, tmp); | |
1858 | uasm_i_rfe(p); /* branch delay */ | |
1859 | uasm_l_r3000_write_probe_fail(l, *p); | |
1860 | uasm_i_tlbwr(p); /* cp0 delay */ | |
1861 | uasm_i_jr(p, tmp); | |
1862 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1863 | } |
1864 | ||
078a55fc | 1865 | static void |
1da177e4 LT |
1866 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, |
1867 | unsigned int ptr) | |
1868 | { | |
1869 | long pgdc = (long)pgd_current; | |
1870 | ||
e30ec452 TS |
1871 | uasm_i_mfc0(p, pte, C0_BADVADDR); |
1872 | uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
1873 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1874 | uasm_i_srl(p, pte, pte, 22); /* load delay */ | |
1875 | uasm_i_sll(p, pte, pte, 2); | |
1876 | uasm_i_addu(p, ptr, ptr, pte); | |
1877 | uasm_i_mfc0(p, pte, C0_CONTEXT); | |
1878 | uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
1879 | uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ | |
1880 | uasm_i_addu(p, ptr, ptr, pte); | |
1881 | uasm_i_lw(p, pte, 0, ptr); | |
1882 | uasm_i_tlbp(p); /* load delay */ | |
1da177e4 LT |
1883 | } |
1884 | ||
078a55fc | 1885 | static void build_r3000_tlb_load_handler(void) |
1da177e4 LT |
1886 | { |
1887 | u32 *p = handle_tlbl; | |
6ba045f9 | 1888 | const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; |
e30ec452 TS |
1889 | struct uasm_label *l = labels; |
1890 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1891 | |
6ba045f9 | 1892 | memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); |
1da177e4 LT |
1893 | memset(labels, 0, sizeof(labels)); |
1894 | memset(relocs, 0, sizeof(relocs)); | |
1895 | ||
1896 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bf28607f | 1897 | build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); |
e30ec452 | 1898 | uasm_i_nop(&p); /* load delay */ |
bbeeffec | 1899 | build_make_valid(&p, &r, K0, K1, -1); |
fded2e50 | 1900 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1901 | |
e30ec452 TS |
1902 | uasm_l_nopage_tlbl(&l, p); |
1903 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1904 | uasm_i_nop(&p); | |
1da177e4 | 1905 | |
6ba045f9 | 1906 | if (p >= handle_tlbl_end) |
1da177e4 LT |
1907 | panic("TLB load handler fastpath space exceeded"); |
1908 | ||
e30ec452 TS |
1909 | uasm_resolve_relocs(relocs, labels); |
1910 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1911 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1912 | |
6ba045f9 | 1913 | dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size); |
1da177e4 LT |
1914 | } |
1915 | ||
078a55fc | 1916 | static void build_r3000_tlb_store_handler(void) |
1da177e4 LT |
1917 | { |
1918 | u32 *p = handle_tlbs; | |
6ba045f9 | 1919 | const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; |
e30ec452 TS |
1920 | struct uasm_label *l = labels; |
1921 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1922 | |
6ba045f9 | 1923 | memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); |
1da177e4 LT |
1924 | memset(labels, 0, sizeof(labels)); |
1925 | memset(relocs, 0, sizeof(relocs)); | |
1926 | ||
1927 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bf28607f | 1928 | build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); |
e30ec452 | 1929 | uasm_i_nop(&p); /* load delay */ |
bbeeffec | 1930 | build_make_write(&p, &r, K0, K1, -1); |
fded2e50 | 1931 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1932 | |
e30ec452 TS |
1933 | uasm_l_nopage_tlbs(&l, p); |
1934 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1935 | uasm_i_nop(&p); | |
1da177e4 | 1936 | |
afc813ae | 1937 | if (p >= handle_tlbs_end) |
1da177e4 LT |
1938 | panic("TLB store handler fastpath space exceeded"); |
1939 | ||
e30ec452 TS |
1940 | uasm_resolve_relocs(relocs, labels); |
1941 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1942 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1943 | |
6ba045f9 | 1944 | dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size); |
1da177e4 LT |
1945 | } |
1946 | ||
078a55fc | 1947 | static void build_r3000_tlb_modify_handler(void) |
1da177e4 LT |
1948 | { |
1949 | u32 *p = handle_tlbm; | |
6ba045f9 | 1950 | const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; |
e30ec452 TS |
1951 | struct uasm_label *l = labels; |
1952 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1953 | |
6ba045f9 | 1954 | memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); |
1da177e4 LT |
1955 | memset(labels, 0, sizeof(labels)); |
1956 | memset(relocs, 0, sizeof(relocs)); | |
1957 | ||
1958 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
d954ffe3 | 1959 | build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); |
e30ec452 | 1960 | uasm_i_nop(&p); /* load delay */ |
bbeeffec | 1961 | build_make_write(&p, &r, K0, K1, -1); |
fded2e50 | 1962 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
1da177e4 | 1963 | |
e30ec452 TS |
1964 | uasm_l_nopage_tlbm(&l, p); |
1965 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1966 | uasm_i_nop(&p); | |
1da177e4 | 1967 | |
6ba045f9 | 1968 | if (p >= handle_tlbm_end) |
1da177e4 LT |
1969 | panic("TLB modify handler fastpath space exceeded"); |
1970 | ||
e30ec452 TS |
1971 | uasm_resolve_relocs(relocs, labels); |
1972 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1973 | (unsigned int)(p - handle_tlbm)); | |
1da177e4 | 1974 | |
6ba045f9 | 1975 | dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size); |
1da177e4 | 1976 | } |
82622284 | 1977 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
1978 | |
1979 | /* | |
1980 | * R4000 style TLB load/store/modify handlers. | |
1981 | */ | |
078a55fc | 1982 | static struct work_registers |
e30ec452 | 1983 | build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, |
bf28607f | 1984 | struct uasm_reloc **r) |
1da177e4 | 1985 | { |
bf28607f DD |
1986 | struct work_registers wr = build_get_work_registers(p); |
1987 | ||
875d43e7 | 1988 | #ifdef CONFIG_64BIT |
bf28607f | 1989 | build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ |
1da177e4 | 1990 | #else |
bf28607f | 1991 | build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ |
1da177e4 LT |
1992 | #endif |
1993 | ||
aa1762f4 | 1994 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
1995 | /* |
1996 | * For huge tlb entries, pmd doesn't contain an address but | |
1997 | * instead contains the tlb pte. Check the PAGE_HUGE bit and | |
1998 | * see if we need to jump to huge tlb processing. | |
1999 | */ | |
bf28607f | 2000 | build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); |
fd062c84 DD |
2001 | #endif |
2002 | ||
bf28607f DD |
2003 | UASM_i_MFC0(p, wr.r1, C0_BADVADDR); |
2004 | UASM_i_LW(p, wr.r2, 0, wr.r2); | |
2005 | UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); | |
2006 | uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); | |
2007 | UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); | |
1da177e4 LT |
2008 | |
2009 | #ifdef CONFIG_SMP | |
e30ec452 TS |
2010 | uasm_l_smp_pgtable_change(l, *p); |
2011 | #endif | |
bf28607f | 2012 | iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ |
070e76cb | 2013 | if (!m4kc_tlbp_war()) { |
8df5beac | 2014 | build_tlb_probe_entry(p); |
070e76cb LY |
2015 | if (cpu_has_htw) { |
2016 | /* race condition happens, leaving */ | |
2017 | uasm_i_ehb(p); | |
2018 | uasm_i_mfc0(p, wr.r3, C0_INDEX); | |
2019 | uasm_il_bltz(p, r, wr.r3, label_leave); | |
2020 | uasm_i_nop(p); | |
2021 | } | |
2022 | } | |
bf28607f | 2023 | return wr; |
1da177e4 LT |
2024 | } |
2025 | ||
078a55fc | 2026 | static void |
e30ec452 TS |
2027 | build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, |
2028 | struct uasm_reloc **r, unsigned int tmp, | |
1da177e4 LT |
2029 | unsigned int ptr) |
2030 | { | |
e30ec452 TS |
2031 | uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); |
2032 | uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1da177e4 LT |
2033 | build_update_entries(p, tmp, ptr); |
2034 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
e30ec452 | 2035 | uasm_l_leave(l, *p); |
bf28607f | 2036 | build_restore_work_registers(p); |
e30ec452 | 2037 | uasm_i_eret(p); /* return from trap */ |
1da177e4 | 2038 | |
875d43e7 | 2039 | #ifdef CONFIG_64BIT |
1ec56329 | 2040 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); |
1da177e4 LT |
2041 | #endif |
2042 | } | |
2043 | ||
078a55fc | 2044 | static void build_r4000_tlb_load_handler(void) |
1da177e4 | 2045 | { |
2c0e57ea | 2046 | u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl); |
6ba045f9 | 2047 | const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; |
e30ec452 TS |
2048 | struct uasm_label *l = labels; |
2049 | struct uasm_reloc *r = relocs; | |
bf28607f | 2050 | struct work_registers wr; |
1da177e4 | 2051 | |
6ba045f9 | 2052 | memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); |
1da177e4 LT |
2053 | memset(labels, 0, sizeof(labels)); |
2054 | memset(relocs, 0, sizeof(relocs)); | |
2055 | ||
2056 | if (bcm1250_m3_war()) { | |
3d45285d RB |
2057 | unsigned int segbits = 44; |
2058 | ||
2059 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
2060 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
e30ec452 | 2061 | uasm_i_xor(&p, K0, K0, K1); |
3be6022c DD |
2062 | uasm_i_dsrl_safe(&p, K1, K0, 62); |
2063 | uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); | |
2064 | uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); | |
3d45285d | 2065 | uasm_i_or(&p, K0, K0, K1); |
e30ec452 TS |
2066 | uasm_il_bnez(&p, &r, K0, label_leave); |
2067 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
2068 | } |
2069 | ||
bf28607f DD |
2070 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2071 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); | |
8df5beac MR |
2072 | if (m4kc_tlbp_war()) |
2073 | build_tlb_probe_entry(&p); | |
6dd9344c | 2074 | |
5890f70f | 2075 | if (cpu_has_rixi && !cpu_has_rixiex) { |
6dd9344c DD |
2076 | /* |
2077 | * If the page is not _PAGE_VALID, RI or XI could not | |
2078 | * have triggered it. Skip the expensive test.. | |
2079 | */ | |
cc33ae43 | 2080 | if (use_bbit_insns()) { |
bf28607f | 2081 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
cc33ae43 DD |
2082 | label_tlbl_goaround1); |
2083 | } else { | |
bf28607f DD |
2084 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
2085 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); | |
cc33ae43 | 2086 | } |
6dd9344c DD |
2087 | uasm_i_nop(&p); |
2088 | ||
2089 | uasm_i_tlbr(&p); | |
73acc7df RB |
2090 | |
2091 | switch (current_cpu_type()) { | |
2092 | default: | |
77f3ee59 | 2093 | if (cpu_has_mips_r2_exec_hazard) { |
73acc7df RB |
2094 | uasm_i_ehb(&p); |
2095 | ||
2096 | case CPU_CAVIUM_OCTEON: | |
2097 | case CPU_CAVIUM_OCTEON_PLUS: | |
2098 | case CPU_CAVIUM_OCTEON2: | |
2099 | break; | |
2100 | } | |
2101 | } | |
2102 | ||
6dd9344c | 2103 | /* Examine entrylo 0 or 1 based on ptr. */ |
cc33ae43 | 2104 | if (use_bbit_insns()) { |
bf28607f | 2105 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
cc33ae43 | 2106 | } else { |
bf28607f DD |
2107 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
2108 | uasm_i_beqz(&p, wr.r3, 8); | |
cc33ae43 | 2109 | } |
bf28607f DD |
2110 | /* load it in the delay slot*/ |
2111 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); | |
2112 | /* load it if ptr is odd */ | |
2113 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); | |
6dd9344c | 2114 | /* |
bf28607f | 2115 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
6dd9344c DD |
2116 | * XI must have triggered it. |
2117 | */ | |
cc33ae43 | 2118 | if (use_bbit_insns()) { |
bf28607f DD |
2119 | uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); |
2120 | uasm_i_nop(&p); | |
cc33ae43 DD |
2121 | uasm_l_tlbl_goaround1(&l, p); |
2122 | } else { | |
bf28607f DD |
2123 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
2124 | uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); | |
2125 | uasm_i_nop(&p); | |
cc33ae43 | 2126 | } |
bf28607f | 2127 | uasm_l_tlbl_goaround1(&l, p); |
6dd9344c | 2128 | } |
bbeeffec | 2129 | build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3); |
bf28607f | 2130 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); |
1da177e4 | 2131 | |
aa1762f4 | 2132 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2133 | /* |
2134 | * This is the entry point when build_r4000_tlbchange_handler_head | |
2135 | * spots a huge page. | |
2136 | */ | |
2137 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2138 | iPTE_LW(&p, wr.r1, wr.r2); |
2139 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); | |
fd062c84 | 2140 | build_tlb_probe_entry(&p); |
6dd9344c | 2141 | |
5890f70f | 2142 | if (cpu_has_rixi && !cpu_has_rixiex) { |
6dd9344c DD |
2143 | /* |
2144 | * If the page is not _PAGE_VALID, RI or XI could not | |
2145 | * have triggered it. Skip the expensive test.. | |
2146 | */ | |
cc33ae43 | 2147 | if (use_bbit_insns()) { |
bf28607f | 2148 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
cc33ae43 DD |
2149 | label_tlbl_goaround2); |
2150 | } else { | |
bf28607f DD |
2151 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
2152 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); | |
cc33ae43 | 2153 | } |
6dd9344c DD |
2154 | uasm_i_nop(&p); |
2155 | ||
2156 | uasm_i_tlbr(&p); | |
73acc7df RB |
2157 | |
2158 | switch (current_cpu_type()) { | |
2159 | default: | |
77f3ee59 | 2160 | if (cpu_has_mips_r2_exec_hazard) { |
73acc7df RB |
2161 | uasm_i_ehb(&p); |
2162 | ||
2163 | case CPU_CAVIUM_OCTEON: | |
2164 | case CPU_CAVIUM_OCTEON_PLUS: | |
2165 | case CPU_CAVIUM_OCTEON2: | |
2166 | break; | |
2167 | } | |
2168 | } | |
2169 | ||
6dd9344c | 2170 | /* Examine entrylo 0 or 1 based on ptr. */ |
cc33ae43 | 2171 | if (use_bbit_insns()) { |
bf28607f | 2172 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
cc33ae43 | 2173 | } else { |
bf28607f DD |
2174 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
2175 | uasm_i_beqz(&p, wr.r3, 8); | |
cc33ae43 | 2176 | } |
bf28607f DD |
2177 | /* load it in the delay slot*/ |
2178 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); | |
2179 | /* load it if ptr is odd */ | |
2180 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); | |
6dd9344c | 2181 | /* |
bf28607f | 2182 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
6dd9344c DD |
2183 | * XI must have triggered it. |
2184 | */ | |
cc33ae43 | 2185 | if (use_bbit_insns()) { |
bf28607f | 2186 | uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); |
cc33ae43 | 2187 | } else { |
bf28607f DD |
2188 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
2189 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); | |
cc33ae43 | 2190 | } |
0f4ccbc8 DD |
2191 | if (PM_DEFAULT_MASK == 0) |
2192 | uasm_i_nop(&p); | |
6dd9344c DD |
2193 | /* |
2194 | * We clobbered C0_PAGEMASK, restore it. On the other branch | |
2195 | * it is restored in build_huge_tlb_write_entry. | |
2196 | */ | |
bf28607f | 2197 | build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); |
6dd9344c DD |
2198 | |
2199 | uasm_l_tlbl_goaround2(&l, p); | |
2200 | } | |
bf28607f DD |
2201 | uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); |
2202 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); | |
fd062c84 DD |
2203 | #endif |
2204 | ||
e30ec452 | 2205 | uasm_l_nopage_tlbl(&l, p); |
bf28607f | 2206 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2207 | #ifdef CONFIG_CPU_MICROMIPS |
2208 | if ((unsigned long)tlb_do_page_fault_0 & 1) { | |
2209 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); | |
2210 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); | |
2211 | uasm_i_jr(&p, K0); | |
2212 | } else | |
2213 | #endif | |
e30ec452 TS |
2214 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); |
2215 | uasm_i_nop(&p); | |
1da177e4 | 2216 | |
6ba045f9 | 2217 | if (p >= handle_tlbl_end) |
1da177e4 LT |
2218 | panic("TLB load handler fastpath space exceeded"); |
2219 | ||
e30ec452 TS |
2220 | uasm_resolve_relocs(relocs, labels); |
2221 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
2222 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 2223 | |
6ba045f9 | 2224 | dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size); |
1da177e4 LT |
2225 | } |
2226 | ||
078a55fc | 2227 | static void build_r4000_tlb_store_handler(void) |
1da177e4 | 2228 | { |
2c0e57ea | 2229 | u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs); |
6ba045f9 | 2230 | const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; |
e30ec452 TS |
2231 | struct uasm_label *l = labels; |
2232 | struct uasm_reloc *r = relocs; | |
bf28607f | 2233 | struct work_registers wr; |
1da177e4 | 2234 | |
6ba045f9 | 2235 | memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); |
1da177e4 LT |
2236 | memset(labels, 0, sizeof(labels)); |
2237 | memset(relocs, 0, sizeof(relocs)); | |
2238 | ||
bf28607f DD |
2239 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2240 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); | |
8df5beac MR |
2241 | if (m4kc_tlbp_war()) |
2242 | build_tlb_probe_entry(&p); | |
bbeeffec | 2243 | build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); |
bf28607f | 2244 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); |
1da177e4 | 2245 | |
aa1762f4 | 2246 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2247 | /* |
2248 | * This is the entry point when | |
2249 | * build_r4000_tlbchange_handler_head spots a huge page. | |
2250 | */ | |
2251 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2252 | iPTE_LW(&p, wr.r1, wr.r2); |
2253 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); | |
fd062c84 | 2254 | build_tlb_probe_entry(&p); |
bf28607f | 2255 | uasm_i_ori(&p, wr.r1, wr.r1, |
fd062c84 | 2256 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
bf28607f | 2257 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); |
fd062c84 DD |
2258 | #endif |
2259 | ||
e30ec452 | 2260 | uasm_l_nopage_tlbs(&l, p); |
bf28607f | 2261 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2262 | #ifdef CONFIG_CPU_MICROMIPS |
2263 | if ((unsigned long)tlb_do_page_fault_1 & 1) { | |
2264 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); | |
2265 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); | |
2266 | uasm_i_jr(&p, K0); | |
2267 | } else | |
2268 | #endif | |
e30ec452 TS |
2269 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
2270 | uasm_i_nop(&p); | |
1da177e4 | 2271 | |
6ba045f9 | 2272 | if (p >= handle_tlbs_end) |
1da177e4 LT |
2273 | panic("TLB store handler fastpath space exceeded"); |
2274 | ||
e30ec452 TS |
2275 | uasm_resolve_relocs(relocs, labels); |
2276 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
2277 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 2278 | |
6ba045f9 | 2279 | dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size); |
1da177e4 LT |
2280 | } |
2281 | ||
078a55fc | 2282 | static void build_r4000_tlb_modify_handler(void) |
1da177e4 | 2283 | { |
2c0e57ea | 2284 | u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm); |
6ba045f9 | 2285 | const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; |
e30ec452 TS |
2286 | struct uasm_label *l = labels; |
2287 | struct uasm_reloc *r = relocs; | |
bf28607f | 2288 | struct work_registers wr; |
1da177e4 | 2289 | |
6ba045f9 | 2290 | memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); |
1da177e4 LT |
2291 | memset(labels, 0, sizeof(labels)); |
2292 | memset(relocs, 0, sizeof(relocs)); | |
2293 | ||
bf28607f DD |
2294 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2295 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); | |
8df5beac MR |
2296 | if (m4kc_tlbp_war()) |
2297 | build_tlb_probe_entry(&p); | |
1da177e4 | 2298 | /* Present and writable bits set, set accessed and dirty bits. */ |
bbeeffec | 2299 | build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); |
bf28607f | 2300 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); |
1da177e4 | 2301 | |
aa1762f4 | 2302 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2303 | /* |
2304 | * This is the entry point when | |
2305 | * build_r4000_tlbchange_handler_head spots a huge page. | |
2306 | */ | |
2307 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2308 | iPTE_LW(&p, wr.r1, wr.r2); |
2309 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); | |
fd062c84 | 2310 | build_tlb_probe_entry(&p); |
bf28607f | 2311 | uasm_i_ori(&p, wr.r1, wr.r1, |
fd062c84 | 2312 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
bf28607f | 2313 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); |
fd062c84 DD |
2314 | #endif |
2315 | ||
e30ec452 | 2316 | uasm_l_nopage_tlbm(&l, p); |
bf28607f | 2317 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2318 | #ifdef CONFIG_CPU_MICROMIPS |
2319 | if ((unsigned long)tlb_do_page_fault_1 & 1) { | |
2320 | uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); | |
2321 | uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); | |
2322 | uasm_i_jr(&p, K0); | |
2323 | } else | |
2324 | #endif | |
e30ec452 TS |
2325 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
2326 | uasm_i_nop(&p); | |
1da177e4 | 2327 | |
6ba045f9 | 2328 | if (p >= handle_tlbm_end) |
1da177e4 LT |
2329 | panic("TLB modify handler fastpath space exceeded"); |
2330 | ||
e30ec452 TS |
2331 | uasm_resolve_relocs(relocs, labels); |
2332 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
2333 | (unsigned int)(p - handle_tlbm)); | |
115f2a44 | 2334 | |
6ba045f9 | 2335 | dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size); |
1da177e4 LT |
2336 | } |
2337 | ||
078a55fc | 2338 | static void flush_tlb_handlers(void) |
a3d9086b JG |
2339 | { |
2340 | local_flush_icache_range((unsigned long)handle_tlbl, | |
6ac5310e | 2341 | (unsigned long)handle_tlbl_end); |
a3d9086b | 2342 | local_flush_icache_range((unsigned long)handle_tlbs, |
6ac5310e | 2343 | (unsigned long)handle_tlbs_end); |
a3d9086b | 2344 | local_flush_icache_range((unsigned long)handle_tlbm, |
6ac5310e | 2345 | (unsigned long)handle_tlbm_end); |
6ac5310e RB |
2346 | local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, |
2347 | (unsigned long)tlbmiss_handler_setup_pgd_end); | |
a3d9086b JG |
2348 | } |
2349 | ||
f1014d1b MC |
2350 | static void print_htw_config(void) |
2351 | { | |
2352 | unsigned long config; | |
2353 | unsigned int pwctl; | |
2354 | const int field = 2 * sizeof(unsigned long); | |
2355 | ||
2356 | config = read_c0_pwfield(); | |
2357 | pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n", | |
2358 | field, config, | |
2359 | (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT, | |
2360 | (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT, | |
2361 | (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT, | |
2362 | (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT, | |
2363 | (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); | |
2364 | ||
2365 | config = read_c0_pwsize(); | |
6446e6cf | 2366 | pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", |
f1014d1b | 2367 | field, config, |
6446e6cf | 2368 | (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT, |
f1014d1b MC |
2369 | (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, |
2370 | (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, | |
2371 | (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, | |
2372 | (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT, | |
2373 | (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); | |
2374 | ||
2375 | pwctl = read_c0_pwctl(); | |
6446e6cf | 2376 | pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", |
f1014d1b MC |
2377 | pwctl, |
2378 | (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, | |
6446e6cf JH |
2379 | (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT, |
2380 | (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT, | |
2381 | (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT, | |
f1014d1b MC |
2382 | (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, |
2383 | (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, | |
2384 | (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); | |
2385 | } | |
2386 | ||
2387 | static void config_htw_params(void) | |
2388 | { | |
2389 | unsigned long pwfield, pwsize, ptei; | |
2390 | unsigned int config; | |
2391 | ||
2392 | /* | |
2393 | * We are using 2-level page tables, so we only need to | |
2394 | * setup GDW and PTW appropriately. UDW and MDW will remain 0. | |
2395 | * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to | |
2396 | * write values less than 0xc in these fields because the entire | |
2397 | * write will be dropped. As a result of which, we must preserve | |
2398 | * the original reset values and overwrite only what we really want. | |
2399 | */ | |
2400 | ||
2401 | pwfield = read_c0_pwfield(); | |
2402 | /* re-initialize the GDI field */ | |
2403 | pwfield &= ~MIPS_PWFIELD_GDI_MASK; | |
2404 | pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT; | |
2405 | /* re-initialize the PTI field including the even/odd bit */ | |
2406 | pwfield &= ~MIPS_PWFIELD_PTI_MASK; | |
2407 | pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT; | |
cab25bc7 PB |
2408 | if (CONFIG_PGTABLE_LEVELS >= 3) { |
2409 | pwfield &= ~MIPS_PWFIELD_MDI_MASK; | |
2410 | pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT; | |
2411 | } | |
f1014d1b MC |
2412 | /* Set the PTEI right shift */ |
2413 | ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT; | |
2414 | pwfield |= ptei; | |
2415 | write_c0_pwfield(pwfield); | |
2416 | /* Check whether the PTEI value is supported */ | |
2417 | back_to_back_c0_hazard(); | |
2418 | pwfield = read_c0_pwfield(); | |
2419 | if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT) | |
2420 | != ptei) { | |
2421 | pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled", | |
2422 | ptei); | |
2423 | /* | |
2424 | * Drop option to avoid HTW being enabled via another path | |
2425 | * (eg htw_reset()) | |
2426 | */ | |
2427 | current_cpu_data.options &= ~MIPS_CPU_HTW; | |
2428 | return; | |
2429 | } | |
2430 | ||
2431 | pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; | |
2432 | pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; | |
cab25bc7 PB |
2433 | if (CONFIG_PGTABLE_LEVELS >= 3) |
2434 | pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; | |
c5b36783 | 2435 | |
aa76042a | 2436 | /* Set pointer size to size of directory pointers */ |
97f2645f | 2437 | if (IS_ENABLED(CONFIG_64BIT)) |
aa76042a JH |
2438 | pwsize |= MIPS_PWSIZE_PS_MASK; |
2439 | /* PTEs may be multiple pointers long (e.g. with XPA) */ | |
2440 | pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT) | |
2441 | & MIPS_PWSIZE_PTEW_MASK; | |
c5b36783 | 2442 | |
f1014d1b MC |
2443 | write_c0_pwsize(pwsize); |
2444 | ||
2445 | /* Make sure everything is set before we enable the HTW */ | |
2446 | back_to_back_c0_hazard(); | |
2447 | ||
aa76042a JH |
2448 | /* |
2449 | * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of | |
2450 | * the pwctl fields. | |
2451 | */ | |
f1014d1b | 2452 | config = 1 << MIPS_PWCTL_PWEN_SHIFT; |
97f2645f | 2453 | if (IS_ENABLED(CONFIG_64BIT)) |
aa76042a | 2454 | config |= MIPS_PWCTL_XU_MASK; |
f1014d1b MC |
2455 | write_c0_pwctl(config); |
2456 | pr_info("Hardware Page Table Walker enabled\n"); | |
2457 | ||
2458 | print_htw_config(); | |
2459 | } | |
2460 | ||
c5b36783 SH |
2461 | static void config_xpa_params(void) |
2462 | { | |
2463 | #ifdef CONFIG_XPA | |
2464 | unsigned int pagegrain; | |
2465 | ||
2466 | if (mips_xpa_disabled) { | |
2467 | pr_info("Extended Physical Addressing (XPA) disabled\n"); | |
2468 | return; | |
2469 | } | |
2470 | ||
2471 | pagegrain = read_c0_pagegrain(); | |
2472 | write_c0_pagegrain(pagegrain | PG_ELPA); | |
2473 | back_to_back_c0_hazard(); | |
2474 | pagegrain = read_c0_pagegrain(); | |
2475 | ||
2476 | if (pagegrain & PG_ELPA) | |
2477 | pr_info("Extended Physical Addressing (XPA) enabled\n"); | |
2478 | else | |
2479 | panic("Extended Physical Addressing (XPA) disabled"); | |
2480 | #endif | |
2481 | } | |
2482 | ||
00bf1c69 PB |
2483 | static void check_pabits(void) |
2484 | { | |
2485 | unsigned long entry; | |
2486 | unsigned pabits, fillbits; | |
2487 | ||
2488 | if (!cpu_has_rixi || !_PAGE_NO_EXEC) { | |
2489 | /* | |
2490 | * We'll only be making use of the fact that we can rotate bits | |
2491 | * into the fill if the CPU supports RIXI, so don't bother | |
2492 | * probing this for CPUs which don't. | |
2493 | */ | |
2494 | return; | |
2495 | } | |
2496 | ||
2497 | write_c0_entrylo0(~0ul); | |
2498 | back_to_back_c0_hazard(); | |
2499 | entry = read_c0_entrylo0(); | |
2500 | ||
2501 | /* clear all non-PFN bits */ | |
2502 | entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1); | |
2503 | entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); | |
2504 | ||
2505 | /* find a lower bound on PABITS, and upper bound on fill bits */ | |
2506 | pabits = fls_long(entry) + 6; | |
2507 | fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0); | |
2508 | ||
2509 | /* minus the RI & XI bits */ | |
2510 | fillbits -= min_t(unsigned, fillbits, 2); | |
2511 | ||
2512 | if (fillbits >= ilog2(_PAGE_NO_EXEC)) | |
2513 | fill_includes_sw_bits = true; | |
2514 | ||
2515 | pr_debug("Entry* registers contain %u fill bits\n", fillbits); | |
2516 | } | |
2517 | ||
078a55fc | 2518 | void build_tlb_refill_handler(void) |
1da177e4 LT |
2519 | { |
2520 | /* | |
2521 | * The refill handler is generated per-CPU, multi-node systems | |
2522 | * may have local storage for it. The other handlers are only | |
2523 | * needed once. | |
2524 | */ | |
2525 | static int run_once = 0; | |
2526 | ||
97f2645f | 2527 | if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi) |
e56c7e18 PB |
2528 | panic("Kernels supporting XPA currently require CPUs with RIXI"); |
2529 | ||
a2c763e0 | 2530 | output_pgtable_bits_defines(); |
00bf1c69 | 2531 | check_pabits(); |
a2c763e0 | 2532 | |
1ec56329 DD |
2533 | #ifdef CONFIG_64BIT |
2534 | check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); | |
2535 | #endif | |
2536 | ||
10cc3529 | 2537 | switch (current_cpu_type()) { |
1da177e4 LT |
2538 | case CPU_R2000: |
2539 | case CPU_R3000: | |
2540 | case CPU_R3000A: | |
2541 | case CPU_R3081E: | |
2542 | case CPU_TX3912: | |
2543 | case CPU_TX3922: | |
2544 | case CPU_TX3927: | |
82622284 | 2545 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
8759934e HC |
2546 | if (cpu_has_local_ebase) |
2547 | build_r3000_tlb_refill_handler(); | |
1da177e4 | 2548 | if (!run_once) { |
8759934e HC |
2549 | if (!cpu_has_local_ebase) |
2550 | build_r3000_tlb_refill_handler(); | |
f4ae17aa | 2551 | build_setup_pgd(); |
1da177e4 LT |
2552 | build_r3000_tlb_load_handler(); |
2553 | build_r3000_tlb_store_handler(); | |
2554 | build_r3000_tlb_modify_handler(); | |
a3d9086b | 2555 | flush_tlb_handlers(); |
1da177e4 LT |
2556 | run_once++; |
2557 | } | |
82622284 DD |
2558 | #else |
2559 | panic("No R3000 TLB refill handler"); | |
2560 | #endif | |
1da177e4 LT |
2561 | break; |
2562 | ||
2563 | case CPU_R6000: | |
2564 | case CPU_R6000A: | |
2565 | panic("No R6000 TLB refill handler yet"); | |
2566 | break; | |
2567 | ||
2568 | case CPU_R8000: | |
2569 | panic("No R8000 TLB refill handler yet"); | |
2570 | break; | |
2571 | ||
2572 | default: | |
380cd582 HC |
2573 | if (cpu_has_ldpte) |
2574 | setup_pw(); | |
2575 | ||
1da177e4 | 2576 | if (!run_once) { |
bf28607f | 2577 | scratch_reg = allocate_kscratch(); |
f4ae17aa | 2578 | build_setup_pgd(); |
1da177e4 LT |
2579 | build_r4000_tlb_load_handler(); |
2580 | build_r4000_tlb_store_handler(); | |
2581 | build_r4000_tlb_modify_handler(); | |
380cd582 HC |
2582 | if (cpu_has_ldpte) |
2583 | build_loongson3_tlb_refill_handler(); | |
2584 | else if (!cpu_has_local_ebase) | |
8759934e | 2585 | build_r4000_tlb_refill_handler(); |
a3d9086b | 2586 | flush_tlb_handlers(); |
1da177e4 LT |
2587 | run_once++; |
2588 | } | |
8759934e HC |
2589 | if (cpu_has_local_ebase) |
2590 | build_r4000_tlb_refill_handler(); | |
c5b36783 SH |
2591 | if (cpu_has_xpa) |
2592 | config_xpa_params(); | |
f1014d1b MC |
2593 | if (cpu_has_htw) |
2594 | config_htw_params(); | |
1da177e4 LT |
2595 | } |
2596 | } |