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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
e30ec452 | 8 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
95affdda | 9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki |
41c594ab | 10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
fd062c84 | 11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. |
41c594ab RB |
12 | * |
13 | * ... and the days got worse and worse and now you see | |
14 | * I've gone completly out of my mind. | |
15 | * | |
16 | * They're coming to take me a away haha | |
17 | * they're coming to take me a away hoho hihi haha | |
18 | * to the funny farm where code is beautiful all the time ... | |
19 | * | |
20 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
21 | */ |
22 | ||
95affdda | 23 | #include <linux/bug.h> |
1da177e4 LT |
24 | #include <linux/kernel.h> |
25 | #include <linux/types.h> | |
631330f5 | 26 | #include <linux/smp.h> |
1da177e4 LT |
27 | #include <linux/string.h> |
28 | #include <linux/init.h> | |
29 | ||
1da177e4 | 30 | #include <asm/mmu_context.h> |
1da177e4 | 31 | #include <asm/war.h> |
3482d713 | 32 | #include <asm/uasm.h> |
e30ec452 | 33 | |
aeffdbba | 34 | static inline int r45k_bvahwbug(void) |
1da177e4 LT |
35 | { |
36 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
37 | return 0; | |
38 | } | |
39 | ||
aeffdbba | 40 | static inline int r4k_250MHZhwbug(void) |
1da177e4 LT |
41 | { |
42 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
43 | return 0; | |
44 | } | |
45 | ||
aeffdbba | 46 | static inline int __maybe_unused bcm1250_m3_war(void) |
1da177e4 LT |
47 | { |
48 | return BCM1250_M3_WAR; | |
49 | } | |
50 | ||
aeffdbba | 51 | static inline int __maybe_unused r10000_llsc_war(void) |
1da177e4 LT |
52 | { |
53 | return R10000_LLSC_WAR; | |
54 | } | |
55 | ||
8df5beac MR |
56 | /* |
57 | * Found by experiment: At least some revisions of the 4kc throw under | |
58 | * some circumstances a machine check exception, triggered by invalid | |
59 | * values in the index register. Delaying the tlbp instruction until | |
60 | * after the next branch, plus adding an additional nop in front of | |
61 | * tlbwi/tlbwr avoids the invalid index register values. Nobody knows | |
62 | * why; it's not an issue caused by the core RTL. | |
63 | * | |
64 | */ | |
234fcd14 | 65 | static int __cpuinit m4kc_tlbp_war(void) |
8df5beac MR |
66 | { |
67 | return (current_cpu_data.processor_id & 0xffff00) == | |
68 | (PRID_COMP_MIPS | PRID_IMP_4KC); | |
69 | } | |
70 | ||
e30ec452 | 71 | /* Handle labels (which must be positive integers). */ |
1da177e4 | 72 | enum label_id { |
e30ec452 | 73 | label_second_part = 1, |
1da177e4 LT |
74 | label_leave, |
75 | label_vmalloc, | |
76 | label_vmalloc_done, | |
77 | label_tlbw_hazard, | |
78 | label_split, | |
6dd9344c DD |
79 | label_tlbl_goaround1, |
80 | label_tlbl_goaround2, | |
1da177e4 LT |
81 | label_nopage_tlbl, |
82 | label_nopage_tlbs, | |
83 | label_nopage_tlbm, | |
84 | label_smp_pgtable_change, | |
85 | label_r3000_write_probe_fail, | |
fd062c84 DD |
86 | #ifdef CONFIG_HUGETLB_PAGE |
87 | label_tlb_huge_update, | |
88 | #endif | |
1da177e4 LT |
89 | }; |
90 | ||
e30ec452 TS |
91 | UASM_L_LA(_second_part) |
92 | UASM_L_LA(_leave) | |
e30ec452 TS |
93 | UASM_L_LA(_vmalloc) |
94 | UASM_L_LA(_vmalloc_done) | |
95 | UASM_L_LA(_tlbw_hazard) | |
96 | UASM_L_LA(_split) | |
6dd9344c DD |
97 | UASM_L_LA(_tlbl_goaround1) |
98 | UASM_L_LA(_tlbl_goaround2) | |
e30ec452 TS |
99 | UASM_L_LA(_nopage_tlbl) |
100 | UASM_L_LA(_nopage_tlbs) | |
101 | UASM_L_LA(_nopage_tlbm) | |
102 | UASM_L_LA(_smp_pgtable_change) | |
103 | UASM_L_LA(_r3000_write_probe_fail) | |
fd062c84 DD |
104 | #ifdef CONFIG_HUGETLB_PAGE |
105 | UASM_L_LA(_tlb_huge_update) | |
106 | #endif | |
656be92f | 107 | |
92b1e6a6 FBH |
108 | /* |
109 | * For debug purposes. | |
110 | */ | |
111 | static inline void dump_handler(const u32 *handler, int count) | |
112 | { | |
113 | int i; | |
114 | ||
115 | pr_debug("\t.set push\n"); | |
116 | pr_debug("\t.set noreorder\n"); | |
117 | ||
118 | for (i = 0; i < count; i++) | |
119 | pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]); | |
120 | ||
121 | pr_debug("\t.set pop\n"); | |
122 | } | |
123 | ||
1da177e4 LT |
124 | /* The only general purpose registers allowed in TLB handlers. */ |
125 | #define K0 26 | |
126 | #define K1 27 | |
127 | ||
128 | /* Some CP0 registers */ | |
41c594ab RB |
129 | #define C0_INDEX 0, 0 |
130 | #define C0_ENTRYLO0 2, 0 | |
131 | #define C0_TCBIND 2, 2 | |
132 | #define C0_ENTRYLO1 3, 0 | |
133 | #define C0_CONTEXT 4, 0 | |
fd062c84 | 134 | #define C0_PAGEMASK 5, 0 |
41c594ab RB |
135 | #define C0_BADVADDR 8, 0 |
136 | #define C0_ENTRYHI 10, 0 | |
137 | #define C0_EPC 14, 0 | |
138 | #define C0_XCONTEXT 20, 0 | |
1da177e4 | 139 | |
875d43e7 | 140 | #ifdef CONFIG_64BIT |
e30ec452 | 141 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) |
1da177e4 | 142 | #else |
e30ec452 | 143 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) |
1da177e4 LT |
144 | #endif |
145 | ||
146 | /* The worst case length of the handler is around 18 instructions for | |
147 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
148 | * Maximum space available is 32 instructions for R3000 and 64 | |
149 | * instructions for R4000. | |
150 | * | |
151 | * We deliberately chose a buffer size of 128, so we won't scribble | |
152 | * over anything important on overflow before we panic. | |
153 | */ | |
234fcd14 | 154 | static u32 tlb_handler[128] __cpuinitdata; |
1da177e4 LT |
155 | |
156 | /* simply assume worst case size for labels and relocs */ | |
234fcd14 RB |
157 | static struct uasm_label labels[128] __cpuinitdata; |
158 | static struct uasm_reloc relocs[128] __cpuinitdata; | |
1da177e4 | 159 | |
82622284 DD |
160 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
161 | /* | |
162 | * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, | |
163 | * we cannot do r3000 under these circumstances. | |
164 | */ | |
165 | ||
1da177e4 LT |
166 | /* |
167 | * The R3000 TLB handler is simple. | |
168 | */ | |
234fcd14 | 169 | static void __cpuinit build_r3000_tlb_refill_handler(void) |
1da177e4 LT |
170 | { |
171 | long pgdc = (long)pgd_current; | |
172 | u32 *p; | |
173 | ||
174 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
175 | p = tlb_handler; | |
176 | ||
e30ec452 TS |
177 | uasm_i_mfc0(&p, K0, C0_BADVADDR); |
178 | uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
179 | uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); | |
180 | uasm_i_srl(&p, K0, K0, 22); /* load delay */ | |
181 | uasm_i_sll(&p, K0, K0, 2); | |
182 | uasm_i_addu(&p, K1, K1, K0); | |
183 | uasm_i_mfc0(&p, K0, C0_CONTEXT); | |
184 | uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ | |
185 | uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ | |
186 | uasm_i_addu(&p, K1, K1, K0); | |
187 | uasm_i_lw(&p, K0, 0, K1); | |
188 | uasm_i_nop(&p); /* load delay */ | |
189 | uasm_i_mtc0(&p, K0, C0_ENTRYLO0); | |
190 | uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ | |
191 | uasm_i_tlbwr(&p); /* cp0 delay */ | |
192 | uasm_i_jr(&p, K1); | |
193 | uasm_i_rfe(&p); /* branch delay */ | |
1da177e4 LT |
194 | |
195 | if (p > tlb_handler + 32) | |
196 | panic("TLB refill handler space exceeded"); | |
197 | ||
e30ec452 TS |
198 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
199 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 200 | |
91b05e67 | 201 | memcpy((void *)ebase, tlb_handler, 0x80); |
92b1e6a6 FBH |
202 | |
203 | dump_handler((u32 *)ebase, 32); | |
1da177e4 | 204 | } |
82622284 | 205 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
206 | |
207 | /* | |
208 | * The R4000 TLB handler is much more complicated. We have two | |
209 | * consecutive handler areas with 32 instructions space each. | |
210 | * Since they aren't used at the same time, we can overflow in the | |
211 | * other one.To keep things simple, we first assume linear space, | |
212 | * then we relocate it to the final handler layout as needed. | |
213 | */ | |
234fcd14 | 214 | static u32 final_handler[64] __cpuinitdata; |
1da177e4 LT |
215 | |
216 | /* | |
217 | * Hazards | |
218 | * | |
219 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
220 | * 2. A timing hazard exists for the TLBP instruction. | |
221 | * | |
222 | * stalling_instruction | |
223 | * TLBP | |
224 | * | |
225 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
226 | * previous instruction. This is not really correct as the stalling instruction | |
227 | * can modify the address used to access the JTLB. The failure symptom is that | |
228 | * the TLBP instruction will use an address created for the stalling instruction | |
229 | * and not the address held in C0_ENHI and thus report the wrong results. | |
230 | * | |
231 | * The software work-around is to not allow the instruction preceding the TLBP | |
232 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
233 | * | |
234 | * Errata 2 will not be fixed. This errata is also on the R5000. | |
235 | * | |
236 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
237 | */ | |
234fcd14 | 238 | static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p) |
1da177e4 | 239 | { |
10cc3529 | 240 | switch (current_cpu_type()) { |
326e2e1a | 241 | /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ |
f5b4d956 | 242 | case CPU_R4600: |
326e2e1a | 243 | case CPU_R4700: |
1da177e4 LT |
244 | case CPU_R5000: |
245 | case CPU_R5000A: | |
246 | case CPU_NEVADA: | |
e30ec452 TS |
247 | uasm_i_nop(p); |
248 | uasm_i_tlbp(p); | |
1da177e4 LT |
249 | break; |
250 | ||
251 | default: | |
e30ec452 | 252 | uasm_i_tlbp(p); |
1da177e4 LT |
253 | break; |
254 | } | |
255 | } | |
256 | ||
257 | /* | |
258 | * Write random or indexed TLB entry, and care about the hazards from | |
259 | * the preceeding mtc0 and for the following eret. | |
260 | */ | |
261 | enum tlb_write_entry { tlb_random, tlb_indexed }; | |
262 | ||
234fcd14 | 263 | static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, |
e30ec452 | 264 | struct uasm_reloc **r, |
1da177e4 LT |
265 | enum tlb_write_entry wmode) |
266 | { | |
267 | void(*tlbw)(u32 **) = NULL; | |
268 | ||
269 | switch (wmode) { | |
e30ec452 TS |
270 | case tlb_random: tlbw = uasm_i_tlbwr; break; |
271 | case tlb_indexed: tlbw = uasm_i_tlbwi; break; | |
1da177e4 LT |
272 | } |
273 | ||
161548bf | 274 | if (cpu_has_mips_r2) { |
41f0e4d0 DD |
275 | if (cpu_has_mips_r2_exec_hazard) |
276 | uasm_i_ehb(p); | |
161548bf RB |
277 | tlbw(p); |
278 | return; | |
279 | } | |
280 | ||
10cc3529 | 281 | switch (current_cpu_type()) { |
1da177e4 LT |
282 | case CPU_R4000PC: |
283 | case CPU_R4000SC: | |
284 | case CPU_R4000MC: | |
285 | case CPU_R4400PC: | |
286 | case CPU_R4400SC: | |
287 | case CPU_R4400MC: | |
288 | /* | |
289 | * This branch uses up a mtc0 hazard nop slot and saves | |
290 | * two nops after the tlbw instruction. | |
291 | */ | |
e30ec452 | 292 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard); |
1da177e4 | 293 | tlbw(p); |
e30ec452 TS |
294 | uasm_l_tlbw_hazard(l, *p); |
295 | uasm_i_nop(p); | |
1da177e4 LT |
296 | break; |
297 | ||
298 | case CPU_R4600: | |
299 | case CPU_R4700: | |
300 | case CPU_R5000: | |
301 | case CPU_R5000A: | |
e30ec452 | 302 | uasm_i_nop(p); |
2c93e12c | 303 | tlbw(p); |
e30ec452 | 304 | uasm_i_nop(p); |
2c93e12c MR |
305 | break; |
306 | ||
307 | case CPU_R4300: | |
1da177e4 LT |
308 | case CPU_5KC: |
309 | case CPU_TX49XX: | |
bdf21b18 | 310 | case CPU_PR4450: |
e30ec452 | 311 | uasm_i_nop(p); |
1da177e4 LT |
312 | tlbw(p); |
313 | break; | |
314 | ||
315 | case CPU_R10000: | |
316 | case CPU_R12000: | |
44d921b2 | 317 | case CPU_R14000: |
1da177e4 | 318 | case CPU_4KC: |
b1ec4c8e | 319 | case CPU_4KEC: |
1da177e4 | 320 | case CPU_SB1: |
93ce2f52 | 321 | case CPU_SB1A: |
1da177e4 LT |
322 | case CPU_4KSC: |
323 | case CPU_20KC: | |
324 | case CPU_25KF: | |
1c0c13eb AJ |
325 | case CPU_BCM3302: |
326 | case CPU_BCM4710: | |
2a21c730 | 327 | case CPU_LOONGSON2: |
0de663ef MB |
328 | case CPU_BCM6338: |
329 | case CPU_BCM6345: | |
330 | case CPU_BCM6348: | |
331 | case CPU_BCM6358: | |
a644b277 | 332 | case CPU_R5500: |
8df5beac | 333 | if (m4kc_tlbp_war()) |
e30ec452 | 334 | uasm_i_nop(p); |
2f794d09 | 335 | case CPU_ALCHEMY: |
1da177e4 LT |
336 | tlbw(p); |
337 | break; | |
338 | ||
339 | case CPU_NEVADA: | |
e30ec452 | 340 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ |
1da177e4 LT |
341 | /* |
342 | * This branch uses up a mtc0 hazard nop slot and saves | |
343 | * a nop after the tlbw instruction. | |
344 | */ | |
e30ec452 | 345 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard); |
1da177e4 | 346 | tlbw(p); |
e30ec452 | 347 | uasm_l_tlbw_hazard(l, *p); |
1da177e4 LT |
348 | break; |
349 | ||
350 | case CPU_RM7000: | |
e30ec452 TS |
351 | uasm_i_nop(p); |
352 | uasm_i_nop(p); | |
353 | uasm_i_nop(p); | |
354 | uasm_i_nop(p); | |
1da177e4 LT |
355 | tlbw(p); |
356 | break; | |
357 | ||
1da177e4 LT |
358 | case CPU_RM9000: |
359 | /* | |
360 | * When the JTLB is updated by tlbwi or tlbwr, a subsequent | |
361 | * use of the JTLB for instructions should not occur for 4 | |
362 | * cpu cycles and use for data translations should not occur | |
363 | * for 3 cpu cycles. | |
364 | */ | |
e30ec452 TS |
365 | uasm_i_ssnop(p); |
366 | uasm_i_ssnop(p); | |
367 | uasm_i_ssnop(p); | |
368 | uasm_i_ssnop(p); | |
1da177e4 | 369 | tlbw(p); |
e30ec452 TS |
370 | uasm_i_ssnop(p); |
371 | uasm_i_ssnop(p); | |
372 | uasm_i_ssnop(p); | |
373 | uasm_i_ssnop(p); | |
1da177e4 LT |
374 | break; |
375 | ||
376 | case CPU_VR4111: | |
377 | case CPU_VR4121: | |
378 | case CPU_VR4122: | |
379 | case CPU_VR4181: | |
380 | case CPU_VR4181A: | |
e30ec452 TS |
381 | uasm_i_nop(p); |
382 | uasm_i_nop(p); | |
1da177e4 | 383 | tlbw(p); |
e30ec452 TS |
384 | uasm_i_nop(p); |
385 | uasm_i_nop(p); | |
1da177e4 LT |
386 | break; |
387 | ||
388 | case CPU_VR4131: | |
389 | case CPU_VR4133: | |
7623debf | 390 | case CPU_R5432: |
e30ec452 TS |
391 | uasm_i_nop(p); |
392 | uasm_i_nop(p); | |
1da177e4 LT |
393 | tlbw(p); |
394 | break; | |
395 | ||
396 | default: | |
397 | panic("No TLB refill handler yet (CPU type: %d)", | |
398 | current_cpu_data.cputype); | |
399 | break; | |
400 | } | |
401 | } | |
402 | ||
6dd9344c DD |
403 | static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, |
404 | unsigned int reg) | |
fd062c84 | 405 | { |
6dd9344c DD |
406 | if (kernel_uses_smartmips_rixi) { |
407 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); | |
408 | UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
409 | } else { | |
410 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
411 | uasm_i_dsrl(p, reg, reg, ilog2(_PAGE_GLOBAL)); | |
412 | #else | |
413 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); | |
414 | #endif | |
415 | } | |
416 | } | |
fd062c84 | 417 | |
6dd9344c | 418 | #ifdef CONFIG_HUGETLB_PAGE |
fd062c84 | 419 | |
6dd9344c DD |
420 | static __cpuinit void build_restore_pagemask(u32 **p, |
421 | struct uasm_reloc **r, | |
422 | unsigned int tmp, | |
423 | enum label_id lid) | |
424 | { | |
fd062c84 DD |
425 | /* Reset default page size */ |
426 | if (PM_DEFAULT_MASK >> 16) { | |
427 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
428 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
6dd9344c | 429 | uasm_il_b(p, r, lid); |
fd062c84 DD |
430 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); |
431 | } else if (PM_DEFAULT_MASK) { | |
432 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
6dd9344c | 433 | uasm_il_b(p, r, lid); |
fd062c84 DD |
434 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); |
435 | } else { | |
6dd9344c | 436 | uasm_il_b(p, r, lid); |
fd062c84 DD |
437 | uasm_i_mtc0(p, 0, C0_PAGEMASK); |
438 | } | |
439 | } | |
440 | ||
6dd9344c DD |
441 | static __cpuinit void build_huge_tlb_write_entry(u32 **p, |
442 | struct uasm_label **l, | |
443 | struct uasm_reloc **r, | |
444 | unsigned int tmp, | |
445 | enum tlb_write_entry wmode) | |
446 | { | |
447 | /* Set huge page tlb entry size */ | |
448 | uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); | |
449 | uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); | |
450 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
451 | ||
452 | build_tlb_write_entry(p, l, r, wmode); | |
453 | ||
454 | build_restore_pagemask(p, r, tmp, label_leave); | |
455 | } | |
456 | ||
fd062c84 DD |
457 | /* |
458 | * Check if Huge PTE is present, if so then jump to LABEL. | |
459 | */ | |
460 | static void __cpuinit | |
461 | build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, | |
462 | unsigned int pmd, int lid) | |
463 | { | |
464 | UASM_i_LW(p, tmp, 0, pmd); | |
465 | uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); | |
466 | uasm_il_bnez(p, r, tmp, lid); | |
467 | } | |
468 | ||
469 | static __cpuinit void build_huge_update_entries(u32 **p, | |
470 | unsigned int pte, | |
471 | unsigned int tmp) | |
472 | { | |
473 | int small_sequence; | |
474 | ||
475 | /* | |
476 | * A huge PTE describes an area the size of the | |
477 | * configured huge page size. This is twice the | |
478 | * of the large TLB entry size we intend to use. | |
479 | * A TLB entry half the size of the configured | |
480 | * huge page size is configured into entrylo0 | |
481 | * and entrylo1 to cover the contiguous huge PTE | |
482 | * address space. | |
483 | */ | |
484 | small_sequence = (HPAGE_SIZE >> 7) < 0x10000; | |
485 | ||
486 | /* We can clobber tmp. It isn't used after this.*/ | |
487 | if (!small_sequence) | |
488 | uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); | |
489 | ||
6dd9344c | 490 | build_convert_pte_to_entrylo(p, pte); |
9b8c3891 | 491 | UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ |
fd062c84 DD |
492 | /* convert to entrylo1 */ |
493 | if (small_sequence) | |
494 | UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); | |
495 | else | |
496 | UASM_i_ADDU(p, pte, pte, tmp); | |
497 | ||
9b8c3891 | 498 | UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ |
fd062c84 DD |
499 | } |
500 | ||
501 | static __cpuinit void build_huge_handler_tail(u32 **p, | |
502 | struct uasm_reloc **r, | |
503 | struct uasm_label **l, | |
504 | unsigned int pte, | |
505 | unsigned int ptr) | |
506 | { | |
507 | #ifdef CONFIG_SMP | |
508 | UASM_i_SC(p, pte, 0, ptr); | |
509 | uasm_il_beqz(p, r, pte, label_tlb_huge_update); | |
510 | UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ | |
511 | #else | |
512 | UASM_i_SW(p, pte, 0, ptr); | |
513 | #endif | |
514 | build_huge_update_entries(p, pte, ptr); | |
515 | build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed); | |
516 | } | |
517 | #endif /* CONFIG_HUGETLB_PAGE */ | |
518 | ||
875d43e7 | 519 | #ifdef CONFIG_64BIT |
1da177e4 LT |
520 | /* |
521 | * TMP and PTR are scratch. | |
522 | * TMP will be clobbered, PTR will hold the pmd entry. | |
523 | */ | |
234fcd14 | 524 | static void __cpuinit |
e30ec452 | 525 | build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
526 | unsigned int tmp, unsigned int ptr) |
527 | { | |
82622284 | 528 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 | 529 | long pgdc = (long)pgd_current; |
82622284 | 530 | #endif |
1da177e4 LT |
531 | /* |
532 | * The vmalloc handling is not in the hotpath. | |
533 | */ | |
e30ec452 | 534 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
e30ec452 | 535 | uasm_il_bltz(p, r, tmp, label_vmalloc); |
e30ec452 | 536 | /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ |
1da177e4 | 537 | |
82622284 DD |
538 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
539 | /* | |
540 | * &pgd << 11 stored in CONTEXT [23..63]. | |
541 | */ | |
542 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
543 | uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */ | |
544 | uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */ | |
545 | uasm_i_drotr(p, ptr, ptr, 11); | |
546 | #elif defined(CONFIG_SMP) | |
41c594ab RB |
547 | # ifdef CONFIG_MIPS_MT_SMTC |
548 | /* | |
549 | * SMTC uses TCBind value as "CPU" index | |
550 | */ | |
e30ec452 TS |
551 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
552 | uasm_i_dsrl(p, ptr, ptr, 19); | |
41c594ab | 553 | # else |
1da177e4 | 554 | /* |
1b3a6e97 | 555 | * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 |
1da177e4 LT |
556 | * stored in CONTEXT. |
557 | */ | |
e30ec452 TS |
558 | uasm_i_dmfc0(p, ptr, C0_CONTEXT); |
559 | uasm_i_dsrl(p, ptr, ptr, 23); | |
82622284 | 560 | # endif |
e30ec452 TS |
561 | UASM_i_LA_mostly(p, tmp, pgdc); |
562 | uasm_i_daddu(p, ptr, ptr, tmp); | |
563 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); | |
564 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 565 | #else |
e30ec452 TS |
566 | UASM_i_LA_mostly(p, ptr, pgdc); |
567 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 LT |
568 | #endif |
569 | ||
e30ec452 | 570 | uasm_l_vmalloc_done(l, *p); |
242954b5 RB |
571 | |
572 | if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */ | |
e30ec452 | 573 | uasm_i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); |
242954b5 | 574 | else |
e30ec452 TS |
575 | uasm_i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32); |
576 | ||
577 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); | |
578 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
325f8a0a | 579 | #ifndef __PAGETABLE_PMD_FOLDED |
e30ec452 TS |
580 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
581 | uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
582 | uasm_i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ | |
583 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); | |
584 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
325f8a0a | 585 | #endif |
1da177e4 LT |
586 | } |
587 | ||
588 | /* | |
589 | * BVADDR is the faulting address, PTR is scratch. | |
590 | * PTR will hold the pgd for vmalloc. | |
591 | */ | |
234fcd14 | 592 | static void __cpuinit |
e30ec452 | 593 | build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
594 | unsigned int bvaddr, unsigned int ptr) |
595 | { | |
596 | long swpd = (long)swapper_pg_dir; | |
597 | ||
e30ec452 | 598 | uasm_l_vmalloc(l, *p); |
1da177e4 | 599 | |
e30ec452 TS |
600 | if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { |
601 | uasm_il_b(p, r, label_vmalloc_done); | |
602 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
1da177e4 | 603 | } else { |
e30ec452 TS |
604 | UASM_i_LA_mostly(p, ptr, swpd); |
605 | uasm_il_b(p, r, label_vmalloc_done); | |
606 | if (uasm_in_compat_space_p(swpd)) | |
607 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
619b6e18 | 608 | else |
e30ec452 | 609 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); |
1da177e4 LT |
610 | } |
611 | } | |
612 | ||
875d43e7 | 613 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
614 | |
615 | /* | |
616 | * TMP and PTR are scratch. | |
617 | * TMP will be clobbered, PTR will hold the pgd entry. | |
618 | */ | |
234fcd14 | 619 | static void __cpuinit __maybe_unused |
1da177e4 LT |
620 | build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
621 | { | |
622 | long pgdc = (long)pgd_current; | |
623 | ||
624 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ | |
625 | #ifdef CONFIG_SMP | |
41c594ab RB |
626 | #ifdef CONFIG_MIPS_MT_SMTC |
627 | /* | |
628 | * SMTC uses TCBind value as "CPU" index | |
629 | */ | |
e30ec452 TS |
630 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
631 | UASM_i_LA_mostly(p, tmp, pgdc); | |
632 | uasm_i_srl(p, ptr, ptr, 19); | |
41c594ab RB |
633 | #else |
634 | /* | |
635 | * smp_processor_id() << 3 is stored in CONTEXT. | |
636 | */ | |
e30ec452 TS |
637 | uasm_i_mfc0(p, ptr, C0_CONTEXT); |
638 | UASM_i_LA_mostly(p, tmp, pgdc); | |
639 | uasm_i_srl(p, ptr, ptr, 23); | |
41c594ab | 640 | #endif |
e30ec452 | 641 | uasm_i_addu(p, ptr, tmp, ptr); |
1da177e4 | 642 | #else |
e30ec452 | 643 | UASM_i_LA_mostly(p, ptr, pgdc); |
1da177e4 | 644 | #endif |
e30ec452 TS |
645 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
646 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
647 | uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ | |
648 | uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); | |
649 | uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1da177e4 LT |
650 | } |
651 | ||
875d43e7 | 652 | #endif /* !CONFIG_64BIT */ |
1da177e4 | 653 | |
234fcd14 | 654 | static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) |
1da177e4 | 655 | { |
242954b5 | 656 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1da177e4 LT |
657 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
658 | ||
10cc3529 | 659 | switch (current_cpu_type()) { |
1da177e4 LT |
660 | case CPU_VR41XX: |
661 | case CPU_VR4111: | |
662 | case CPU_VR4121: | |
663 | case CPU_VR4122: | |
664 | case CPU_VR4131: | |
665 | case CPU_VR4181: | |
666 | case CPU_VR4181A: | |
667 | case CPU_VR4133: | |
668 | shift += 2; | |
669 | break; | |
670 | ||
671 | default: | |
672 | break; | |
673 | } | |
674 | ||
675 | if (shift) | |
e30ec452 TS |
676 | UASM_i_SRL(p, ctx, ctx, shift); |
677 | uasm_i_andi(p, ctx, ctx, mask); | |
1da177e4 LT |
678 | } |
679 | ||
234fcd14 | 680 | static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 LT |
681 | { |
682 | /* | |
683 | * Bug workaround for the Nevada. It seems as if under certain | |
684 | * circumstances the move from cp0_context might produce a | |
685 | * bogus result when the mfc0 instruction and its consumer are | |
686 | * in a different cacheline or a load instruction, probably any | |
687 | * memory reference, is between them. | |
688 | */ | |
10cc3529 | 689 | switch (current_cpu_type()) { |
1da177e4 | 690 | case CPU_NEVADA: |
e30ec452 | 691 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
692 | GET_CONTEXT(p, tmp); /* get context reg */ |
693 | break; | |
694 | ||
695 | default: | |
696 | GET_CONTEXT(p, tmp); /* get context reg */ | |
e30ec452 | 697 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
698 | break; |
699 | } | |
700 | ||
701 | build_adjust_context(p, tmp); | |
e30ec452 | 702 | UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ |
1da177e4 LT |
703 | } |
704 | ||
234fcd14 | 705 | static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, |
1da177e4 LT |
706 | unsigned int ptep) |
707 | { | |
708 | /* | |
709 | * 64bit address support (36bit on a 32bit CPU) in a 32bit | |
710 | * Kernel is a special case. Only a few CPUs use it. | |
711 | */ | |
712 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
713 | if (cpu_has_64bits) { | |
e30ec452 TS |
714 | uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ |
715 | uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
6dd9344c DD |
716 | if (kernel_uses_smartmips_rixi) { |
717 | UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); | |
718 | UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); | |
719 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
720 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
721 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
722 | } else { | |
723 | uasm_i_dsrl(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ | |
724 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
725 | uasm_i_dsrl(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ | |
726 | } | |
9b8c3891 | 727 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
728 | } else { |
729 | int pte_off_even = sizeof(pte_t) / 2; | |
730 | int pte_off_odd = pte_off_even + sizeof(pte_t); | |
731 | ||
732 | /* The pte entries are pre-shifted */ | |
e30ec452 | 733 | uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ |
9b8c3891 | 734 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ |
e30ec452 | 735 | uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ |
9b8c3891 | 736 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ |
1da177e4 LT |
737 | } |
738 | #else | |
e30ec452 TS |
739 | UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ |
740 | UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1da177e4 LT |
741 | if (r45k_bvahwbug()) |
742 | build_tlb_probe_entry(p); | |
6dd9344c DD |
743 | if (kernel_uses_smartmips_rixi) { |
744 | UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); | |
745 | UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); | |
746 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
747 | if (r4k_250MHZhwbug()) | |
748 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
749 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
750 | UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
751 | } else { | |
752 | UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ | |
753 | if (r4k_250MHZhwbug()) | |
754 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
755 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
756 | UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ | |
757 | if (r45k_bvahwbug()) | |
758 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
759 | } | |
1da177e4 | 760 | if (r4k_250MHZhwbug()) |
9b8c3891 DD |
761 | UASM_i_MTC0(p, 0, C0_ENTRYLO1); |
762 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
763 | #endif |
764 | } | |
765 | ||
e6f72d3a DD |
766 | /* |
767 | * For a 64-bit kernel, we are using the 64-bit XTLB refill exception | |
768 | * because EXL == 0. If we wrap, we can also use the 32 instruction | |
769 | * slots before the XTLB refill exception handler which belong to the | |
770 | * unused TLB refill exception. | |
771 | */ | |
772 | #define MIPS64_REFILL_INSNS 32 | |
773 | ||
234fcd14 | 774 | static void __cpuinit build_r4000_tlb_refill_handler(void) |
1da177e4 LT |
775 | { |
776 | u32 *p = tlb_handler; | |
e30ec452 TS |
777 | struct uasm_label *l = labels; |
778 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
779 | u32 *f; |
780 | unsigned int final_len; | |
781 | ||
782 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
783 | memset(labels, 0, sizeof(labels)); | |
784 | memset(relocs, 0, sizeof(relocs)); | |
785 | memset(final_handler, 0, sizeof(final_handler)); | |
786 | ||
787 | /* | |
788 | * create the plain linear handler | |
789 | */ | |
790 | if (bcm1250_m3_war()) { | |
3d45285d RB |
791 | unsigned int segbits = 44; |
792 | ||
793 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
794 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
e30ec452 | 795 | uasm_i_xor(&p, K0, K0, K1); |
3d45285d RB |
796 | uasm_i_dsrl32(&p, K1, K0, 62 - 32); |
797 | uasm_i_dsrl(&p, K0, K0, 12 + 1); | |
798 | uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32); | |
799 | uasm_i_or(&p, K0, K0, K1); | |
e30ec452 TS |
800 | uasm_il_bnez(&p, &r, K0, label_leave); |
801 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
802 | } |
803 | ||
875d43e7 | 804 | #ifdef CONFIG_64BIT |
1da177e4 LT |
805 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
806 | #else | |
807 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ | |
808 | #endif | |
809 | ||
fd062c84 DD |
810 | #ifdef CONFIG_HUGETLB_PAGE |
811 | build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); | |
812 | #endif | |
813 | ||
1da177e4 LT |
814 | build_get_ptep(&p, K0, K1); |
815 | build_update_entries(&p, K0, K1); | |
816 | build_tlb_write_entry(&p, &l, &r, tlb_random); | |
e30ec452 TS |
817 | uasm_l_leave(&l, p); |
818 | uasm_i_eret(&p); /* return from trap */ | |
1da177e4 | 819 | |
fd062c84 DD |
820 | #ifdef CONFIG_HUGETLB_PAGE |
821 | uasm_l_tlb_huge_update(&l, p); | |
822 | UASM_i_LW(&p, K0, 0, K1); | |
823 | build_huge_update_entries(&p, K0, K1); | |
824 | build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random); | |
825 | #endif | |
826 | ||
875d43e7 | 827 | #ifdef CONFIG_64BIT |
1da177e4 LT |
828 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); |
829 | #endif | |
830 | ||
831 | /* | |
832 | * Overflow check: For the 64bit handler, we need at least one | |
833 | * free instruction slot for the wrap-around branch. In worst | |
834 | * case, if the intended insertion point is a delay slot, we | |
4b3f686d | 835 | * need three, with the second nop'ed and the third being |
1da177e4 LT |
836 | * unused. |
837 | */ | |
2a21c730 FZ |
838 | /* Loongson2 ebase is different than r4k, we have more space */ |
839 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) | |
1da177e4 LT |
840 | if ((p - tlb_handler) > 64) |
841 | panic("TLB refill handler space exceeded"); | |
842 | #else | |
e6f72d3a DD |
843 | if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) |
844 | || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) | |
845 | && uasm_insn_has_bdelay(relocs, | |
846 | tlb_handler + MIPS64_REFILL_INSNS - 3))) | |
1da177e4 LT |
847 | panic("TLB refill handler space exceeded"); |
848 | #endif | |
849 | ||
850 | /* | |
851 | * Now fold the handler in the TLB refill handler space. | |
852 | */ | |
2a21c730 | 853 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) |
1da177e4 LT |
854 | f = final_handler; |
855 | /* Simplest case, just copy the handler. */ | |
e30ec452 | 856 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 | 857 | final_len = p - tlb_handler; |
875d43e7 | 858 | #else /* CONFIG_64BIT */ |
e6f72d3a DD |
859 | f = final_handler + MIPS64_REFILL_INSNS; |
860 | if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { | |
1da177e4 | 861 | /* Just copy the handler. */ |
e30ec452 | 862 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 LT |
863 | final_len = p - tlb_handler; |
864 | } else { | |
fd062c84 DD |
865 | #if defined(CONFIG_HUGETLB_PAGE) |
866 | const enum label_id ls = label_tlb_huge_update; | |
95affdda DD |
867 | #else |
868 | const enum label_id ls = label_vmalloc; | |
869 | #endif | |
870 | u32 *split; | |
871 | int ov = 0; | |
872 | int i; | |
873 | ||
874 | for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) | |
875 | ; | |
876 | BUG_ON(i == ARRAY_SIZE(labels)); | |
877 | split = labels[i].addr; | |
1da177e4 LT |
878 | |
879 | /* | |
95affdda | 880 | * See if we have overflown one way or the other. |
1da177e4 | 881 | */ |
95affdda DD |
882 | if (split > tlb_handler + MIPS64_REFILL_INSNS || |
883 | split < p - MIPS64_REFILL_INSNS) | |
884 | ov = 1; | |
885 | ||
886 | if (ov) { | |
887 | /* | |
888 | * Split two instructions before the end. One | |
889 | * for the branch and one for the instruction | |
890 | * in the delay slot. | |
891 | */ | |
892 | split = tlb_handler + MIPS64_REFILL_INSNS - 2; | |
893 | ||
894 | /* | |
895 | * If the branch would fall in a delay slot, | |
896 | * we must back up an additional instruction | |
897 | * so that it is no longer in a delay slot. | |
898 | */ | |
899 | if (uasm_insn_has_bdelay(relocs, split - 1)) | |
900 | split--; | |
901 | } | |
1da177e4 | 902 | /* Copy first part of the handler. */ |
e30ec452 | 903 | uasm_copy_handler(relocs, labels, tlb_handler, split, f); |
1da177e4 LT |
904 | f += split - tlb_handler; |
905 | ||
95affdda DD |
906 | if (ov) { |
907 | /* Insert branch. */ | |
908 | uasm_l_split(&l, final_handler); | |
909 | uasm_il_b(&f, &r, label_split); | |
910 | if (uasm_insn_has_bdelay(relocs, split)) | |
911 | uasm_i_nop(&f); | |
912 | else { | |
913 | uasm_copy_handler(relocs, labels, | |
914 | split, split + 1, f); | |
915 | uasm_move_labels(labels, f, f + 1, -1); | |
916 | f++; | |
917 | split++; | |
918 | } | |
1da177e4 LT |
919 | } |
920 | ||
921 | /* Copy the rest of the handler. */ | |
e30ec452 | 922 | uasm_copy_handler(relocs, labels, split, p, final_handler); |
e6f72d3a DD |
923 | final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + |
924 | (p - split); | |
1da177e4 | 925 | } |
875d43e7 | 926 | #endif /* CONFIG_64BIT */ |
1da177e4 | 927 | |
e30ec452 TS |
928 | uasm_resolve_relocs(relocs, labels); |
929 | pr_debug("Wrote TLB refill handler (%u instructions).\n", | |
930 | final_len); | |
1da177e4 | 931 | |
91b05e67 | 932 | memcpy((void *)ebase, final_handler, 0x100); |
92b1e6a6 FBH |
933 | |
934 | dump_handler((u32 *)ebase, 64); | |
1da177e4 LT |
935 | } |
936 | ||
937 | /* | |
938 | * TLB load/store/modify handlers. | |
939 | * | |
940 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
941 | * do_page_fault remains normal asm. | |
942 | */ | |
943 | extern void tlb_do_page_fault_0(void); | |
944 | extern void tlb_do_page_fault_1(void); | |
945 | ||
1da177e4 LT |
946 | /* |
947 | * 128 instructions for the fastpath handler is generous and should | |
948 | * never be exceeded. | |
949 | */ | |
950 | #define FASTPATH_SIZE 128 | |
951 | ||
cbdbe07f FBH |
952 | u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; |
953 | u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; | |
954 | u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; | |
1da177e4 | 955 | |
234fcd14 | 956 | static void __cpuinit |
bd1437e4 | 957 | iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
958 | { |
959 | #ifdef CONFIG_SMP | |
960 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
961 | if (cpu_has_64bits) | |
e30ec452 | 962 | uasm_i_lld(p, pte, 0, ptr); |
1da177e4 LT |
963 | else |
964 | # endif | |
e30ec452 | 965 | UASM_i_LL(p, pte, 0, ptr); |
1da177e4 LT |
966 | #else |
967 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
968 | if (cpu_has_64bits) | |
e30ec452 | 969 | uasm_i_ld(p, pte, 0, ptr); |
1da177e4 LT |
970 | else |
971 | # endif | |
e30ec452 | 972 | UASM_i_LW(p, pte, 0, ptr); |
1da177e4 LT |
973 | #endif |
974 | } | |
975 | ||
234fcd14 | 976 | static void __cpuinit |
e30ec452 | 977 | iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, |
63b2d2f4 | 978 | unsigned int mode) |
1da177e4 | 979 | { |
63b2d2f4 TS |
980 | #ifdef CONFIG_64BIT_PHYS_ADDR |
981 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); | |
982 | #endif | |
983 | ||
e30ec452 | 984 | uasm_i_ori(p, pte, pte, mode); |
1da177e4 LT |
985 | #ifdef CONFIG_SMP |
986 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
987 | if (cpu_has_64bits) | |
e30ec452 | 988 | uasm_i_scd(p, pte, 0, ptr); |
1da177e4 LT |
989 | else |
990 | # endif | |
e30ec452 | 991 | UASM_i_SC(p, pte, 0, ptr); |
1da177e4 LT |
992 | |
993 | if (r10000_llsc_war()) | |
e30ec452 | 994 | uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 995 | else |
e30ec452 | 996 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
1da177e4 LT |
997 | |
998 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
999 | if (!cpu_has_64bits) { | |
e30ec452 TS |
1000 | /* no uasm_i_nop needed */ |
1001 | uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
1002 | uasm_i_ori(p, pte, pte, hwmode); | |
1003 | uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); | |
1004 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); | |
1005 | /* no uasm_i_nop needed */ | |
1006 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 | 1007 | } else |
e30ec452 | 1008 | uasm_i_nop(p); |
1da177e4 | 1009 | # else |
e30ec452 | 1010 | uasm_i_nop(p); |
1da177e4 LT |
1011 | # endif |
1012 | #else | |
1013 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1014 | if (cpu_has_64bits) | |
e30ec452 | 1015 | uasm_i_sd(p, pte, 0, ptr); |
1da177e4 LT |
1016 | else |
1017 | # endif | |
e30ec452 | 1018 | UASM_i_SW(p, pte, 0, ptr); |
1da177e4 LT |
1019 | |
1020 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1021 | if (!cpu_has_64bits) { | |
e30ec452 TS |
1022 | uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); |
1023 | uasm_i_ori(p, pte, pte, hwmode); | |
1024 | uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); | |
1025 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 LT |
1026 | } |
1027 | # endif | |
1028 | #endif | |
1029 | } | |
1030 | ||
1031 | /* | |
1032 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
1033 | * the page table where this PTE is located, PTE will be re-loaded | |
1034 | * with it's original value. | |
1035 | */ | |
234fcd14 | 1036 | static void __cpuinit |
bd1437e4 | 1037 | build_pte_present(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
1038 | unsigned int pte, unsigned int ptr, enum label_id lid) |
1039 | { | |
6dd9344c DD |
1040 | if (kernel_uses_smartmips_rixi) { |
1041 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT); | |
1042 | uasm_il_beqz(p, r, pte, lid); | |
1043 | } else { | |
1044 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); | |
1045 | uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); | |
1046 | uasm_il_bnez(p, r, pte, lid); | |
1047 | } | |
bd1437e4 | 1048 | iPTE_LW(p, pte, ptr); |
1da177e4 LT |
1049 | } |
1050 | ||
1051 | /* Make PTE valid, store result in PTR. */ | |
234fcd14 | 1052 | static void __cpuinit |
e30ec452 | 1053 | build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1054 | unsigned int ptr) |
1055 | { | |
63b2d2f4 TS |
1056 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
1057 | ||
1058 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1059 | } |
1060 | ||
1061 | /* | |
1062 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
1063 | * restore PTE with value from PTR when done. | |
1064 | */ | |
234fcd14 | 1065 | static void __cpuinit |
bd1437e4 | 1066 | build_pte_writable(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
1067 | unsigned int pte, unsigned int ptr, enum label_id lid) |
1068 | { | |
e30ec452 TS |
1069 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); |
1070 | uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
1071 | uasm_il_bnez(p, r, pte, lid); | |
bd1437e4 | 1072 | iPTE_LW(p, pte, ptr); |
1da177e4 LT |
1073 | } |
1074 | ||
1075 | /* Make PTE writable, update software status bits as well, then store | |
1076 | * at PTR. | |
1077 | */ | |
234fcd14 | 1078 | static void __cpuinit |
e30ec452 | 1079 | build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
1080 | unsigned int ptr) |
1081 | { | |
63b2d2f4 TS |
1082 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
1083 | | _PAGE_DIRTY); | |
1084 | ||
1085 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1086 | } |
1087 | ||
1088 | /* | |
1089 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
1090 | * restore PTE with value from PTR when done. | |
1091 | */ | |
234fcd14 | 1092 | static void __cpuinit |
bd1437e4 | 1093 | build_pte_modifiable(u32 **p, struct uasm_reloc **r, |
1da177e4 LT |
1094 | unsigned int pte, unsigned int ptr, enum label_id lid) |
1095 | { | |
e30ec452 TS |
1096 | uasm_i_andi(p, pte, pte, _PAGE_WRITE); |
1097 | uasm_il_beqz(p, r, pte, lid); | |
bd1437e4 | 1098 | iPTE_LW(p, pte, ptr); |
1da177e4 LT |
1099 | } |
1100 | ||
82622284 | 1101 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 LT |
1102 | /* |
1103 | * R3000 style TLB load/store/modify handlers. | |
1104 | */ | |
1105 | ||
fded2e50 MR |
1106 | /* |
1107 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
1108 | * Then it returns. | |
1109 | */ | |
234fcd14 | 1110 | static void __cpuinit |
fded2e50 | 1111 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 1112 | { |
e30ec452 TS |
1113 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1114 | uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
1115 | uasm_i_tlbwi(p); | |
1116 | uasm_i_jr(p, tmp); | |
1117 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1118 | } |
1119 | ||
1120 | /* | |
fded2e50 MR |
1121 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
1122 | * or tlbwr as appropriate. This is because the index register | |
1123 | * may have the probe fail bit set as a result of a trap on a | |
1124 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 | 1125 | */ |
234fcd14 | 1126 | static void __cpuinit |
e30ec452 TS |
1127 | build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, |
1128 | struct uasm_reloc **r, unsigned int pte, | |
1129 | unsigned int tmp) | |
1130 | { | |
1131 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1132 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ | |
1133 | uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
1134 | uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
1135 | uasm_i_tlbwi(p); /* cp0 delay */ | |
1136 | uasm_i_jr(p, tmp); | |
1137 | uasm_i_rfe(p); /* branch delay */ | |
1138 | uasm_l_r3000_write_probe_fail(l, *p); | |
1139 | uasm_i_tlbwr(p); /* cp0 delay */ | |
1140 | uasm_i_jr(p, tmp); | |
1141 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1142 | } |
1143 | ||
234fcd14 | 1144 | static void __cpuinit |
1da177e4 LT |
1145 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, |
1146 | unsigned int ptr) | |
1147 | { | |
1148 | long pgdc = (long)pgd_current; | |
1149 | ||
e30ec452 TS |
1150 | uasm_i_mfc0(p, pte, C0_BADVADDR); |
1151 | uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
1152 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1153 | uasm_i_srl(p, pte, pte, 22); /* load delay */ | |
1154 | uasm_i_sll(p, pte, pte, 2); | |
1155 | uasm_i_addu(p, ptr, ptr, pte); | |
1156 | uasm_i_mfc0(p, pte, C0_CONTEXT); | |
1157 | uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
1158 | uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ | |
1159 | uasm_i_addu(p, ptr, ptr, pte); | |
1160 | uasm_i_lw(p, pte, 0, ptr); | |
1161 | uasm_i_tlbp(p); /* load delay */ | |
1da177e4 LT |
1162 | } |
1163 | ||
234fcd14 | 1164 | static void __cpuinit build_r3000_tlb_load_handler(void) |
1da177e4 LT |
1165 | { |
1166 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1167 | struct uasm_label *l = labels; |
1168 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1169 | |
1170 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1171 | memset(labels, 0, sizeof(labels)); | |
1172 | memset(relocs, 0, sizeof(relocs)); | |
1173 | ||
1174 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1175 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); |
e30ec452 | 1176 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1177 | build_make_valid(&p, &r, K0, K1); |
fded2e50 | 1178 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1179 | |
e30ec452 TS |
1180 | uasm_l_nopage_tlbl(&l, p); |
1181 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1182 | uasm_i_nop(&p); | |
1da177e4 LT |
1183 | |
1184 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1185 | panic("TLB load handler fastpath space exceeded"); | |
1186 | ||
e30ec452 TS |
1187 | uasm_resolve_relocs(relocs, labels); |
1188 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1189 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1190 | |
92b1e6a6 | 1191 | dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
1192 | } |
1193 | ||
234fcd14 | 1194 | static void __cpuinit build_r3000_tlb_store_handler(void) |
1da177e4 LT |
1195 | { |
1196 | u32 *p = handle_tlbs; | |
e30ec452 TS |
1197 | struct uasm_label *l = labels; |
1198 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1199 | |
1200 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1201 | memset(labels, 0, sizeof(labels)); | |
1202 | memset(relocs, 0, sizeof(relocs)); | |
1203 | ||
1204 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1205 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); |
e30ec452 | 1206 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1207 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1208 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1209 | |
e30ec452 TS |
1210 | uasm_l_nopage_tlbs(&l, p); |
1211 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1212 | uasm_i_nop(&p); | |
1da177e4 LT |
1213 | |
1214 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1215 | panic("TLB store handler fastpath space exceeded"); | |
1216 | ||
e30ec452 TS |
1217 | uasm_resolve_relocs(relocs, labels); |
1218 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1219 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1220 | |
92b1e6a6 | 1221 | dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
1222 | } |
1223 | ||
234fcd14 | 1224 | static void __cpuinit build_r3000_tlb_modify_handler(void) |
1da177e4 LT |
1225 | { |
1226 | u32 *p = handle_tlbm; | |
e30ec452 TS |
1227 | struct uasm_label *l = labels; |
1228 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1229 | |
1230 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1231 | memset(labels, 0, sizeof(labels)); | |
1232 | memset(relocs, 0, sizeof(relocs)); | |
1233 | ||
1234 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
bd1437e4 | 1235 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); |
e30ec452 | 1236 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1237 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1238 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
1da177e4 | 1239 | |
e30ec452 TS |
1240 | uasm_l_nopage_tlbm(&l, p); |
1241 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1242 | uasm_i_nop(&p); | |
1da177e4 LT |
1243 | |
1244 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1245 | panic("TLB modify handler fastpath space exceeded"); | |
1246 | ||
e30ec452 TS |
1247 | uasm_resolve_relocs(relocs, labels); |
1248 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1249 | (unsigned int)(p - handle_tlbm)); | |
1da177e4 | 1250 | |
92b1e6a6 | 1251 | dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 | 1252 | } |
82622284 | 1253 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
1254 | |
1255 | /* | |
1256 | * R4000 style TLB load/store/modify handlers. | |
1257 | */ | |
234fcd14 | 1258 | static void __cpuinit |
e30ec452 TS |
1259 | build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, |
1260 | struct uasm_reloc **r, unsigned int pte, | |
1da177e4 LT |
1261 | unsigned int ptr) |
1262 | { | |
875d43e7 | 1263 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1264 | build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ |
1265 | #else | |
1266 | build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ | |
1267 | #endif | |
1268 | ||
fd062c84 DD |
1269 | #ifdef CONFIG_HUGETLB_PAGE |
1270 | /* | |
1271 | * For huge tlb entries, pmd doesn't contain an address but | |
1272 | * instead contains the tlb pte. Check the PAGE_HUGE bit and | |
1273 | * see if we need to jump to huge tlb processing. | |
1274 | */ | |
1275 | build_is_huge_pte(p, r, pte, ptr, label_tlb_huge_update); | |
1276 | #endif | |
1277 | ||
e30ec452 TS |
1278 | UASM_i_MFC0(p, pte, C0_BADVADDR); |
1279 | UASM_i_LW(p, ptr, 0, ptr); | |
1280 | UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); | |
1281 | uasm_i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); | |
1282 | UASM_i_ADDU(p, ptr, ptr, pte); | |
1da177e4 LT |
1283 | |
1284 | #ifdef CONFIG_SMP | |
e30ec452 TS |
1285 | uasm_l_smp_pgtable_change(l, *p); |
1286 | #endif | |
bd1437e4 | 1287 | iPTE_LW(p, pte, ptr); /* get even pte */ |
8df5beac MR |
1288 | if (!m4kc_tlbp_war()) |
1289 | build_tlb_probe_entry(p); | |
1da177e4 LT |
1290 | } |
1291 | ||
234fcd14 | 1292 | static void __cpuinit |
e30ec452 TS |
1293 | build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, |
1294 | struct uasm_reloc **r, unsigned int tmp, | |
1da177e4 LT |
1295 | unsigned int ptr) |
1296 | { | |
e30ec452 TS |
1297 | uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); |
1298 | uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1da177e4 LT |
1299 | build_update_entries(p, tmp, ptr); |
1300 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
e30ec452 TS |
1301 | uasm_l_leave(l, *p); |
1302 | uasm_i_eret(p); /* return from trap */ | |
1da177e4 | 1303 | |
875d43e7 | 1304 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1305 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr); |
1306 | #endif | |
1307 | } | |
1308 | ||
234fcd14 | 1309 | static void __cpuinit build_r4000_tlb_load_handler(void) |
1da177e4 LT |
1310 | { |
1311 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1312 | struct uasm_label *l = labels; |
1313 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1314 | |
1315 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1316 | memset(labels, 0, sizeof(labels)); | |
1317 | memset(relocs, 0, sizeof(relocs)); | |
1318 | ||
1319 | if (bcm1250_m3_war()) { | |
3d45285d RB |
1320 | unsigned int segbits = 44; |
1321 | ||
1322 | uasm_i_dmfc0(&p, K0, C0_BADVADDR); | |
1323 | uasm_i_dmfc0(&p, K1, C0_ENTRYHI); | |
e30ec452 | 1324 | uasm_i_xor(&p, K0, K0, K1); |
3d45285d RB |
1325 | uasm_i_dsrl32(&p, K1, K0, 62 - 32); |
1326 | uasm_i_dsrl(&p, K0, K0, 12 + 1); | |
1327 | uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32); | |
1328 | uasm_i_or(&p, K0, K0, K1); | |
e30ec452 TS |
1329 | uasm_il_bnez(&p, &r, K0, label_leave); |
1330 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
1331 | } |
1332 | ||
1333 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1334 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); |
8df5beac MR |
1335 | if (m4kc_tlbp_war()) |
1336 | build_tlb_probe_entry(&p); | |
6dd9344c DD |
1337 | |
1338 | if (kernel_uses_smartmips_rixi) { | |
1339 | /* | |
1340 | * If the page is not _PAGE_VALID, RI or XI could not | |
1341 | * have triggered it. Skip the expensive test.. | |
1342 | */ | |
1343 | uasm_i_andi(&p, K0, K0, _PAGE_VALID); | |
1344 | uasm_il_beqz(&p, &r, K0, label_tlbl_goaround1); | |
1345 | uasm_i_nop(&p); | |
1346 | ||
1347 | uasm_i_tlbr(&p); | |
1348 | /* Examine entrylo 0 or 1 based on ptr. */ | |
1349 | uasm_i_andi(&p, K0, K1, sizeof(pte_t)); | |
1350 | uasm_i_beqz(&p, K0, 8); | |
1351 | ||
1352 | UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/ | |
1353 | UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */ | |
1354 | /* | |
1355 | * If the entryLo (now in K0) is valid (bit 1), RI or | |
1356 | * XI must have triggered it. | |
1357 | */ | |
1358 | uasm_i_andi(&p, K0, K0, 2); | |
1359 | uasm_il_bnez(&p, &r, K0, label_nopage_tlbl); | |
1360 | ||
1361 | uasm_l_tlbl_goaround1(&l, p); | |
1362 | /* Reload the PTE value */ | |
1363 | iPTE_LW(&p, K0, K1); | |
1364 | } | |
1da177e4 LT |
1365 | build_make_valid(&p, &r, K0, K1); |
1366 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1367 | ||
fd062c84 DD |
1368 | #ifdef CONFIG_HUGETLB_PAGE |
1369 | /* | |
1370 | * This is the entry point when build_r4000_tlbchange_handler_head | |
1371 | * spots a huge page. | |
1372 | */ | |
1373 | uasm_l_tlb_huge_update(&l, p); | |
1374 | iPTE_LW(&p, K0, K1); | |
1375 | build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); | |
1376 | build_tlb_probe_entry(&p); | |
6dd9344c DD |
1377 | |
1378 | if (kernel_uses_smartmips_rixi) { | |
1379 | /* | |
1380 | * If the page is not _PAGE_VALID, RI or XI could not | |
1381 | * have triggered it. Skip the expensive test.. | |
1382 | */ | |
1383 | uasm_i_andi(&p, K0, K0, _PAGE_VALID); | |
1384 | uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); | |
1385 | uasm_i_nop(&p); | |
1386 | ||
1387 | uasm_i_tlbr(&p); | |
1388 | /* Examine entrylo 0 or 1 based on ptr. */ | |
1389 | uasm_i_andi(&p, K0, K1, sizeof(pte_t)); | |
1390 | uasm_i_beqz(&p, K0, 8); | |
1391 | ||
1392 | UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/ | |
1393 | UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */ | |
1394 | /* | |
1395 | * If the entryLo (now in K0) is valid (bit 1), RI or | |
1396 | * XI must have triggered it. | |
1397 | */ | |
1398 | uasm_i_andi(&p, K0, K0, 2); | |
1399 | uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); | |
1400 | /* Reload the PTE value */ | |
1401 | iPTE_LW(&p, K0, K1); | |
1402 | ||
1403 | /* | |
1404 | * We clobbered C0_PAGEMASK, restore it. On the other branch | |
1405 | * it is restored in build_huge_tlb_write_entry. | |
1406 | */ | |
1407 | build_restore_pagemask(&p, &r, K0, label_nopage_tlbl); | |
1408 | ||
1409 | uasm_l_tlbl_goaround2(&l, p); | |
1410 | } | |
fd062c84 DD |
1411 | uasm_i_ori(&p, K0, K0, (_PAGE_ACCESSED | _PAGE_VALID)); |
1412 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1413 | #endif | |
1414 | ||
e30ec452 TS |
1415 | uasm_l_nopage_tlbl(&l, p); |
1416 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1417 | uasm_i_nop(&p); | |
1da177e4 LT |
1418 | |
1419 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1420 | panic("TLB load handler fastpath space exceeded"); | |
1421 | ||
e30ec452 TS |
1422 | uasm_resolve_relocs(relocs, labels); |
1423 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1424 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1425 | |
92b1e6a6 | 1426 | dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
1427 | } |
1428 | ||
234fcd14 | 1429 | static void __cpuinit build_r4000_tlb_store_handler(void) |
1da177e4 LT |
1430 | { |
1431 | u32 *p = handle_tlbs; | |
e30ec452 TS |
1432 | struct uasm_label *l = labels; |
1433 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1434 | |
1435 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1436 | memset(labels, 0, sizeof(labels)); | |
1437 | memset(relocs, 0, sizeof(relocs)); | |
1438 | ||
1439 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1440 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); |
8df5beac MR |
1441 | if (m4kc_tlbp_war()) |
1442 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1443 | build_make_write(&p, &r, K0, K1); |
1444 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1445 | ||
fd062c84 DD |
1446 | #ifdef CONFIG_HUGETLB_PAGE |
1447 | /* | |
1448 | * This is the entry point when | |
1449 | * build_r4000_tlbchange_handler_head spots a huge page. | |
1450 | */ | |
1451 | uasm_l_tlb_huge_update(&l, p); | |
1452 | iPTE_LW(&p, K0, K1); | |
1453 | build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs); | |
1454 | build_tlb_probe_entry(&p); | |
1455 | uasm_i_ori(&p, K0, K0, | |
1456 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); | |
1457 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1458 | #endif | |
1459 | ||
e30ec452 TS |
1460 | uasm_l_nopage_tlbs(&l, p); |
1461 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1462 | uasm_i_nop(&p); | |
1da177e4 LT |
1463 | |
1464 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1465 | panic("TLB store handler fastpath space exceeded"); | |
1466 | ||
e30ec452 TS |
1467 | uasm_resolve_relocs(relocs, labels); |
1468 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1469 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1470 | |
92b1e6a6 | 1471 | dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
1472 | } |
1473 | ||
234fcd14 | 1474 | static void __cpuinit build_r4000_tlb_modify_handler(void) |
1da177e4 LT |
1475 | { |
1476 | u32 *p = handle_tlbm; | |
e30ec452 TS |
1477 | struct uasm_label *l = labels; |
1478 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1479 | |
1480 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1481 | memset(labels, 0, sizeof(labels)); | |
1482 | memset(relocs, 0, sizeof(relocs)); | |
1483 | ||
1484 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
bd1437e4 | 1485 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); |
8df5beac MR |
1486 | if (m4kc_tlbp_war()) |
1487 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1488 | /* Present and writable bits set, set accessed and dirty bits. */ |
1489 | build_make_write(&p, &r, K0, K1); | |
1490 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1491 | ||
fd062c84 DD |
1492 | #ifdef CONFIG_HUGETLB_PAGE |
1493 | /* | |
1494 | * This is the entry point when | |
1495 | * build_r4000_tlbchange_handler_head spots a huge page. | |
1496 | */ | |
1497 | uasm_l_tlb_huge_update(&l, p); | |
1498 | iPTE_LW(&p, K0, K1); | |
1499 | build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm); | |
1500 | build_tlb_probe_entry(&p); | |
1501 | uasm_i_ori(&p, K0, K0, | |
1502 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); | |
1503 | build_huge_handler_tail(&p, &r, &l, K0, K1); | |
1504 | #endif | |
1505 | ||
e30ec452 TS |
1506 | uasm_l_nopage_tlbm(&l, p); |
1507 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1508 | uasm_i_nop(&p); | |
1da177e4 LT |
1509 | |
1510 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1511 | panic("TLB modify handler fastpath space exceeded"); | |
1512 | ||
e30ec452 TS |
1513 | uasm_resolve_relocs(relocs, labels); |
1514 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1515 | (unsigned int)(p - handle_tlbm)); | |
115f2a44 | 1516 | |
92b1e6a6 | 1517 | dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 LT |
1518 | } |
1519 | ||
234fcd14 | 1520 | void __cpuinit build_tlb_refill_handler(void) |
1da177e4 LT |
1521 | { |
1522 | /* | |
1523 | * The refill handler is generated per-CPU, multi-node systems | |
1524 | * may have local storage for it. The other handlers are only | |
1525 | * needed once. | |
1526 | */ | |
1527 | static int run_once = 0; | |
1528 | ||
10cc3529 | 1529 | switch (current_cpu_type()) { |
1da177e4 LT |
1530 | case CPU_R2000: |
1531 | case CPU_R3000: | |
1532 | case CPU_R3000A: | |
1533 | case CPU_R3081E: | |
1534 | case CPU_TX3912: | |
1535 | case CPU_TX3922: | |
1536 | case CPU_TX3927: | |
82622284 | 1537 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 LT |
1538 | build_r3000_tlb_refill_handler(); |
1539 | if (!run_once) { | |
1540 | build_r3000_tlb_load_handler(); | |
1541 | build_r3000_tlb_store_handler(); | |
1542 | build_r3000_tlb_modify_handler(); | |
1543 | run_once++; | |
1544 | } | |
82622284 DD |
1545 | #else |
1546 | panic("No R3000 TLB refill handler"); | |
1547 | #endif | |
1da177e4 LT |
1548 | break; |
1549 | ||
1550 | case CPU_R6000: | |
1551 | case CPU_R6000A: | |
1552 | panic("No R6000 TLB refill handler yet"); | |
1553 | break; | |
1554 | ||
1555 | case CPU_R8000: | |
1556 | panic("No R8000 TLB refill handler yet"); | |
1557 | break; | |
1558 | ||
1559 | default: | |
1560 | build_r4000_tlb_refill_handler(); | |
1561 | if (!run_once) { | |
1562 | build_r4000_tlb_load_handler(); | |
1563 | build_r4000_tlb_store_handler(); | |
1564 | build_r4000_tlb_modify_handler(); | |
1565 | run_once++; | |
1566 | } | |
1567 | } | |
1568 | } | |
1d40cfcd | 1569 | |
234fcd14 | 1570 | void __cpuinit flush_tlb_handlers(void) |
1d40cfcd | 1571 | { |
e0cee3ee | 1572 | local_flush_icache_range((unsigned long)handle_tlbl, |
1d40cfcd | 1573 | (unsigned long)handle_tlbl + sizeof(handle_tlbl)); |
e0cee3ee | 1574 | local_flush_icache_range((unsigned long)handle_tlbs, |
1d40cfcd | 1575 | (unsigned long)handle_tlbs + sizeof(handle_tlbs)); |
e0cee3ee | 1576 | local_flush_icache_range((unsigned long)handle_tlbm, |
1d40cfcd RB |
1577 | (unsigned long)handle_tlbm + sizeof(handle_tlbm)); |
1578 | } |