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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
115f2a44 | 8 | * Copyright (C) 2004,2005,2006 by Thiemo Seufer |
fded2e50 | 9 | * Copyright (C) 2005 Maciej W. Rozycki |
41c594ab RB |
10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
11 | * | |
12 | * ... and the days got worse and worse and now you see | |
13 | * I've gone completly out of my mind. | |
14 | * | |
15 | * They're coming to take me a away haha | |
16 | * they're coming to take me a away hoho hihi haha | |
17 | * to the funny farm where code is beautiful all the time ... | |
18 | * | |
19 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
20 | */ |
21 | ||
22 | #include <stdarg.h> | |
23 | ||
1da177e4 LT |
24 | #include <linux/mm.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/types.h> | |
27 | #include <linux/string.h> | |
28 | #include <linux/init.h> | |
29 | ||
30 | #include <asm/pgtable.h> | |
31 | #include <asm/cacheflush.h> | |
32 | #include <asm/mmu_context.h> | |
33 | #include <asm/inst.h> | |
34 | #include <asm/elf.h> | |
35 | #include <asm/smp.h> | |
36 | #include <asm/war.h> | |
37 | ||
e8b6d40a | 38 | static __init int __maybe_unused r45k_bvahwbug(void) |
1da177e4 LT |
39 | { |
40 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
41 | return 0; | |
42 | } | |
43 | ||
e8b6d40a | 44 | static __init int __maybe_unused r4k_250MHZhwbug(void) |
1da177e4 LT |
45 | { |
46 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
47 | return 0; | |
48 | } | |
49 | ||
e8b6d40a | 50 | static __init int __maybe_unused bcm1250_m3_war(void) |
1da177e4 LT |
51 | { |
52 | return BCM1250_M3_WAR; | |
53 | } | |
54 | ||
e8b6d40a | 55 | static __init int __maybe_unused r10000_llsc_war(void) |
1da177e4 LT |
56 | { |
57 | return R10000_LLSC_WAR; | |
58 | } | |
59 | ||
60 | /* | |
61 | * A little micro-assembler, intended for TLB refill handler | |
62 | * synthesizing. It is intentionally kept simple, does only support | |
63 | * a subset of instructions, and does not try to hide pipeline effects | |
64 | * like branch delay slots. | |
65 | */ | |
66 | ||
67 | enum fields | |
68 | { | |
69 | RS = 0x001, | |
70 | RT = 0x002, | |
71 | RD = 0x004, | |
72 | RE = 0x008, | |
73 | SIMM = 0x010, | |
74 | UIMM = 0x020, | |
75 | BIMM = 0x040, | |
76 | JIMM = 0x080, | |
77 | FUNC = 0x100, | |
41c594ab | 78 | SET = 0x200 |
1da177e4 LT |
79 | }; |
80 | ||
81 | #define OP_MASK 0x2f | |
82 | #define OP_SH 26 | |
83 | #define RS_MASK 0x1f | |
84 | #define RS_SH 21 | |
85 | #define RT_MASK 0x1f | |
86 | #define RT_SH 16 | |
87 | #define RD_MASK 0x1f | |
88 | #define RD_SH 11 | |
89 | #define RE_MASK 0x1f | |
90 | #define RE_SH 6 | |
91 | #define IMM_MASK 0xffff | |
92 | #define IMM_SH 0 | |
93 | #define JIMM_MASK 0x3ffffff | |
94 | #define JIMM_SH 0 | |
95 | #define FUNC_MASK 0x2f | |
96 | #define FUNC_SH 0 | |
41c594ab RB |
97 | #define SET_MASK 0x7 |
98 | #define SET_SH 0 | |
1da177e4 LT |
99 | |
100 | enum opcode { | |
101 | insn_invalid, | |
102 | insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, | |
103 | insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, | |
104 | insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, | |
242954b5 | 105 | insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, |
1da177e4 LT |
106 | insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, |
107 | insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, | |
108 | insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, | |
109 | insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi, | |
110 | insn_tlbwr, insn_xor, insn_xori | |
111 | }; | |
112 | ||
113 | struct insn { | |
114 | enum opcode opcode; | |
115 | u32 match; | |
116 | enum fields fields; | |
117 | }; | |
118 | ||
119 | /* This macro sets the non-variable bits of an instruction. */ | |
120 | #define M(a, b, c, d, e, f) \ | |
121 | ((a) << OP_SH \ | |
122 | | (b) << RS_SH \ | |
123 | | (c) << RT_SH \ | |
124 | | (d) << RD_SH \ | |
125 | | (e) << RE_SH \ | |
126 | | (f) << FUNC_SH) | |
127 | ||
128 | static __initdata struct insn insn_table[] = { | |
129 | { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM }, | |
130 | { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD }, | |
131 | { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD }, | |
132 | { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM }, | |
133 | { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM }, | |
134 | { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM }, | |
135 | { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM }, | |
136 | { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM }, | |
137 | { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM }, | |
138 | { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM }, | |
139 | { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM }, | |
140 | { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM }, | |
141 | { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD }, | |
41c594ab RB |
142 | { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD | SET}, |
143 | { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD | SET}, | |
1da177e4 LT |
144 | { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE }, |
145 | { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, | |
146 | { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, | |
147 | { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, | |
242954b5 | 148 | { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE }, |
1da177e4 LT |
149 | { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, |
150 | { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, | |
151 | { insn_j, M(j_op,0,0,0,0,0), JIMM }, | |
152 | { insn_jal, M(jal_op,0,0,0,0,0), JIMM }, | |
153 | { insn_jr, M(spec_op,0,0,0,0,jr_op), RS }, | |
154 | { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM }, | |
155 | { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM }, | |
156 | { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM }, | |
157 | { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM }, | |
158 | { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM }, | |
41c594ab RB |
159 | { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD | SET}, |
160 | { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD | SET}, | |
1da177e4 LT |
161 | { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM }, |
162 | { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 }, | |
163 | { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM }, | |
164 | { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM }, | |
165 | { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM }, | |
166 | { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE }, | |
167 | { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE }, | |
168 | { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE }, | |
169 | { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD }, | |
170 | { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM }, | |
171 | { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 }, | |
172 | { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 }, | |
173 | { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 }, | |
174 | { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD }, | |
175 | { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM }, | |
176 | { insn_invalid, 0, 0 } | |
177 | }; | |
178 | ||
179 | #undef M | |
180 | ||
181 | static __init u32 build_rs(u32 arg) | |
182 | { | |
183 | if (arg & ~RS_MASK) | |
184 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
185 | ||
186 | return (arg & RS_MASK) << RS_SH; | |
187 | } | |
188 | ||
189 | static __init u32 build_rt(u32 arg) | |
190 | { | |
191 | if (arg & ~RT_MASK) | |
192 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
193 | ||
194 | return (arg & RT_MASK) << RT_SH; | |
195 | } | |
196 | ||
197 | static __init u32 build_rd(u32 arg) | |
198 | { | |
199 | if (arg & ~RD_MASK) | |
200 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
201 | ||
202 | return (arg & RD_MASK) << RD_SH; | |
203 | } | |
204 | ||
205 | static __init u32 build_re(u32 arg) | |
206 | { | |
207 | if (arg & ~RE_MASK) | |
208 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
209 | ||
210 | return (arg & RE_MASK) << RE_SH; | |
211 | } | |
212 | ||
213 | static __init u32 build_simm(s32 arg) | |
214 | { | |
215 | if (arg > 0x7fff || arg < -0x8000) | |
216 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
217 | ||
218 | return arg & 0xffff; | |
219 | } | |
220 | ||
221 | static __init u32 build_uimm(u32 arg) | |
222 | { | |
223 | if (arg & ~IMM_MASK) | |
224 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
225 | ||
226 | return arg & IMM_MASK; | |
227 | } | |
228 | ||
229 | static __init u32 build_bimm(s32 arg) | |
230 | { | |
231 | if (arg > 0x1ffff || arg < -0x20000) | |
232 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
233 | ||
234 | if (arg & 0x3) | |
235 | printk(KERN_WARNING "Invalid TLB synthesizer branch target\n"); | |
236 | ||
237 | return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); | |
238 | } | |
239 | ||
240 | static __init u32 build_jimm(u32 arg) | |
241 | { | |
242 | if (arg & ~((JIMM_MASK) << 2)) | |
243 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
244 | ||
245 | return (arg >> 2) & JIMM_MASK; | |
246 | } | |
247 | ||
248 | static __init u32 build_func(u32 arg) | |
249 | { | |
250 | if (arg & ~FUNC_MASK) | |
251 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
252 | ||
253 | return arg & FUNC_MASK; | |
254 | } | |
255 | ||
41c594ab RB |
256 | static __init u32 build_set(u32 arg) |
257 | { | |
258 | if (arg & ~SET_MASK) | |
259 | printk(KERN_WARNING "TLB synthesizer field overflow\n"); | |
260 | ||
261 | return arg & SET_MASK; | |
262 | } | |
263 | ||
1da177e4 LT |
264 | /* |
265 | * The order of opcode arguments is implicitly left to right, | |
266 | * starting with RS and ending with FUNC or IMM. | |
267 | */ | |
268 | static void __init build_insn(u32 **buf, enum opcode opc, ...) | |
269 | { | |
270 | struct insn *ip = NULL; | |
271 | unsigned int i; | |
272 | va_list ap; | |
273 | u32 op; | |
274 | ||
275 | for (i = 0; insn_table[i].opcode != insn_invalid; i++) | |
276 | if (insn_table[i].opcode == opc) { | |
277 | ip = &insn_table[i]; | |
278 | break; | |
279 | } | |
280 | ||
281 | if (!ip) | |
282 | panic("Unsupported TLB synthesizer instruction %d", opc); | |
283 | ||
284 | op = ip->match; | |
285 | va_start(ap, opc); | |
286 | if (ip->fields & RS) op |= build_rs(va_arg(ap, u32)); | |
287 | if (ip->fields & RT) op |= build_rt(va_arg(ap, u32)); | |
288 | if (ip->fields & RD) op |= build_rd(va_arg(ap, u32)); | |
289 | if (ip->fields & RE) op |= build_re(va_arg(ap, u32)); | |
290 | if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32)); | |
291 | if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32)); | |
292 | if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32)); | |
293 | if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32)); | |
294 | if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32)); | |
41c594ab | 295 | if (ip->fields & SET) op |= build_set(va_arg(ap, u32)); |
1da177e4 LT |
296 | va_end(ap); |
297 | ||
298 | **buf = op; | |
299 | (*buf)++; | |
300 | } | |
301 | ||
302 | #define I_u1u2u3(op) \ | |
1443e483 | 303 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
304 | unsigned int b, unsigned int c) \ |
305 | { \ | |
306 | build_insn(buf, insn##op, a, b, c); \ | |
307 | } | |
308 | ||
309 | #define I_u2u1u3(op) \ | |
1443e483 | 310 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
311 | unsigned int b, unsigned int c) \ |
312 | { \ | |
313 | build_insn(buf, insn##op, b, a, c); \ | |
314 | } | |
315 | ||
316 | #define I_u3u1u2(op) \ | |
1443e483 | 317 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
318 | unsigned int b, unsigned int c) \ |
319 | { \ | |
320 | build_insn(buf, insn##op, b, c, a); \ | |
321 | } | |
322 | ||
323 | #define I_u1u2s3(op) \ | |
1443e483 | 324 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
325 | unsigned int b, signed int c) \ |
326 | { \ | |
327 | build_insn(buf, insn##op, a, b, c); \ | |
328 | } | |
329 | ||
330 | #define I_u2s3u1(op) \ | |
1443e483 | 331 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
332 | signed int b, unsigned int c) \ |
333 | { \ | |
334 | build_insn(buf, insn##op, c, a, b); \ | |
335 | } | |
336 | ||
337 | #define I_u2u1s3(op) \ | |
1443e483 | 338 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
339 | unsigned int b, signed int c) \ |
340 | { \ | |
341 | build_insn(buf, insn##op, b, a, c); \ | |
342 | } | |
343 | ||
344 | #define I_u1u2(op) \ | |
1443e483 | 345 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
346 | unsigned int b) \ |
347 | { \ | |
348 | build_insn(buf, insn##op, a, b); \ | |
349 | } | |
350 | ||
351 | #define I_u1s2(op) \ | |
1443e483 | 352 | static inline void __init i##op(u32 **buf, unsigned int a, \ |
1da177e4 LT |
353 | signed int b) \ |
354 | { \ | |
355 | build_insn(buf, insn##op, a, b); \ | |
356 | } | |
357 | ||
358 | #define I_u1(op) \ | |
1443e483 | 359 | static inline void __init i##op(u32 **buf, unsigned int a) \ |
1da177e4 LT |
360 | { \ |
361 | build_insn(buf, insn##op, a); \ | |
362 | } | |
363 | ||
364 | #define I_0(op) \ | |
1443e483 | 365 | static inline void __init i##op(u32 **buf) \ |
1da177e4 LT |
366 | { \ |
367 | build_insn(buf, insn##op); \ | |
368 | } | |
369 | ||
370 | I_u2u1s3(_addiu); | |
371 | I_u3u1u2(_addu); | |
372 | I_u2u1u3(_andi); | |
373 | I_u3u1u2(_and); | |
374 | I_u1u2s3(_beq); | |
375 | I_u1u2s3(_beql); | |
376 | I_u1s2(_bgez); | |
377 | I_u1s2(_bgezl); | |
378 | I_u1s2(_bltz); | |
379 | I_u1s2(_bltzl); | |
380 | I_u1u2s3(_bne); | |
41c594ab RB |
381 | I_u1u2u3(_dmfc0); |
382 | I_u1u2u3(_dmtc0); | |
1da177e4 LT |
383 | I_u2u1s3(_daddiu); |
384 | I_u3u1u2(_daddu); | |
385 | I_u2u1u3(_dsll); | |
386 | I_u2u1u3(_dsll32); | |
387 | I_u2u1u3(_dsra); | |
388 | I_u2u1u3(_dsrl); | |
242954b5 | 389 | I_u2u1u3(_dsrl32); |
1da177e4 LT |
390 | I_u3u1u2(_dsubu); |
391 | I_0(_eret); | |
392 | I_u1(_j); | |
393 | I_u1(_jal); | |
394 | I_u1(_jr); | |
395 | I_u2s3u1(_ld); | |
396 | I_u2s3u1(_ll); | |
397 | I_u2s3u1(_lld); | |
398 | I_u1s2(_lui); | |
399 | I_u2s3u1(_lw); | |
41c594ab RB |
400 | I_u1u2u3(_mfc0); |
401 | I_u1u2u3(_mtc0); | |
1da177e4 LT |
402 | I_u2u1u3(_ori); |
403 | I_0(_rfe); | |
404 | I_u2s3u1(_sc); | |
405 | I_u2s3u1(_scd); | |
406 | I_u2s3u1(_sd); | |
407 | I_u2u1u3(_sll); | |
408 | I_u2u1u3(_sra); | |
409 | I_u2u1u3(_srl); | |
410 | I_u3u1u2(_subu); | |
411 | I_u2s3u1(_sw); | |
412 | I_0(_tlbp); | |
413 | I_0(_tlbwi); | |
414 | I_0(_tlbwr); | |
415 | I_u3u1u2(_xor) | |
416 | I_u2u1u3(_xori); | |
417 | ||
418 | /* | |
419 | * handling labels | |
420 | */ | |
421 | ||
422 | enum label_id { | |
423 | label_invalid, | |
424 | label_second_part, | |
425 | label_leave, | |
656be92f AN |
426 | #ifdef MODULE_START |
427 | label_module_alloc, | |
428 | #endif | |
1da177e4 LT |
429 | label_vmalloc, |
430 | label_vmalloc_done, | |
431 | label_tlbw_hazard, | |
432 | label_split, | |
433 | label_nopage_tlbl, | |
434 | label_nopage_tlbs, | |
435 | label_nopage_tlbm, | |
436 | label_smp_pgtable_change, | |
437 | label_r3000_write_probe_fail, | |
1da177e4 LT |
438 | }; |
439 | ||
440 | struct label { | |
441 | u32 *addr; | |
442 | enum label_id lab; | |
443 | }; | |
444 | ||
445 | static __init void build_label(struct label **lab, u32 *addr, | |
446 | enum label_id l) | |
447 | { | |
448 | (*lab)->addr = addr; | |
449 | (*lab)->lab = l; | |
450 | (*lab)++; | |
451 | } | |
452 | ||
453 | #define L_LA(lb) \ | |
454 | static inline void l##lb(struct label **lab, u32 *addr) \ | |
455 | { \ | |
456 | build_label(lab, addr, label##lb); \ | |
457 | } | |
458 | ||
459 | L_LA(_second_part) | |
460 | L_LA(_leave) | |
656be92f AN |
461 | #ifdef MODULE_START |
462 | L_LA(_module_alloc) | |
463 | #endif | |
1da177e4 LT |
464 | L_LA(_vmalloc) |
465 | L_LA(_vmalloc_done) | |
466 | L_LA(_tlbw_hazard) | |
467 | L_LA(_split) | |
468 | L_LA(_nopage_tlbl) | |
469 | L_LA(_nopage_tlbs) | |
470 | L_LA(_nopage_tlbm) | |
471 | L_LA(_smp_pgtable_change) | |
472 | L_LA(_r3000_write_probe_fail) | |
1da177e4 LT |
473 | |
474 | /* convenience macros for instructions */ | |
875d43e7 | 475 | #ifdef CONFIG_64BIT |
1da177e4 LT |
476 | # define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off) |
477 | # define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off) | |
478 | # define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh) | |
479 | # define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh) | |
480 | # define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh) | |
41c594ab RB |
481 | # define i_MFC0(buf, rt, rd...) i_dmfc0(buf, rt, rd) |
482 | # define i_MTC0(buf, rt, rd...) i_dmtc0(buf, rt, rd) | |
1da177e4 LT |
483 | # define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val) |
484 | # define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd) | |
485 | # define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd) | |
486 | # define i_LL(buf, rs, rt, off) i_lld(buf, rs, rt, off) | |
487 | # define i_SC(buf, rs, rt, off) i_scd(buf, rs, rt, off) | |
488 | #else | |
489 | # define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off) | |
490 | # define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off) | |
491 | # define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh) | |
492 | # define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh) | |
493 | # define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh) | |
41c594ab RB |
494 | # define i_MFC0(buf, rt, rd...) i_mfc0(buf, rt, rd) |
495 | # define i_MTC0(buf, rt, rd...) i_mtc0(buf, rt, rd) | |
1da177e4 LT |
496 | # define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val) |
497 | # define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd) | |
498 | # define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd) | |
499 | # define i_LL(buf, rs, rt, off) i_ll(buf, rs, rt, off) | |
500 | # define i_SC(buf, rs, rt, off) i_sc(buf, rs, rt, off) | |
501 | #endif | |
502 | ||
503 | #define i_b(buf, off) i_beq(buf, 0, 0, off) | |
504 | #define i_beqz(buf, rs, off) i_beq(buf, rs, 0, off) | |
505 | #define i_beqzl(buf, rs, off) i_beql(buf, rs, 0, off) | |
506 | #define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off) | |
507 | #define i_bnezl(buf, rs, off) i_bnel(buf, rs, 0, off) | |
508 | #define i_move(buf, a, b) i_ADDU(buf, a, 0, b) | |
509 | #define i_nop(buf) i_sll(buf, 0, 0, 0) | |
510 | #define i_ssnop(buf) i_sll(buf, 0, 0, 1) | |
511 | #define i_ehb(buf) i_sll(buf, 0, 0, 3) | |
512 | ||
875d43e7 | 513 | #ifdef CONFIG_64BIT |
e8b6d40a | 514 | static __init int __maybe_unused in_compat_space_p(long addr) |
1da177e4 LT |
515 | { |
516 | /* Is this address in 32bit compat space? */ | |
3ef33e68 | 517 | return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); |
1da177e4 LT |
518 | } |
519 | ||
e8b6d40a | 520 | static __init int __maybe_unused rel_highest(long val) |
1da177e4 LT |
521 | { |
522 | return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; | |
523 | } | |
524 | ||
e8b6d40a | 525 | static __init int __maybe_unused rel_higher(long val) |
1da177e4 LT |
526 | { |
527 | return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; | |
528 | } | |
529 | #endif | |
530 | ||
531 | static __init int rel_hi(long val) | |
532 | { | |
533 | return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; | |
534 | } | |
535 | ||
536 | static __init int rel_lo(long val) | |
537 | { | |
538 | return ((val & 0xffff) ^ 0x8000) - 0x8000; | |
539 | } | |
540 | ||
541 | static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) | |
542 | { | |
766160c2 | 543 | #ifdef CONFIG_64BIT |
1da177e4 LT |
544 | if (!in_compat_space_p(addr)) { |
545 | i_lui(buf, rs, rel_highest(addr)); | |
546 | if (rel_higher(addr)) | |
547 | i_daddiu(buf, rs, rs, rel_higher(addr)); | |
548 | if (rel_hi(addr)) { | |
549 | i_dsll(buf, rs, rs, 16); | |
550 | i_daddiu(buf, rs, rs, rel_hi(addr)); | |
551 | i_dsll(buf, rs, rs, 16); | |
552 | } else | |
553 | i_dsll32(buf, rs, rs, 0); | |
554 | } else | |
555 | #endif | |
556 | i_lui(buf, rs, rel_hi(addr)); | |
557 | } | |
558 | ||
e8b6d40a DR |
559 | static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs, |
560 | long addr) | |
1da177e4 LT |
561 | { |
562 | i_LA_mostly(buf, rs, addr); | |
563 | if (rel_lo(addr)) | |
564 | i_ADDIU(buf, rs, rs, rel_lo(addr)); | |
565 | } | |
566 | ||
567 | /* | |
568 | * handle relocations | |
569 | */ | |
570 | ||
571 | struct reloc { | |
572 | u32 *addr; | |
573 | unsigned int type; | |
574 | enum label_id lab; | |
575 | }; | |
576 | ||
577 | static __init void r_mips_pc16(struct reloc **rel, u32 *addr, | |
578 | enum label_id l) | |
579 | { | |
580 | (*rel)->addr = addr; | |
581 | (*rel)->type = R_MIPS_PC16; | |
582 | (*rel)->lab = l; | |
583 | (*rel)++; | |
584 | } | |
585 | ||
586 | static inline void __resolve_relocs(struct reloc *rel, struct label *lab) | |
587 | { | |
588 | long laddr = (long)lab->addr; | |
589 | long raddr = (long)rel->addr; | |
590 | ||
591 | switch (rel->type) { | |
592 | case R_MIPS_PC16: | |
593 | *rel->addr |= build_bimm(laddr - (raddr + 4)); | |
594 | break; | |
595 | ||
596 | default: | |
597 | panic("Unsupported TLB synthesizer relocation %d", | |
598 | rel->type); | |
599 | } | |
600 | } | |
601 | ||
602 | static __init void resolve_relocs(struct reloc *rel, struct label *lab) | |
603 | { | |
604 | struct label *l; | |
605 | ||
606 | for (; rel->lab != label_invalid; rel++) | |
607 | for (l = lab; l->lab != label_invalid; l++) | |
608 | if (rel->lab == l->lab) | |
609 | __resolve_relocs(rel, l); | |
610 | } | |
611 | ||
612 | static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end, | |
613 | long off) | |
614 | { | |
615 | for (; rel->lab != label_invalid; rel++) | |
616 | if (rel->addr >= first && rel->addr < end) | |
617 | rel->addr += off; | |
618 | } | |
619 | ||
620 | static __init void move_labels(struct label *lab, u32 *first, u32 *end, | |
621 | long off) | |
622 | { | |
623 | for (; lab->lab != label_invalid; lab++) | |
624 | if (lab->addr >= first && lab->addr < end) | |
625 | lab->addr += off; | |
626 | } | |
627 | ||
628 | static __init void copy_handler(struct reloc *rel, struct label *lab, | |
629 | u32 *first, u32 *end, u32 *target) | |
630 | { | |
631 | long off = (long)(target - first); | |
632 | ||
633 | memcpy(target, first, (end - first) * sizeof(u32)); | |
634 | ||
635 | move_relocs(rel, first, end, off); | |
636 | move_labels(lab, first, end, off); | |
637 | } | |
638 | ||
e8b6d40a DR |
639 | static __init int __maybe_unused insn_has_bdelay(struct reloc *rel, |
640 | u32 *addr) | |
1da177e4 LT |
641 | { |
642 | for (; rel->lab != label_invalid; rel++) { | |
643 | if (rel->addr == addr | |
644 | && (rel->type == R_MIPS_PC16 | |
645 | || rel->type == R_MIPS_26)) | |
646 | return 1; | |
647 | } | |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
652 | /* convenience functions for labeled branches */ | |
e8b6d40a | 653 | static void __init __maybe_unused |
1443e483 | 654 | il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) |
1da177e4 LT |
655 | { |
656 | r_mips_pc16(r, *p, l); | |
657 | i_bltz(p, reg, 0); | |
658 | } | |
659 | ||
e8b6d40a DR |
660 | static void __init __maybe_unused il_b(u32 **p, struct reloc **r, |
661 | enum label_id l) | |
1da177e4 LT |
662 | { |
663 | r_mips_pc16(r, *p, l); | |
664 | i_b(p, 0); | |
665 | } | |
666 | ||
1443e483 | 667 | static void __init il_beqz(u32 **p, struct reloc **r, unsigned int reg, |
1da177e4 LT |
668 | enum label_id l) |
669 | { | |
670 | r_mips_pc16(r, *p, l); | |
671 | i_beqz(p, reg, 0); | |
672 | } | |
673 | ||
e8b6d40a | 674 | static void __init __maybe_unused |
1da177e4 LT |
675 | il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) |
676 | { | |
677 | r_mips_pc16(r, *p, l); | |
678 | i_beqzl(p, reg, 0); | |
679 | } | |
680 | ||
1443e483 | 681 | static void __init il_bnez(u32 **p, struct reloc **r, unsigned int reg, |
1da177e4 LT |
682 | enum label_id l) |
683 | { | |
684 | r_mips_pc16(r, *p, l); | |
685 | i_bnez(p, reg, 0); | |
686 | } | |
687 | ||
1443e483 | 688 | static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg, |
1da177e4 LT |
689 | enum label_id l) |
690 | { | |
691 | r_mips_pc16(r, *p, l); | |
692 | i_bgezl(p, reg, 0); | |
693 | } | |
694 | ||
e8b6d40a | 695 | static void __init __maybe_unused |
656be92f AN |
696 | il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) |
697 | { | |
698 | r_mips_pc16(r, *p, l); | |
699 | i_bgez(p, reg, 0); | |
700 | } | |
701 | ||
1da177e4 LT |
702 | /* The only general purpose registers allowed in TLB handlers. */ |
703 | #define K0 26 | |
704 | #define K1 27 | |
705 | ||
706 | /* Some CP0 registers */ | |
41c594ab RB |
707 | #define C0_INDEX 0, 0 |
708 | #define C0_ENTRYLO0 2, 0 | |
709 | #define C0_TCBIND 2, 2 | |
710 | #define C0_ENTRYLO1 3, 0 | |
711 | #define C0_CONTEXT 4, 0 | |
712 | #define C0_BADVADDR 8, 0 | |
713 | #define C0_ENTRYHI 10, 0 | |
714 | #define C0_EPC 14, 0 | |
715 | #define C0_XCONTEXT 20, 0 | |
1da177e4 | 716 | |
875d43e7 | 717 | #ifdef CONFIG_64BIT |
1da177e4 LT |
718 | # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT) |
719 | #else | |
720 | # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT) | |
721 | #endif | |
722 | ||
723 | /* The worst case length of the handler is around 18 instructions for | |
724 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
725 | * Maximum space available is 32 instructions for R3000 and 64 | |
726 | * instructions for R4000. | |
727 | * | |
728 | * We deliberately chose a buffer size of 128, so we won't scribble | |
729 | * over anything important on overflow before we panic. | |
730 | */ | |
731 | static __initdata u32 tlb_handler[128]; | |
732 | ||
733 | /* simply assume worst case size for labels and relocs */ | |
734 | static __initdata struct label labels[128]; | |
735 | static __initdata struct reloc relocs[128]; | |
736 | ||
737 | /* | |
738 | * The R3000 TLB handler is simple. | |
739 | */ | |
740 | static void __init build_r3000_tlb_refill_handler(void) | |
741 | { | |
742 | long pgdc = (long)pgd_current; | |
743 | u32 *p; | |
115f2a44 | 744 | int i; |
1da177e4 LT |
745 | |
746 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
747 | p = tlb_handler; | |
748 | ||
749 | i_mfc0(&p, K0, C0_BADVADDR); | |
750 | i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */ | |
751 | i_lw(&p, K1, rel_lo(pgdc), K1); | |
752 | i_srl(&p, K0, K0, 22); /* load delay */ | |
753 | i_sll(&p, K0, K0, 2); | |
754 | i_addu(&p, K1, K1, K0); | |
755 | i_mfc0(&p, K0, C0_CONTEXT); | |
756 | i_lw(&p, K1, 0, K1); /* cp0 delay */ | |
757 | i_andi(&p, K0, K0, 0xffc); /* load delay */ | |
758 | i_addu(&p, K1, K1, K0); | |
759 | i_lw(&p, K0, 0, K1); | |
760 | i_nop(&p); /* load delay */ | |
761 | i_mtc0(&p, K0, C0_ENTRYLO0); | |
762 | i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ | |
763 | i_tlbwr(&p); /* cp0 delay */ | |
764 | i_jr(&p, K1); | |
765 | i_rfe(&p); /* branch delay */ | |
766 | ||
767 | if (p > tlb_handler + 32) | |
768 | panic("TLB refill handler space exceeded"); | |
769 | ||
115f2a44 TS |
770 | pr_info("Synthesized TLB refill handler (%u instructions).\n", |
771 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 772 | |
115f2a44 TS |
773 | pr_debug("\t.set push\n"); |
774 | pr_debug("\t.set noreorder\n"); | |
775 | for (i = 0; i < (p - tlb_handler); i++) | |
776 | pr_debug("\t.word 0x%08x\n", tlb_handler[i]); | |
777 | pr_debug("\t.set pop\n"); | |
1da177e4 | 778 | |
91b05e67 | 779 | memcpy((void *)ebase, tlb_handler, 0x80); |
1da177e4 LT |
780 | } |
781 | ||
782 | /* | |
783 | * The R4000 TLB handler is much more complicated. We have two | |
784 | * consecutive handler areas with 32 instructions space each. | |
785 | * Since they aren't used at the same time, we can overflow in the | |
786 | * other one.To keep things simple, we first assume linear space, | |
787 | * then we relocate it to the final handler layout as needed. | |
788 | */ | |
789 | static __initdata u32 final_handler[64]; | |
790 | ||
791 | /* | |
792 | * Hazards | |
793 | * | |
794 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
795 | * 2. A timing hazard exists for the TLBP instruction. | |
796 | * | |
797 | * stalling_instruction | |
798 | * TLBP | |
799 | * | |
800 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
801 | * previous instruction. This is not really correct as the stalling instruction | |
802 | * can modify the address used to access the JTLB. The failure symptom is that | |
803 | * the TLBP instruction will use an address created for the stalling instruction | |
804 | * and not the address held in C0_ENHI and thus report the wrong results. | |
805 | * | |
806 | * The software work-around is to not allow the instruction preceding the TLBP | |
807 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
808 | * | |
809 | * Errata 2 will not be fixed. This errata is also on the R5000. | |
810 | * | |
811 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
812 | */ | |
e8b6d40a | 813 | static __init void __maybe_unused build_tlb_probe_entry(u32 **p) |
1da177e4 LT |
814 | { |
815 | switch (current_cpu_data.cputype) { | |
f5b4d956 TS |
816 | /* Found by experiment: R4600 v2.0 needs this, too. */ |
817 | case CPU_R4600: | |
1da177e4 LT |
818 | case CPU_R5000: |
819 | case CPU_R5000A: | |
820 | case CPU_NEVADA: | |
821 | i_nop(p); | |
822 | i_tlbp(p); | |
823 | break; | |
824 | ||
825 | default: | |
826 | i_tlbp(p); | |
827 | break; | |
828 | } | |
829 | } | |
830 | ||
831 | /* | |
832 | * Write random or indexed TLB entry, and care about the hazards from | |
833 | * the preceeding mtc0 and for the following eret. | |
834 | */ | |
835 | enum tlb_write_entry { tlb_random, tlb_indexed }; | |
836 | ||
837 | static __init void build_tlb_write_entry(u32 **p, struct label **l, | |
838 | struct reloc **r, | |
839 | enum tlb_write_entry wmode) | |
840 | { | |
841 | void(*tlbw)(u32 **) = NULL; | |
842 | ||
843 | switch (wmode) { | |
844 | case tlb_random: tlbw = i_tlbwr; break; | |
845 | case tlb_indexed: tlbw = i_tlbwi; break; | |
846 | } | |
847 | ||
848 | switch (current_cpu_data.cputype) { | |
849 | case CPU_R4000PC: | |
850 | case CPU_R4000SC: | |
851 | case CPU_R4000MC: | |
852 | case CPU_R4400PC: | |
853 | case CPU_R4400SC: | |
854 | case CPU_R4400MC: | |
855 | /* | |
856 | * This branch uses up a mtc0 hazard nop slot and saves | |
857 | * two nops after the tlbw instruction. | |
858 | */ | |
859 | il_bgezl(p, r, 0, label_tlbw_hazard); | |
860 | tlbw(p); | |
861 | l_tlbw_hazard(l, *p); | |
862 | i_nop(p); | |
863 | break; | |
864 | ||
865 | case CPU_R4600: | |
866 | case CPU_R4700: | |
867 | case CPU_R5000: | |
868 | case CPU_R5000A: | |
2c93e12c MR |
869 | i_nop(p); |
870 | tlbw(p); | |
871 | i_nop(p); | |
872 | break; | |
873 | ||
874 | case CPU_R4300: | |
1da177e4 LT |
875 | case CPU_5KC: |
876 | case CPU_TX49XX: | |
877 | case CPU_AU1000: | |
878 | case CPU_AU1100: | |
879 | case CPU_AU1500: | |
880 | case CPU_AU1550: | |
e3ad1c23 | 881 | case CPU_AU1200: |
bdf21b18 | 882 | case CPU_PR4450: |
1da177e4 LT |
883 | i_nop(p); |
884 | tlbw(p); | |
885 | break; | |
886 | ||
887 | case CPU_R10000: | |
888 | case CPU_R12000: | |
44d921b2 | 889 | case CPU_R14000: |
1da177e4 LT |
890 | case CPU_4KC: |
891 | case CPU_SB1: | |
93ce2f52 | 892 | case CPU_SB1A: |
1da177e4 LT |
893 | case CPU_4KSC: |
894 | case CPU_20KC: | |
895 | case CPU_25KF: | |
896 | tlbw(p); | |
897 | break; | |
898 | ||
899 | case CPU_NEVADA: | |
900 | i_nop(p); /* QED specifies 2 nops hazard */ | |
901 | /* | |
902 | * This branch uses up a mtc0 hazard nop slot and saves | |
903 | * a nop after the tlbw instruction. | |
904 | */ | |
905 | il_bgezl(p, r, 0, label_tlbw_hazard); | |
906 | tlbw(p); | |
907 | l_tlbw_hazard(l, *p); | |
908 | break; | |
909 | ||
910 | case CPU_RM7000: | |
911 | i_nop(p); | |
912 | i_nop(p); | |
913 | i_nop(p); | |
914 | i_nop(p); | |
915 | tlbw(p); | |
916 | break; | |
917 | ||
918 | case CPU_4KEC: | |
919 | case CPU_24K: | |
bbc7f22f | 920 | case CPU_34K: |
c620953c | 921 | case CPU_74K: |
1da177e4 LT |
922 | i_ehb(p); |
923 | tlbw(p); | |
924 | break; | |
925 | ||
926 | case CPU_RM9000: | |
927 | /* | |
928 | * When the JTLB is updated by tlbwi or tlbwr, a subsequent | |
929 | * use of the JTLB for instructions should not occur for 4 | |
930 | * cpu cycles and use for data translations should not occur | |
931 | * for 3 cpu cycles. | |
932 | */ | |
933 | i_ssnop(p); | |
934 | i_ssnop(p); | |
935 | i_ssnop(p); | |
936 | i_ssnop(p); | |
937 | tlbw(p); | |
938 | i_ssnop(p); | |
939 | i_ssnop(p); | |
940 | i_ssnop(p); | |
941 | i_ssnop(p); | |
942 | break; | |
943 | ||
944 | case CPU_VR4111: | |
945 | case CPU_VR4121: | |
946 | case CPU_VR4122: | |
947 | case CPU_VR4181: | |
948 | case CPU_VR4181A: | |
949 | i_nop(p); | |
950 | i_nop(p); | |
951 | tlbw(p); | |
952 | i_nop(p); | |
953 | i_nop(p); | |
954 | break; | |
955 | ||
956 | case CPU_VR4131: | |
957 | case CPU_VR4133: | |
7623debf | 958 | case CPU_R5432: |
1da177e4 LT |
959 | i_nop(p); |
960 | i_nop(p); | |
961 | tlbw(p); | |
962 | break; | |
963 | ||
964 | default: | |
965 | panic("No TLB refill handler yet (CPU type: %d)", | |
966 | current_cpu_data.cputype); | |
967 | break; | |
968 | } | |
969 | } | |
970 | ||
875d43e7 | 971 | #ifdef CONFIG_64BIT |
1da177e4 LT |
972 | /* |
973 | * TMP and PTR are scratch. | |
974 | * TMP will be clobbered, PTR will hold the pmd entry. | |
975 | */ | |
976 | static __init void | |
977 | build_get_pmde64(u32 **p, struct label **l, struct reloc **r, | |
978 | unsigned int tmp, unsigned int ptr) | |
979 | { | |
980 | long pgdc = (long)pgd_current; | |
981 | ||
982 | /* | |
983 | * The vmalloc handling is not in the hotpath. | |
984 | */ | |
985 | i_dmfc0(p, tmp, C0_BADVADDR); | |
656be92f AN |
986 | #ifdef MODULE_START |
987 | il_bltz(p, r, tmp, label_module_alloc); | |
988 | #else | |
1da177e4 | 989 | il_bltz(p, r, tmp, label_vmalloc); |
656be92f | 990 | #endif |
1da177e4 LT |
991 | /* No i_nop needed here, since the next insn doesn't touch TMP. */ |
992 | ||
993 | #ifdef CONFIG_SMP | |
41c594ab RB |
994 | # ifdef CONFIG_MIPS_MT_SMTC |
995 | /* | |
996 | * SMTC uses TCBind value as "CPU" index | |
997 | */ | |
998 | i_mfc0(p, ptr, C0_TCBIND); | |
999 | i_dsrl(p, ptr, ptr, 19); | |
1000 | # else | |
1da177e4 | 1001 | /* |
1b3a6e97 | 1002 | * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 |
1da177e4 LT |
1003 | * stored in CONTEXT. |
1004 | */ | |
1b3a6e97 TS |
1005 | i_dmfc0(p, ptr, C0_CONTEXT); |
1006 | i_dsrl(p, ptr, ptr, 23); | |
41c594ab | 1007 | #endif |
1b3a6e97 TS |
1008 | i_LA_mostly(p, tmp, pgdc); |
1009 | i_daddu(p, ptr, ptr, tmp); | |
1010 | i_dmfc0(p, tmp, C0_BADVADDR); | |
1011 | i_ld(p, ptr, rel_lo(pgdc), ptr); | |
1da177e4 LT |
1012 | #else |
1013 | i_LA_mostly(p, ptr, pgdc); | |
1014 | i_ld(p, ptr, rel_lo(pgdc), ptr); | |
1015 | #endif | |
1016 | ||
1017 | l_vmalloc_done(l, *p); | |
242954b5 RB |
1018 | |
1019 | if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */ | |
1020 | i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); | |
1021 | else | |
1022 | i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32); | |
1023 | ||
1da177e4 LT |
1024 | i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); |
1025 | i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1026 | i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ | |
1027 | i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
1028 | i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ | |
1029 | i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); | |
1030 | i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
1031 | } | |
1032 | ||
1033 | /* | |
1034 | * BVADDR is the faulting address, PTR is scratch. | |
1035 | * PTR will hold the pgd for vmalloc. | |
1036 | */ | |
1037 | static __init void | |
1038 | build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, | |
1039 | unsigned int bvaddr, unsigned int ptr) | |
1040 | { | |
1041 | long swpd = (long)swapper_pg_dir; | |
1042 | ||
656be92f AN |
1043 | #ifdef MODULE_START |
1044 | long modd = (long)module_pg_dir; | |
1045 | ||
1046 | l_module_alloc(l, *p); | |
1047 | /* | |
1048 | * Assumption: | |
1049 | * VMALLOC_START >= 0xc000000000000000UL | |
1050 | * MODULE_START >= 0xe000000000000000UL | |
1051 | */ | |
1052 | i_SLL(p, ptr, bvaddr, 2); | |
1053 | il_bgez(p, r, ptr, label_vmalloc); | |
1054 | ||
1055 | if (in_compat_space_p(MODULE_START) && !rel_lo(MODULE_START)) { | |
1056 | i_lui(p, ptr, rel_hi(MODULE_START)); /* delay slot */ | |
1057 | } else { | |
1058 | /* unlikely configuration */ | |
1059 | i_nop(p); /* delay slot */ | |
1060 | i_LA(p, ptr, MODULE_START); | |
1061 | } | |
1062 | i_dsubu(p, bvaddr, bvaddr, ptr); | |
1063 | ||
1064 | if (in_compat_space_p(modd) && !rel_lo(modd)) { | |
1065 | il_b(p, r, label_vmalloc_done); | |
1066 | i_lui(p, ptr, rel_hi(modd)); | |
1067 | } else { | |
1068 | i_LA_mostly(p, ptr, modd); | |
1069 | il_b(p, r, label_vmalloc_done); | |
1070 | i_daddiu(p, ptr, ptr, rel_lo(modd)); | |
1071 | } | |
1072 | ||
1073 | l_vmalloc(l, *p); | |
1074 | if (in_compat_space_p(MODULE_START) && !rel_lo(MODULE_START) && | |
1075 | MODULE_START << 32 == VMALLOC_START) | |
1076 | i_dsll32(p, ptr, ptr, 0); /* typical case */ | |
1077 | else | |
1078 | i_LA(p, ptr, VMALLOC_START); | |
1079 | #else | |
1da177e4 LT |
1080 | l_vmalloc(l, *p); |
1081 | i_LA(p, ptr, VMALLOC_START); | |
656be92f | 1082 | #endif |
1da177e4 LT |
1083 | i_dsubu(p, bvaddr, bvaddr, ptr); |
1084 | ||
1085 | if (in_compat_space_p(swpd) && !rel_lo(swpd)) { | |
1086 | il_b(p, r, label_vmalloc_done); | |
1087 | i_lui(p, ptr, rel_hi(swpd)); | |
1088 | } else { | |
1089 | i_LA_mostly(p, ptr, swpd); | |
1090 | il_b(p, r, label_vmalloc_done); | |
1091 | i_daddiu(p, ptr, ptr, rel_lo(swpd)); | |
1092 | } | |
1093 | } | |
1094 | ||
875d43e7 | 1095 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
1096 | |
1097 | /* | |
1098 | * TMP and PTR are scratch. | |
1099 | * TMP will be clobbered, PTR will hold the pgd entry. | |
1100 | */ | |
e8b6d40a | 1101 | static __init void __maybe_unused |
1da177e4 LT |
1102 | build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
1103 | { | |
1104 | long pgdc = (long)pgd_current; | |
1105 | ||
1106 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ | |
1107 | #ifdef CONFIG_SMP | |
41c594ab RB |
1108 | #ifdef CONFIG_MIPS_MT_SMTC |
1109 | /* | |
1110 | * SMTC uses TCBind value as "CPU" index | |
1111 | */ | |
1112 | i_mfc0(p, ptr, C0_TCBIND); | |
1113 | i_LA_mostly(p, tmp, pgdc); | |
1114 | i_srl(p, ptr, ptr, 19); | |
1115 | #else | |
1116 | /* | |
1117 | * smp_processor_id() << 3 is stored in CONTEXT. | |
1118 | */ | |
1da177e4 LT |
1119 | i_mfc0(p, ptr, C0_CONTEXT); |
1120 | i_LA_mostly(p, tmp, pgdc); | |
1121 | i_srl(p, ptr, ptr, 23); | |
41c594ab | 1122 | #endif |
1da177e4 LT |
1123 | i_addu(p, ptr, tmp, ptr); |
1124 | #else | |
1125 | i_LA_mostly(p, ptr, pgdc); | |
1126 | #endif | |
1127 | i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ | |
1128 | i_lw(p, ptr, rel_lo(pgdc), ptr); | |
1129 | i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ | |
1130 | i_sll(p, tmp, tmp, PGD_T_LOG2); | |
1131 | i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1132 | } | |
1133 | ||
875d43e7 | 1134 | #endif /* !CONFIG_64BIT */ |
1da177e4 LT |
1135 | |
1136 | static __init void build_adjust_context(u32 **p, unsigned int ctx) | |
1137 | { | |
242954b5 | 1138 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1da177e4 LT |
1139 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
1140 | ||
1141 | switch (current_cpu_data.cputype) { | |
1142 | case CPU_VR41XX: | |
1143 | case CPU_VR4111: | |
1144 | case CPU_VR4121: | |
1145 | case CPU_VR4122: | |
1146 | case CPU_VR4131: | |
1147 | case CPU_VR4181: | |
1148 | case CPU_VR4181A: | |
1149 | case CPU_VR4133: | |
1150 | shift += 2; | |
1151 | break; | |
1152 | ||
1153 | default: | |
1154 | break; | |
1155 | } | |
1156 | ||
1157 | if (shift) | |
1158 | i_SRL(p, ctx, ctx, shift); | |
1159 | i_andi(p, ctx, ctx, mask); | |
1160 | } | |
1161 | ||
1162 | static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) | |
1163 | { | |
1164 | /* | |
1165 | * Bug workaround for the Nevada. It seems as if under certain | |
1166 | * circumstances the move from cp0_context might produce a | |
1167 | * bogus result when the mfc0 instruction and its consumer are | |
1168 | * in a different cacheline or a load instruction, probably any | |
1169 | * memory reference, is between them. | |
1170 | */ | |
1171 | switch (current_cpu_data.cputype) { | |
1172 | case CPU_NEVADA: | |
1173 | i_LW(p, ptr, 0, ptr); | |
1174 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1175 | break; | |
1176 | ||
1177 | default: | |
1178 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1179 | i_LW(p, ptr, 0, ptr); | |
1180 | break; | |
1181 | } | |
1182 | ||
1183 | build_adjust_context(p, tmp); | |
1184 | i_ADDU(p, ptr, ptr, tmp); /* add in offset */ | |
1185 | } | |
1186 | ||
1187 | static __init void build_update_entries(u32 **p, unsigned int tmp, | |
1188 | unsigned int ptep) | |
1189 | { | |
1190 | /* | |
1191 | * 64bit address support (36bit on a 32bit CPU) in a 32bit | |
1192 | * Kernel is a special case. Only a few CPUs use it. | |
1193 | */ | |
1194 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
1195 | if (cpu_has_64bits) { | |
1196 | i_ld(p, tmp, 0, ptep); /* get even pte */ | |
1197 | i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1198 | i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ | |
1199 | i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
1200 | i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ | |
1201 | i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1202 | } else { | |
1203 | int pte_off_even = sizeof(pte_t) / 2; | |
1204 | int pte_off_odd = pte_off_even + sizeof(pte_t); | |
1205 | ||
1206 | /* The pte entries are pre-shifted */ | |
1207 | i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ | |
1208 | i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
1209 | i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ | |
1210 | i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1211 | } | |
1212 | #else | |
1213 | i_LW(p, tmp, 0, ptep); /* get even pte */ | |
1214 | i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1215 | if (r45k_bvahwbug()) | |
1216 | build_tlb_probe_entry(p); | |
1217 | i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ | |
1218 | if (r4k_250MHZhwbug()) | |
1219 | i_mtc0(p, 0, C0_ENTRYLO0); | |
1220 | i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
1221 | i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ | |
1222 | if (r45k_bvahwbug()) | |
1223 | i_mfc0(p, tmp, C0_INDEX); | |
1224 | if (r4k_250MHZhwbug()) | |
1225 | i_mtc0(p, 0, C0_ENTRYLO1); | |
1226 | i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1227 | #endif | |
1228 | } | |
1229 | ||
1230 | static void __init build_r4000_tlb_refill_handler(void) | |
1231 | { | |
1232 | u32 *p = tlb_handler; | |
1233 | struct label *l = labels; | |
1234 | struct reloc *r = relocs; | |
1235 | u32 *f; | |
1236 | unsigned int final_len; | |
115f2a44 | 1237 | int i; |
1da177e4 LT |
1238 | |
1239 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
1240 | memset(labels, 0, sizeof(labels)); | |
1241 | memset(relocs, 0, sizeof(relocs)); | |
1242 | memset(final_handler, 0, sizeof(final_handler)); | |
1243 | ||
1244 | /* | |
1245 | * create the plain linear handler | |
1246 | */ | |
1247 | if (bcm1250_m3_war()) { | |
1248 | i_MFC0(&p, K0, C0_BADVADDR); | |
1249 | i_MFC0(&p, K1, C0_ENTRYHI); | |
1250 | i_xor(&p, K0, K0, K1); | |
1251 | i_SRL(&p, K0, K0, PAGE_SHIFT + 1); | |
1252 | il_bnez(&p, &r, K0, label_leave); | |
1253 | /* No need for i_nop */ | |
1254 | } | |
1255 | ||
875d43e7 | 1256 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1257 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
1258 | #else | |
1259 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ | |
1260 | #endif | |
1261 | ||
1262 | build_get_ptep(&p, K0, K1); | |
1263 | build_update_entries(&p, K0, K1); | |
1264 | build_tlb_write_entry(&p, &l, &r, tlb_random); | |
1265 | l_leave(&l, p); | |
1266 | i_eret(&p); /* return from trap */ | |
1267 | ||
875d43e7 | 1268 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1269 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); |
1270 | #endif | |
1271 | ||
1272 | /* | |
1273 | * Overflow check: For the 64bit handler, we need at least one | |
1274 | * free instruction slot for the wrap-around branch. In worst | |
1275 | * case, if the intended insertion point is a delay slot, we | |
4b3f686d | 1276 | * need three, with the second nop'ed and the third being |
1da177e4 LT |
1277 | * unused. |
1278 | */ | |
875d43e7 | 1279 | #ifdef CONFIG_32BIT |
1da177e4 LT |
1280 | if ((p - tlb_handler) > 64) |
1281 | panic("TLB refill handler space exceeded"); | |
1282 | #else | |
1283 | if (((p - tlb_handler) > 63) | |
1284 | || (((p - tlb_handler) > 61) | |
1285 | && insn_has_bdelay(relocs, tlb_handler + 29))) | |
1286 | panic("TLB refill handler space exceeded"); | |
1287 | #endif | |
1288 | ||
1289 | /* | |
1290 | * Now fold the handler in the TLB refill handler space. | |
1291 | */ | |
875d43e7 | 1292 | #ifdef CONFIG_32BIT |
1da177e4 LT |
1293 | f = final_handler; |
1294 | /* Simplest case, just copy the handler. */ | |
1295 | copy_handler(relocs, labels, tlb_handler, p, f); | |
1296 | final_len = p - tlb_handler; | |
875d43e7 | 1297 | #else /* CONFIG_64BIT */ |
1da177e4 LT |
1298 | f = final_handler + 32; |
1299 | if ((p - tlb_handler) <= 32) { | |
1300 | /* Just copy the handler. */ | |
1301 | copy_handler(relocs, labels, tlb_handler, p, f); | |
1302 | final_len = p - tlb_handler; | |
1303 | } else { | |
1304 | u32 *split = tlb_handler + 30; | |
1305 | ||
1306 | /* | |
1307 | * Find the split point. | |
1308 | */ | |
1309 | if (insn_has_bdelay(relocs, split - 1)) | |
1310 | split--; | |
1311 | ||
1312 | /* Copy first part of the handler. */ | |
1313 | copy_handler(relocs, labels, tlb_handler, split, f); | |
1314 | f += split - tlb_handler; | |
1315 | ||
1316 | /* Insert branch. */ | |
1317 | l_split(&l, final_handler); | |
1318 | il_b(&f, &r, label_split); | |
1319 | if (insn_has_bdelay(relocs, split)) | |
1320 | i_nop(&f); | |
1321 | else { | |
1322 | copy_handler(relocs, labels, split, split + 1, f); | |
1323 | move_labels(labels, f, f + 1, -1); | |
1324 | f++; | |
1325 | split++; | |
1326 | } | |
1327 | ||
1328 | /* Copy the rest of the handler. */ | |
1329 | copy_handler(relocs, labels, split, p, final_handler); | |
1330 | final_len = (f - (final_handler + 32)) + (p - split); | |
1331 | } | |
875d43e7 | 1332 | #endif /* CONFIG_64BIT */ |
1da177e4 LT |
1333 | |
1334 | resolve_relocs(relocs, labels); | |
115f2a44 TS |
1335 | pr_info("Synthesized TLB refill handler (%u instructions).\n", |
1336 | final_len); | |
1da177e4 | 1337 | |
115f2a44 | 1338 | f = final_handler; |
4c0a2d42 | 1339 | #ifdef CONFIG_64BIT |
115f2a44 TS |
1340 | if (final_len > 32) |
1341 | final_len = 64; | |
1342 | else | |
1343 | f = final_handler + 32; | |
4c0a2d42 | 1344 | #endif /* CONFIG_64BIT */ |
115f2a44 TS |
1345 | pr_debug("\t.set push\n"); |
1346 | pr_debug("\t.set noreorder\n"); | |
1347 | for (i = 0; i < final_len; i++) | |
1348 | pr_debug("\t.word 0x%08x\n", f[i]); | |
1349 | pr_debug("\t.set pop\n"); | |
1da177e4 | 1350 | |
91b05e67 | 1351 | memcpy((void *)ebase, final_handler, 0x100); |
1da177e4 LT |
1352 | } |
1353 | ||
1354 | /* | |
1355 | * TLB load/store/modify handlers. | |
1356 | * | |
1357 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
1358 | * do_page_fault remains normal asm. | |
1359 | */ | |
1360 | extern void tlb_do_page_fault_0(void); | |
1361 | extern void tlb_do_page_fault_1(void); | |
1362 | ||
1363 | #define __tlb_handler_align \ | |
1364 | __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT))) | |
1365 | ||
1366 | /* | |
1367 | * 128 instructions for the fastpath handler is generous and should | |
1368 | * never be exceeded. | |
1369 | */ | |
1370 | #define FASTPATH_SIZE 128 | |
1371 | ||
1372 | u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE]; | |
1373 | u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE]; | |
1374 | u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE]; | |
1375 | ||
1376 | static void __init | |
63b2d2f4 | 1377 | iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
1378 | { |
1379 | #ifdef CONFIG_SMP | |
1380 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1381 | if (cpu_has_64bits) | |
63b2d2f4 | 1382 | i_lld(p, pte, 0, ptr); |
1da177e4 LT |
1383 | else |
1384 | # endif | |
63b2d2f4 | 1385 | i_LL(p, pte, 0, ptr); |
1da177e4 LT |
1386 | #else |
1387 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1388 | if (cpu_has_64bits) | |
63b2d2f4 | 1389 | i_ld(p, pte, 0, ptr); |
1da177e4 LT |
1390 | else |
1391 | # endif | |
63b2d2f4 | 1392 | i_LW(p, pte, 0, ptr); |
1da177e4 LT |
1393 | #endif |
1394 | } | |
1395 | ||
1396 | static void __init | |
63b2d2f4 TS |
1397 | iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr, |
1398 | unsigned int mode) | |
1da177e4 | 1399 | { |
63b2d2f4 TS |
1400 | #ifdef CONFIG_64BIT_PHYS_ADDR |
1401 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); | |
1402 | #endif | |
1403 | ||
1404 | i_ori(p, pte, pte, mode); | |
1da177e4 LT |
1405 | #ifdef CONFIG_SMP |
1406 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1407 | if (cpu_has_64bits) | |
63b2d2f4 | 1408 | i_scd(p, pte, 0, ptr); |
1da177e4 LT |
1409 | else |
1410 | # endif | |
63b2d2f4 | 1411 | i_SC(p, pte, 0, ptr); |
1da177e4 LT |
1412 | |
1413 | if (r10000_llsc_war()) | |
1414 | il_beqzl(p, r, pte, label_smp_pgtable_change); | |
1415 | else | |
1416 | il_beqz(p, r, pte, label_smp_pgtable_change); | |
1417 | ||
1418 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1419 | if (!cpu_has_64bits) { | |
1420 | /* no i_nop needed */ | |
1421 | i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
63b2d2f4 | 1422 | i_ori(p, pte, pte, hwmode); |
1da177e4 LT |
1423 | i_sc(p, pte, sizeof(pte_t) / 2, ptr); |
1424 | il_beqz(p, r, pte, label_smp_pgtable_change); | |
1425 | /* no i_nop needed */ | |
1426 | i_lw(p, pte, 0, ptr); | |
1427 | } else | |
1428 | i_nop(p); | |
1429 | # else | |
1430 | i_nop(p); | |
1431 | # endif | |
1432 | #else | |
1433 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1434 | if (cpu_has_64bits) | |
63b2d2f4 | 1435 | i_sd(p, pte, 0, ptr); |
1da177e4 LT |
1436 | else |
1437 | # endif | |
63b2d2f4 | 1438 | i_SW(p, pte, 0, ptr); |
1da177e4 LT |
1439 | |
1440 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
1441 | if (!cpu_has_64bits) { | |
1442 | i_lw(p, pte, sizeof(pte_t) / 2, ptr); | |
63b2d2f4 | 1443 | i_ori(p, pte, pte, hwmode); |
1da177e4 LT |
1444 | i_sw(p, pte, sizeof(pte_t) / 2, ptr); |
1445 | i_lw(p, pte, 0, ptr); | |
1446 | } | |
1447 | # endif | |
1448 | #endif | |
1449 | } | |
1450 | ||
1451 | /* | |
1452 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
1453 | * the page table where this PTE is located, PTE will be re-loaded | |
1454 | * with it's original value. | |
1455 | */ | |
1456 | static void __init | |
1457 | build_pte_present(u32 **p, struct label **l, struct reloc **r, | |
1458 | unsigned int pte, unsigned int ptr, enum label_id lid) | |
1459 | { | |
1460 | i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); | |
1461 | i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); | |
1462 | il_bnez(p, r, pte, lid); | |
63b2d2f4 | 1463 | iPTE_LW(p, l, pte, ptr); |
1da177e4 LT |
1464 | } |
1465 | ||
1466 | /* Make PTE valid, store result in PTR. */ | |
1467 | static void __init | |
1468 | build_make_valid(u32 **p, struct reloc **r, unsigned int pte, | |
1469 | unsigned int ptr) | |
1470 | { | |
63b2d2f4 TS |
1471 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
1472 | ||
1473 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1474 | } |
1475 | ||
1476 | /* | |
1477 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
1478 | * restore PTE with value from PTR when done. | |
1479 | */ | |
1480 | static void __init | |
1481 | build_pte_writable(u32 **p, struct label **l, struct reloc **r, | |
1482 | unsigned int pte, unsigned int ptr, enum label_id lid) | |
1483 | { | |
1484 | i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
1485 | i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
1486 | il_bnez(p, r, pte, lid); | |
63b2d2f4 | 1487 | iPTE_LW(p, l, pte, ptr); |
1da177e4 LT |
1488 | } |
1489 | ||
1490 | /* Make PTE writable, update software status bits as well, then store | |
1491 | * at PTR. | |
1492 | */ | |
1493 | static void __init | |
1494 | build_make_write(u32 **p, struct reloc **r, unsigned int pte, | |
1495 | unsigned int ptr) | |
1496 | { | |
63b2d2f4 TS |
1497 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
1498 | | _PAGE_DIRTY); | |
1499 | ||
1500 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
1501 | } |
1502 | ||
1503 | /* | |
1504 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
1505 | * restore PTE with value from PTR when done. | |
1506 | */ | |
1507 | static void __init | |
1508 | build_pte_modifiable(u32 **p, struct label **l, struct reloc **r, | |
1509 | unsigned int pte, unsigned int ptr, enum label_id lid) | |
1510 | { | |
1511 | i_andi(p, pte, pte, _PAGE_WRITE); | |
1512 | il_beqz(p, r, pte, lid); | |
63b2d2f4 | 1513 | iPTE_LW(p, l, pte, ptr); |
1da177e4 LT |
1514 | } |
1515 | ||
1516 | /* | |
1517 | * R3000 style TLB load/store/modify handlers. | |
1518 | */ | |
1519 | ||
fded2e50 MR |
1520 | /* |
1521 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
1522 | * Then it returns. | |
1523 | */ | |
1da177e4 | 1524 | static void __init |
fded2e50 | 1525 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 1526 | { |
fded2e50 MR |
1527 | i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1528 | i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
1529 | i_tlbwi(p); | |
1530 | i_jr(p, tmp); | |
1531 | i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1532 | } |
1533 | ||
1534 | /* | |
fded2e50 MR |
1535 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
1536 | * or tlbwr as appropriate. This is because the index register | |
1537 | * may have the probe fail bit set as a result of a trap on a | |
1538 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 LT |
1539 | */ |
1540 | static void __init | |
fded2e50 MR |
1541 | build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r, |
1542 | unsigned int pte, unsigned int tmp) | |
1da177e4 LT |
1543 | { |
1544 | i_mfc0(p, tmp, C0_INDEX); | |
fded2e50 MR |
1545 | i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1546 | il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
1547 | i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
1548 | i_tlbwi(p); /* cp0 delay */ | |
1549 | i_jr(p, tmp); | |
1550 | i_rfe(p); /* branch delay */ | |
1da177e4 | 1551 | l_r3000_write_probe_fail(l, *p); |
fded2e50 MR |
1552 | i_tlbwr(p); /* cp0 delay */ |
1553 | i_jr(p, tmp); | |
1554 | i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1555 | } |
1556 | ||
1557 | static void __init | |
1558 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, | |
1559 | unsigned int ptr) | |
1560 | { | |
1561 | long pgdc = (long)pgd_current; | |
1562 | ||
1563 | i_mfc0(p, pte, C0_BADVADDR); | |
1564 | i_lui(p, ptr, rel_hi(pgdc)); /* cp0 delay */ | |
1565 | i_lw(p, ptr, rel_lo(pgdc), ptr); | |
1566 | i_srl(p, pte, pte, 22); /* load delay */ | |
1567 | i_sll(p, pte, pte, 2); | |
1568 | i_addu(p, ptr, ptr, pte); | |
1569 | i_mfc0(p, pte, C0_CONTEXT); | |
1570 | i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
1571 | i_andi(p, pte, pte, 0xffc); /* load delay */ | |
1572 | i_addu(p, ptr, ptr, pte); | |
1573 | i_lw(p, pte, 0, ptr); | |
fded2e50 | 1574 | i_tlbp(p); /* load delay */ |
1da177e4 LT |
1575 | } |
1576 | ||
1577 | static void __init build_r3000_tlb_load_handler(void) | |
1578 | { | |
1579 | u32 *p = handle_tlbl; | |
1580 | struct label *l = labels; | |
1581 | struct reloc *r = relocs; | |
115f2a44 | 1582 | int i; |
1da177e4 LT |
1583 | |
1584 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1585 | memset(labels, 0, sizeof(labels)); | |
1586 | memset(relocs, 0, sizeof(relocs)); | |
1587 | ||
1588 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
1589 | build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); | |
d925c262 | 1590 | i_nop(&p); /* load delay */ |
1da177e4 | 1591 | build_make_valid(&p, &r, K0, K1); |
fded2e50 | 1592 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 LT |
1593 | |
1594 | l_nopage_tlbl(&l, p); | |
1595 | i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1596 | i_nop(&p); | |
1597 | ||
1598 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1599 | panic("TLB load handler fastpath space exceeded"); | |
1600 | ||
1601 | resolve_relocs(relocs, labels); | |
115f2a44 TS |
1602 | pr_info("Synthesized TLB load handler fastpath (%u instructions).\n", |
1603 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1604 | |
115f2a44 TS |
1605 | pr_debug("\t.set push\n"); |
1606 | pr_debug("\t.set noreorder\n"); | |
1607 | for (i = 0; i < (p - handle_tlbl); i++) | |
1608 | pr_debug("\t.word 0x%08x\n", handle_tlbl[i]); | |
1609 | pr_debug("\t.set pop\n"); | |
1da177e4 LT |
1610 | } |
1611 | ||
1612 | static void __init build_r3000_tlb_store_handler(void) | |
1613 | { | |
1614 | u32 *p = handle_tlbs; | |
1615 | struct label *l = labels; | |
1616 | struct reloc *r = relocs; | |
115f2a44 | 1617 | int i; |
1da177e4 LT |
1618 | |
1619 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1620 | memset(labels, 0, sizeof(labels)); | |
1621 | memset(relocs, 0, sizeof(relocs)); | |
1622 | ||
1623 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
1624 | build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); | |
d925c262 | 1625 | i_nop(&p); /* load delay */ |
1da177e4 | 1626 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1627 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 LT |
1628 | |
1629 | l_nopage_tlbs(&l, p); | |
1630 | i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1631 | i_nop(&p); | |
1632 | ||
1633 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1634 | panic("TLB store handler fastpath space exceeded"); | |
1635 | ||
1636 | resolve_relocs(relocs, labels); | |
115f2a44 TS |
1637 | pr_info("Synthesized TLB store handler fastpath (%u instructions).\n", |
1638 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1639 | |
115f2a44 TS |
1640 | pr_debug("\t.set push\n"); |
1641 | pr_debug("\t.set noreorder\n"); | |
1642 | for (i = 0; i < (p - handle_tlbs); i++) | |
1643 | pr_debug("\t.word 0x%08x\n", handle_tlbs[i]); | |
1644 | pr_debug("\t.set pop\n"); | |
1da177e4 LT |
1645 | } |
1646 | ||
1647 | static void __init build_r3000_tlb_modify_handler(void) | |
1648 | { | |
1649 | u32 *p = handle_tlbm; | |
1650 | struct label *l = labels; | |
1651 | struct reloc *r = relocs; | |
115f2a44 | 1652 | int i; |
1da177e4 LT |
1653 | |
1654 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1655 | memset(labels, 0, sizeof(labels)); | |
1656 | memset(relocs, 0, sizeof(relocs)); | |
1657 | ||
1658 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
1659 | build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); | |
d925c262 | 1660 | i_nop(&p); /* load delay */ |
1da177e4 | 1661 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1662 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
1da177e4 LT |
1663 | |
1664 | l_nopage_tlbm(&l, p); | |
1665 | i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1666 | i_nop(&p); | |
1667 | ||
1668 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1669 | panic("TLB modify handler fastpath space exceeded"); | |
1670 | ||
1671 | resolve_relocs(relocs, labels); | |
115f2a44 TS |
1672 | pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n", |
1673 | (unsigned int)(p - handle_tlbm)); | |
1da177e4 | 1674 | |
115f2a44 TS |
1675 | pr_debug("\t.set push\n"); |
1676 | pr_debug("\t.set noreorder\n"); | |
1677 | for (i = 0; i < (p - handle_tlbm); i++) | |
1678 | pr_debug("\t.word 0x%08x\n", handle_tlbm[i]); | |
1679 | pr_debug("\t.set pop\n"); | |
1da177e4 LT |
1680 | } |
1681 | ||
1682 | /* | |
1683 | * R4000 style TLB load/store/modify handlers. | |
1684 | */ | |
1685 | static void __init | |
1686 | build_r4000_tlbchange_handler_head(u32 **p, struct label **l, | |
1687 | struct reloc **r, unsigned int pte, | |
1688 | unsigned int ptr) | |
1689 | { | |
875d43e7 | 1690 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1691 | build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ |
1692 | #else | |
1693 | build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ | |
1694 | #endif | |
1695 | ||
1696 | i_MFC0(p, pte, C0_BADVADDR); | |
1697 | i_LW(p, ptr, 0, ptr); | |
1698 | i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); | |
1699 | i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); | |
1700 | i_ADDU(p, ptr, ptr, pte); | |
1701 | ||
1702 | #ifdef CONFIG_SMP | |
1703 | l_smp_pgtable_change(l, *p); | |
1704 | # endif | |
63b2d2f4 | 1705 | iPTE_LW(p, l, pte, ptr); /* get even pte */ |
1da177e4 LT |
1706 | build_tlb_probe_entry(p); |
1707 | } | |
1708 | ||
1709 | static void __init | |
1710 | build_r4000_tlbchange_handler_tail(u32 **p, struct label **l, | |
1711 | struct reloc **r, unsigned int tmp, | |
1712 | unsigned int ptr) | |
1713 | { | |
1714 | i_ori(p, ptr, ptr, sizeof(pte_t)); | |
1715 | i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1716 | build_update_entries(p, tmp, ptr); | |
1717 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
1718 | l_leave(l, *p); | |
1719 | i_eret(p); /* return from trap */ | |
1720 | ||
875d43e7 | 1721 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1722 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr); |
1723 | #endif | |
1724 | } | |
1725 | ||
1726 | static void __init build_r4000_tlb_load_handler(void) | |
1727 | { | |
1728 | u32 *p = handle_tlbl; | |
1729 | struct label *l = labels; | |
1730 | struct reloc *r = relocs; | |
115f2a44 | 1731 | int i; |
1da177e4 LT |
1732 | |
1733 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1734 | memset(labels, 0, sizeof(labels)); | |
1735 | memset(relocs, 0, sizeof(relocs)); | |
1736 | ||
1737 | if (bcm1250_m3_war()) { | |
1738 | i_MFC0(&p, K0, C0_BADVADDR); | |
1739 | i_MFC0(&p, K1, C0_ENTRYHI); | |
1740 | i_xor(&p, K0, K0, K1); | |
1741 | i_SRL(&p, K0, K0, PAGE_SHIFT + 1); | |
1742 | il_bnez(&p, &r, K0, label_leave); | |
1743 | /* No need for i_nop */ | |
1744 | } | |
1745 | ||
1746 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
1747 | build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); | |
1748 | build_make_valid(&p, &r, K0, K1); | |
1749 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1750 | ||
1751 | l_nopage_tlbl(&l, p); | |
1752 | i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1753 | i_nop(&p); | |
1754 | ||
1755 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1756 | panic("TLB load handler fastpath space exceeded"); | |
1757 | ||
1758 | resolve_relocs(relocs, labels); | |
115f2a44 TS |
1759 | pr_info("Synthesized TLB load handler fastpath (%u instructions).\n", |
1760 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1761 | |
115f2a44 TS |
1762 | pr_debug("\t.set push\n"); |
1763 | pr_debug("\t.set noreorder\n"); | |
1764 | for (i = 0; i < (p - handle_tlbl); i++) | |
1765 | pr_debug("\t.word 0x%08x\n", handle_tlbl[i]); | |
1766 | pr_debug("\t.set pop\n"); | |
1da177e4 LT |
1767 | } |
1768 | ||
1769 | static void __init build_r4000_tlb_store_handler(void) | |
1770 | { | |
1771 | u32 *p = handle_tlbs; | |
1772 | struct label *l = labels; | |
1773 | struct reloc *r = relocs; | |
115f2a44 | 1774 | int i; |
1da177e4 LT |
1775 | |
1776 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1777 | memset(labels, 0, sizeof(labels)); | |
1778 | memset(relocs, 0, sizeof(relocs)); | |
1779 | ||
1780 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
1781 | build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); | |
1782 | build_make_write(&p, &r, K0, K1); | |
1783 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1784 | ||
1785 | l_nopage_tlbs(&l, p); | |
1786 | i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1787 | i_nop(&p); | |
1788 | ||
1789 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1790 | panic("TLB store handler fastpath space exceeded"); | |
1791 | ||
1792 | resolve_relocs(relocs, labels); | |
115f2a44 TS |
1793 | pr_info("Synthesized TLB store handler fastpath (%u instructions).\n", |
1794 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1795 | |
115f2a44 TS |
1796 | pr_debug("\t.set push\n"); |
1797 | pr_debug("\t.set noreorder\n"); | |
1798 | for (i = 0; i < (p - handle_tlbs); i++) | |
1799 | pr_debug("\t.word 0x%08x\n", handle_tlbs[i]); | |
1800 | pr_debug("\t.set pop\n"); | |
1da177e4 LT |
1801 | } |
1802 | ||
1803 | static void __init build_r4000_tlb_modify_handler(void) | |
1804 | { | |
1805 | u32 *p = handle_tlbm; | |
1806 | struct label *l = labels; | |
1807 | struct reloc *r = relocs; | |
115f2a44 | 1808 | int i; |
1da177e4 LT |
1809 | |
1810 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1811 | memset(labels, 0, sizeof(labels)); | |
1812 | memset(relocs, 0, sizeof(relocs)); | |
1813 | ||
1814 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
1815 | build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); | |
1816 | /* Present and writable bits set, set accessed and dirty bits. */ | |
1817 | build_make_write(&p, &r, K0, K1); | |
1818 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1819 | ||
1820 | l_nopage_tlbm(&l, p); | |
1821 | i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1822 | i_nop(&p); | |
1823 | ||
1824 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1825 | panic("TLB modify handler fastpath space exceeded"); | |
1826 | ||
1827 | resolve_relocs(relocs, labels); | |
115f2a44 TS |
1828 | pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n", |
1829 | (unsigned int)(p - handle_tlbm)); | |
1830 | ||
1831 | pr_debug("\t.set push\n"); | |
1832 | pr_debug("\t.set noreorder\n"); | |
1833 | for (i = 0; i < (p - handle_tlbm); i++) | |
1834 | pr_debug("\t.word 0x%08x\n", handle_tlbm[i]); | |
1835 | pr_debug("\t.set pop\n"); | |
1da177e4 LT |
1836 | } |
1837 | ||
1838 | void __init build_tlb_refill_handler(void) | |
1839 | { | |
1840 | /* | |
1841 | * The refill handler is generated per-CPU, multi-node systems | |
1842 | * may have local storage for it. The other handlers are only | |
1843 | * needed once. | |
1844 | */ | |
1845 | static int run_once = 0; | |
1846 | ||
1847 | switch (current_cpu_data.cputype) { | |
1848 | case CPU_R2000: | |
1849 | case CPU_R3000: | |
1850 | case CPU_R3000A: | |
1851 | case CPU_R3081E: | |
1852 | case CPU_TX3912: | |
1853 | case CPU_TX3922: | |
1854 | case CPU_TX3927: | |
1855 | build_r3000_tlb_refill_handler(); | |
1856 | if (!run_once) { | |
1857 | build_r3000_tlb_load_handler(); | |
1858 | build_r3000_tlb_store_handler(); | |
1859 | build_r3000_tlb_modify_handler(); | |
1860 | run_once++; | |
1861 | } | |
1862 | break; | |
1863 | ||
1864 | case CPU_R6000: | |
1865 | case CPU_R6000A: | |
1866 | panic("No R6000 TLB refill handler yet"); | |
1867 | break; | |
1868 | ||
1869 | case CPU_R8000: | |
1870 | panic("No R8000 TLB refill handler yet"); | |
1871 | break; | |
1872 | ||
1873 | default: | |
1874 | build_r4000_tlb_refill_handler(); | |
1875 | if (!run_once) { | |
1876 | build_r4000_tlb_load_handler(); | |
1877 | build_r4000_tlb_store_handler(); | |
1878 | build_r4000_tlb_modify_handler(); | |
1879 | run_once++; | |
1880 | } | |
1881 | } | |
1882 | } | |
1d40cfcd RB |
1883 | |
1884 | void __init flush_tlb_handlers(void) | |
1885 | { | |
1886 | flush_icache_range((unsigned long)handle_tlbl, | |
1887 | (unsigned long)handle_tlbl + sizeof(handle_tlbl)); | |
1888 | flush_icache_range((unsigned long)handle_tlbs, | |
1889 | (unsigned long)handle_tlbs + sizeof(handle_tlbs)); | |
1890 | flush_icache_range((unsigned long)handle_tlbm, | |
1891 | (unsigned long)handle_tlbm + sizeof(handle_tlbm)); | |
1892 | } |