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[mirror_ubuntu-artful-kernel.git] / arch / mips / mm / uasm-micromips.c
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a6a4834c
SH		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
9 *
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
14 */
15
16#include <linux/kernel.h>
17#include <linux/types.h>
a6a4834c
SH		 18
19#include <asm/inst.h>
20#include <asm/elf.h>
21#include <asm/bugs.h>
22#define UASM_ISA _UASM_ISA_MICROMIPS
23#include <asm/uasm.h>
24
25#define RS_MASK 0x1f
26#define RS_SH 16
27#define RT_MASK 0x1f
28#define RT_SH 21
29#define SCIMM_MASK 0x3ff
30#define SCIMM_SH 16
31
32/* This macro sets the non-variable bits of an instruction. */
33#define M(a, b, c, d, e, f) \
34 ((a) << OP_SH \
35 | (b) << RT_SH \
36 | (c) << RS_SH \
37 | (d) << RD_SH \
38 | (e) << RE_SH \
39 | (f) << FUNC_SH)
40
41/* Define these when we are not the ISA the kernel is being compiled with. */
42#ifndef CONFIG_CPU_MICROMIPS
43#define MM_uasm_i_b(buf, off) ISAOPC(_beq)(buf, 0, 0, off)
44#define MM_uasm_i_beqz(buf, rs, off) ISAOPC(_beq)(buf, rs, 0, off)
45#define MM_uasm_i_beqzl(buf, rs, off) ISAOPC(_beql)(buf, rs, 0, off)
46#define MM_uasm_i_bnez(buf, rs, off) ISAOPC(_bne)(buf, rs, 0, off)
47#endif
48
49#include "uasm.c"
50
078a55fc 51static struct insn insn_table_MM[] = {
a6a4834c
SH		 52 { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD },
53 { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
54 { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD },
55 { insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
56 { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
57 { insn_beql, 0, 0 },
58 { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM },
59 { insn_bgezl, 0, 0 },
60 { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM },
61 { insn_bltzl, 0, 0 },
62 { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM },
63 { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM },
64 { insn_daddu, 0, 0 },
65 { insn_daddiu, 0, 0 },
4c12a854 66 { insn_divu, M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS },
a6a4834c
SH		 67 { insn_dmfc0, 0, 0 },
68 { insn_dmtc0, 0, 0 },
69 { insn_dsll, 0, 0 },
70 { insn_dsll32, 0, 0 },
71 { insn_dsra, 0, 0 },
72 { insn_dsrl, 0, 0 },
73 { insn_dsrl32, 0, 0 },
74 { insn_drotr, 0, 0 },
75 { insn_drotr32, 0, 0 },
76 { insn_dsubu, 0, 0 },
77 { insn_eret, M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0 },
78 { insn_ins, M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE },
79 { insn_ext, M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE },
80 { insn_j, M(mm_j32_op, 0, 0, 0, 0, 0), JIMM },
81 { insn_jal, M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM },
7fa22681 82 { insn_jalr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS },
a6a4834c 83 { insn_jr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS },
82488818 84 { insn_lb, M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
a6a4834c 85 { insn_ld, 0, 0 },
d6b3314b 86 { insn_lh, M(mm_lh32_op, 0, 0, 0, 0, 0), RS | RS | SIMM },
a6a4834c
SH		 87 { insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM },
88 { insn_lld, 0, 0 },
89 { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM },
90 { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
91 { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD },
f3ec7a23 92 { insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS },
16d21a81 93 { insn_mflo, M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS },
a6a4834c 94 { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD },
a8e897ad 95 { insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD },
a6a4834c
SH		 96 { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD },
97 { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
98 { insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM },
99 { insn_rfe, 0, 0 },
100 { insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM },
101 { insn_scd, 0, 0 },
102 { insn_sd, 0, 0 },
103 { insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD },
bef581ba 104 { insn_sllv, M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD },
7682f9e8 105 { insn_slt, M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD },
390363ed 106 { insn_sltiu, M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
e8ef868b 107 { insn_sltu, M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD },
a6a4834c
SH		 108 { insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD },
109 { insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD },
f31318fd 110 { insn_srlv, M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD },
a6a4834c
SH		 111 { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD },
112 { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD },
113 { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
729ff561 114 { insn_sync, M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS },
a6a4834c
SH		 115 { insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 },
116 { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 },
117 { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 },
118 { insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 },
53ed1389 119 { insn_wait, M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM },
ab9e4fa0 120 { insn_wsbh, M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS },
a6a4834c
SH		 121 { insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD },
122 { insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
123 { insn_dins, 0, 0 },
124 { insn_dinsm, 0, 0 },
125 { insn_syscall, M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM},
126 { insn_bbit0, 0, 0 },
127 { insn_bbit1, 0, 0 },
128 { insn_lwx, 0, 0 },
129 { insn_ldx, 0, 0 },
130 { insn_invalid, 0, 0 }
131};
132
133#undef M
134
078a55fc 135static inline u32 build_bimm(s32 arg)
a6a4834c
SH		 136{
137 WARN(arg > 0xffff || arg < -0x10000,
138 KERN_WARNING "Micro-assembler field overflow\n");
139
140 WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");
141
142 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff);
143}
144
078a55fc 145static inline u32 build_jimm(u32 arg)
a6a4834c 146{
8fe4bb98
SH		 147
148 WARN(arg & ~((JIMM_MASK << 2) | 1),
a6a4834c
SH		 149 KERN_WARNING "Micro-assembler field overflow\n");
150
151 return (arg >> 1) & JIMM_MASK;
152}
153
154/*
155 * The order of opcode arguments is implicitly left to right,
156 * starting with RS and ending with FUNC or IMM.
157 */
078a55fc 158static void build_insn(u32 **buf, enum opcode opc, ...)
a6a4834c
SH		 159{
160 struct insn *ip = NULL;
161 unsigned int i;
162 va_list ap;
163 u32 op;
164
165 for (i = 0; insn_table_MM[i].opcode != insn_invalid; i++)
166 if (insn_table_MM[i].opcode == opc) {
167 ip = &insn_table_MM[i];
168 break;
169 }
170
171 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
172 panic("Unsupported Micro-assembler instruction %d", opc);
173
174 op = ip->match;
175 va_start(ap, opc);
176 if (ip->fields & RS) {
177 if (opc == insn_mfc0 || opc == insn_mtc0)
178 op |= build_rt(va_arg(ap, u32));
179 else
180 op |= build_rs(va_arg(ap, u32));
181 }
182 if (ip->fields & RT) {
183 if (opc == insn_mfc0 || opc == insn_mtc0)
184 op |= build_rs(va_arg(ap, u32));
185 else
186 op |= build_rt(va_arg(ap, u32));
187 }
188 if (ip->fields & RD)
189 op |= build_rd(va_arg(ap, u32));
190 if (ip->fields & RE)
191 op |= build_re(va_arg(ap, u32));
192 if (ip->fields & SIMM)
193 op |= build_simm(va_arg(ap, s32));
194 if (ip->fields & UIMM)
195 op |= build_uimm(va_arg(ap, u32));
196 if (ip->fields & BIMM)
197 op |= build_bimm(va_arg(ap, s32));
198 if (ip->fields & JIMM)
199 op |= build_jimm(va_arg(ap, u32));
200 if (ip->fields & FUNC)
201 op |= build_func(va_arg(ap, u32));
202 if (ip->fields & SET)
203 op |= build_set(va_arg(ap, u32));
204 if (ip->fields & SCIMM)
205 op |= build_scimm(va_arg(ap, u32));
206 va_end(ap);
207
208#ifdef CONFIG_CPU_LITTLE_ENDIAN
209 **buf = ((op & 0xffff) << 16) | (op >> 16);
210#else
211 **buf = op;
212#endif
213 (*buf)++;
214}
215
078a55fc 216static inline void
a6a4834c
SH		 217__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
218{
219 long laddr = (long)lab->addr;
220 long raddr = (long)rel->addr;
221
222 switch (rel->type) {
223 case R_MIPS_PC16:
224#ifdef CONFIG_CPU_LITTLE_ENDIAN
225 *rel->addr |= (build_bimm(laddr - (raddr + 4)) << 16);
226#else
227 *rel->addr |= build_bimm(laddr - (raddr + 4));
228#endif
229 break;
230
231 default:
232 panic("Unsupported Micro-assembler relocation %d",
233 rel->type);
234 }
235}
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