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abc597fe SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * A small micro-assembler. It is intentionally kept simple, does only | |
7 | * support a subset of instructions, and does not try to hide pipeline | |
8 | * effects like branch delay slots. | |
9 | * | |
10 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer | |
11 | * Copyright (C) 2005, 2007 Maciej W. Rozycki | |
12 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) | |
13 | * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/types.h> | |
abc597fe SH |
18 | |
19 | #include <asm/inst.h> | |
20 | #include <asm/elf.h> | |
21 | #include <asm/bugs.h> | |
cf6d9058 | 22 | #define UASM_ISA _UASM_ISA_CLASSIC |
abc597fe SH |
23 | #include <asm/uasm.h> |
24 | ||
25 | #define RS_MASK 0x1f | |
26 | #define RS_SH 21 | |
27 | #define RT_MASK 0x1f | |
28 | #define RT_SH 16 | |
29 | #define SCIMM_MASK 0xfffff | |
30 | #define SCIMM_SH 6 | |
31 | ||
32 | /* This macro sets the non-variable bits of an instruction. */ | |
33 | #define M(a, b, c, d, e, f) \ | |
34 | ((a) << OP_SH \ | |
35 | | (b) << RS_SH \ | |
36 | | (c) << RT_SH \ | |
37 | | (d) << RD_SH \ | |
38 | | (e) << RE_SH \ | |
39 | | (f) << FUNC_SH) | |
40 | ||
a168b8f1 LY |
41 | /* This macro sets the non-variable bits of an R6 instruction. */ |
42 | #define M6(a, b, c, d, e) \ | |
43 | ((a) << OP_SH \ | |
44 | | (b) << RS_SH \ | |
45 | | (c) << RT_SH \ | |
46 | | (d) << SIMM9_SH \ | |
47 | | (e) << FUNC_SH) | |
48 | ||
abc597fe SH |
49 | #include "uasm.c" |
50 | ||
00e06297 | 51 | static const struct insn insn_table[insn_invalid] = { |
ce807d5f DD |
52 | [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
53 | [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD}, | |
54 | [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD}, | |
55 | [insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, | |
56 | [insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, | |
57 | [insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, | |
58 | [insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, | |
59 | [insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, | |
60 | [insn_bgez] = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM}, | |
61 | [insn_bgezl] = {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM}, | |
dc190129 DD |
62 | [insn_bgtz] = {M(bgtz_op, 0, 0, 0, 0, 0), RS | BIMM}, |
63 | [insn_blez] = {M(blez_op, 0, 0, 0, 0, 0), RS | BIMM}, | |
ce807d5f DD |
64 | [insn_bltz] = {M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM}, |
65 | [insn_bltzl] = {M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM}, | |
66 | [insn_bne] = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, | |
dc190129 | 67 | [insn_break] = {M(spec_op, 0, 0, 0, 0, break_op), SCIMM}, |
a168b8f1 | 68 | #ifndef CONFIG_CPU_MIPSR6 |
ce807d5f | 69 | [insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
a168b8f1 | 70 | #else |
ce807d5f | 71 | [insn_cache] = {M6(spec3_op, 0, 0, 0, cache6_op), RS | RT | SIMM9}, |
a168b8f1 | 72 | #endif |
ce807d5f DD |
73 | [insn_cfc1] = {M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD}, |
74 | [insn_cfcmsa] = {M(msa_op, 0, msa_cfc_op, 0, 0, msa_elm_op), RD | RE}, | |
75 | [insn_ctc1] = {M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD}, | |
76 | [insn_ctcmsa] = {M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE}, | |
77 | [insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, | |
78 | [insn_daddu] = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD}, | |
dc190129 | 79 | [insn_ddivu] = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT}, |
ce807d5f DD |
80 | [insn_di] = {M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT}, |
81 | [insn_dins] = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE}, | |
82 | [insn_dinsm] = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE}, | |
dc190129 | 83 | [insn_dinsu] = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE}, |
ce807d5f DD |
84 | [insn_divu] = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT}, |
85 | [insn_dmfc0] = {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, | |
86 | [insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, | |
dc190129 | 87 | [insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT}, |
ce807d5f DD |
88 | [insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE}, |
89 | [insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE}, | |
dc190129 DD |
90 | [insn_dsbh] = {M(spec3_op, 0, 0, 0, dsbh_op, dbshfl_op), RT | RD}, |
91 | [insn_dshd] = {M(spec3_op, 0, 0, 0, dshd_op, dbshfl_op), RT | RD}, | |
ce807d5f DD |
92 | [insn_dsll] = {M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE}, |
93 | [insn_dsll32] = {M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE}, | |
dc190129 | 94 | [insn_dsllv] = {M(spec_op, 0, 0, 0, 0, dsllv_op), RS | RT | RD}, |
ce807d5f | 95 | [insn_dsra] = {M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE}, |
dc190129 DD |
96 | [insn_dsra32] = {M(spec_op, 0, 0, 0, 0, dsra32_op), RT | RD | RE}, |
97 | [insn_dsrav] = {M(spec_op, 0, 0, 0, 0, dsrav_op), RS | RT | RD}, | |
ce807d5f DD |
98 | [insn_dsrl] = {M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE}, |
99 | [insn_dsrl32] = {M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE}, | |
dc190129 | 100 | [insn_dsrlv] = {M(spec_op, 0, 0, 0, 0, dsrlv_op), RS | RT | RD}, |
ce807d5f DD |
101 | [insn_dsubu] = {M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD}, |
102 | [insn_eret] = {M(cop0_op, cop_op, 0, 0, 0, eret_op), 0}, | |
103 | [insn_ext] = {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE}, | |
104 | [insn_ins] = {M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE}, | |
105 | [insn_j] = {M(j_op, 0, 0, 0, 0, 0), JIMM}, | |
106 | [insn_jal] = {M(jal_op, 0, 0, 0, 0, 0), JIMM}, | |
107 | [insn_jalr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD}, | |
a168b8f1 | 108 | #ifndef CONFIG_CPU_MIPSR6 |
ce807d5f | 109 | [insn_jr] = {M(spec_op, 0, 0, 0, 0, jr_op), RS}, |
a168b8f1 | 110 | #else |
ce807d5f | 111 | [insn_jr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS}, |
a168b8f1 | 112 | #endif |
ce807d5f | 113 | [insn_lb] = {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
dc190129 | 114 | [insn_lbu] = {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
ce807d5f DD |
115 | [insn_ld] = {M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
116 | [insn_lddir] = {M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD}, | |
117 | [insn_ldpte] = {M(lwc2_op, 0, 0, 0, ldpte_op, mult_op), RS | RD}, | |
118 | [insn_ldx] = {M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD}, | |
119 | [insn_lh] = {M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, | |
120 | [insn_lhu] = {M(lhu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, | |
a168b8f1 | 121 | #ifndef CONFIG_CPU_MIPSR6 |
ce807d5f DD |
122 | [insn_ll] = {M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
123 | [insn_lld] = {M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, | |
a168b8f1 | 124 | #else |
ce807d5f DD |
125 | [insn_ll] = {M6(spec3_op, 0, 0, 0, ll6_op), RS | RT | SIMM9}, |
126 | [insn_lld] = {M6(spec3_op, 0, 0, 0, lld6_op), RS | RT | SIMM9}, | |
a168b8f1 | 127 | #endif |
ce807d5f DD |
128 | [insn_lui] = {M(lui_op, 0, 0, 0, 0, 0), RT | SIMM}, |
129 | [insn_lw] = {M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, | |
dc190129 | 130 | [insn_lwu] = {M(lwu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
ce807d5f DD |
131 | [insn_lwx] = {M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD}, |
132 | [insn_mfc0] = {M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, | |
133 | [insn_mfhc0] = {M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET}, | |
134 | [insn_mfhi] = {M(spec_op, 0, 0, 0, 0, mfhi_op), RD}, | |
135 | [insn_mflo] = {M(spec_op, 0, 0, 0, 0, mflo_op), RD}, | |
dc190129 DD |
136 | [insn_movn] = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD}, |
137 | [insn_movz] = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD}, | |
ce807d5f DD |
138 | [insn_mtc0] = {M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, |
139 | [insn_mthc0] = {M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET}, | |
140 | [insn_mthi] = {M(spec_op, 0, 0, 0, 0, mthi_op), RS}, | |
141 | [insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS}, | |
6f63405c | 142 | #ifndef CONFIG_CPU_MIPSR6 |
ce807d5f | 143 | [insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD}, |
6f63405c | 144 | #else |
ce807d5f | 145 | [insn_mul] = {M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD}, |
6f63405c | 146 | #endif |
dc190129 DD |
147 | [insn_multu] = {M(spec_op, 0, 0, 0, 0, multu_op), RS | RT}, |
148 | [insn_nor] = {M(spec_op, 0, 0, 0, 0, nor_op), RS | RT | RD}, | |
ce807d5f DD |
149 | [insn_or] = {M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD}, |
150 | [insn_ori] = {M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, | |
a168b8f1 | 151 | #ifndef CONFIG_CPU_MIPSR6 |
ce807d5f | 152 | [insn_pref] = {M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
a168b8f1 | 153 | #else |
ce807d5f | 154 | [insn_pref] = {M6(spec3_op, 0, 0, 0, pref6_op), RS | RT | SIMM9}, |
a168b8f1 | 155 | #endif |
ce807d5f DD |
156 | [insn_rfe] = {M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0}, |
157 | [insn_rotr] = {M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE}, | |
dc190129 | 158 | [insn_sb] = {M(sb_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
a168b8f1 | 159 | #ifndef CONFIG_CPU_MIPSR6 |
ce807d5f DD |
160 | [insn_sc] = {M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
161 | [insn_scd] = {M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, | |
a168b8f1 | 162 | #else |
ce807d5f DD |
163 | [insn_sc] = {M6(spec3_op, 0, 0, 0, sc6_op), RS | RT | SIMM9}, |
164 | [insn_scd] = {M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9}, | |
a168b8f1 | 165 | #endif |
ce807d5f | 166 | [insn_sd] = {M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
dc190129 | 167 | [insn_sh] = {M(sh_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
ce807d5f DD |
168 | [insn_sll] = {M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE}, |
169 | [insn_sllv] = {M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD}, | |
170 | [insn_slt] = {M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD}, | |
dc190129 | 171 | [insn_slti] = {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
ce807d5f DD |
172 | [insn_sltiu] = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
173 | [insn_sltu] = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD}, | |
174 | [insn_sra] = {M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE}, | |
175 | [insn_srl] = {M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE}, | |
176 | [insn_srlv] = {M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD}, | |
177 | [insn_subu] = {M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD}, | |
178 | [insn_sw] = {M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, | |
179 | [insn_sync] = {M(spec_op, 0, 0, 0, 0, sync_op), RE}, | |
180 | [insn_syscall] = {M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, | |
181 | [insn_tlbp] = {M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0}, | |
182 | [insn_tlbr] = {M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0}, | |
183 | [insn_tlbwi] = {M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0}, | |
184 | [insn_tlbwr] = {M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0}, | |
185 | [insn_wait] = {M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM}, | |
186 | [insn_wsbh] = {M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD}, | |
187 | [insn_xor] = {M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD}, | |
188 | [insn_xori] = {M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, | |
189 | [insn_yield] = {M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD}, | |
abc597fe SH |
190 | }; |
191 | ||
192 | #undef M | |
193 | ||
078a55fc | 194 | static inline u32 build_bimm(s32 arg) |
abc597fe SH |
195 | { |
196 | WARN(arg > 0x1ffff || arg < -0x20000, | |
197 | KERN_WARNING "Micro-assembler field overflow\n"); | |
198 | ||
199 | WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); | |
200 | ||
201 | return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); | |
202 | } | |
203 | ||
078a55fc | 204 | static inline u32 build_jimm(u32 arg) |
abc597fe SH |
205 | { |
206 | WARN(arg & ~(JIMM_MASK << 2), | |
207 | KERN_WARNING "Micro-assembler field overflow\n"); | |
208 | ||
209 | return (arg >> 2) & JIMM_MASK; | |
210 | } | |
211 | ||
212 | /* | |
213 | * The order of opcode arguments is implicitly left to right, | |
214 | * starting with RS and ending with FUNC or IMM. | |
215 | */ | |
078a55fc | 216 | static void build_insn(u32 **buf, enum opcode opc, ...) |
abc597fe | 217 | { |
ce807d5f | 218 | const struct insn *ip; |
abc597fe SH |
219 | va_list ap; |
220 | u32 op; | |
221 | ||
ce807d5f DD |
222 | if (opc < 0 || opc >= insn_invalid || |
223 | (opc == insn_daddiu && r4k_daddiu_bug()) || | |
224 | (insn_table[opc].match == 0 && insn_table[opc].fields == 0)) | |
abc597fe SH |
225 | panic("Unsupported Micro-assembler instruction %d", opc); |
226 | ||
ce807d5f DD |
227 | ip = &insn_table[opc]; |
228 | ||
abc597fe SH |
229 | op = ip->match; |
230 | va_start(ap, opc); | |
231 | if (ip->fields & RS) | |
232 | op |= build_rs(va_arg(ap, u32)); | |
233 | if (ip->fields & RT) | |
234 | op |= build_rt(va_arg(ap, u32)); | |
235 | if (ip->fields & RD) | |
236 | op |= build_rd(va_arg(ap, u32)); | |
237 | if (ip->fields & RE) | |
238 | op |= build_re(va_arg(ap, u32)); | |
239 | if (ip->fields & SIMM) | |
240 | op |= build_simm(va_arg(ap, s32)); | |
241 | if (ip->fields & UIMM) | |
242 | op |= build_uimm(va_arg(ap, u32)); | |
243 | if (ip->fields & BIMM) | |
244 | op |= build_bimm(va_arg(ap, s32)); | |
245 | if (ip->fields & JIMM) | |
246 | op |= build_jimm(va_arg(ap, u32)); | |
247 | if (ip->fields & FUNC) | |
248 | op |= build_func(va_arg(ap, u32)); | |
249 | if (ip->fields & SET) | |
250 | op |= build_set(va_arg(ap, u32)); | |
251 | if (ip->fields & SCIMM) | |
252 | op |= build_scimm(va_arg(ap, u32)); | |
a168b8f1 LY |
253 | if (ip->fields & SIMM9) |
254 | op |= build_scimm9(va_arg(ap, u32)); | |
abc597fe SH |
255 | va_end(ap); |
256 | ||
257 | **buf = op; | |
258 | (*buf)++; | |
259 | } | |
260 | ||
078a55fc | 261 | static inline void |
abc597fe SH |
262 | __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) |
263 | { | |
264 | long laddr = (long)lab->addr; | |
265 | long raddr = (long)rel->addr; | |
266 | ||
267 | switch (rel->type) { | |
268 | case R_MIPS_PC16: | |
269 | *rel->addr |= build_bimm(laddr - (raddr + 4)); | |
270 | break; | |
271 | ||
272 | default: | |
273 | panic("Unsupported Micro-assembler relocation %d", | |
274 | rel->type); | |
275 | } | |
276 | } |