[mirror_ubuntu-artful-kernel.git] / arch / mips / mm / uasm.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * A small micro-assembler. It is intentionally kept simple, does only
 * support a subset of instructions, and does not try to hide pipeline
 * effects like branch delay slots.
 *
 * Copyright (C) 2004, 2005, 2006, 2008	 Thiemo Seufer
 * Copyright (C) 2005, 2007  Maciej W. Rozycki
 * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2012, 2013  MIPS Technologies, Inc.  All rights reserved.
 */

enum fields {
	RS = 0x001,
	RT = 0x002,
	RD = 0x004,
	RE = 0x008,
	SIMM = 0x010,
	UIMM = 0x020,
	BIMM = 0x040,
	JIMM = 0x080,
	FUNC = 0x100,
	SET = 0x200,
	SCIMM = 0x400
};

#define OP_MASK		0x3f
#define OP_SH		26
#define RD_MASK		0x1f
#define RD_SH		11
#define RE_MASK		0x1f
#define RE_SH		6
#define IMM_MASK	0xffff
#define IMM_SH		0
#define JIMM_MASK	0x3ffffff
#define JIMM_SH		0
#define FUNC_MASK	0x3f
#define FUNC_SH		0
#define SET_MASK	0x7
#define SET_SH		0

enum opcode {
	insn_invalid,
	insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
	insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
	insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
	insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
	insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
	insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ldx,
	insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0,
	insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,
	insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
	insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor,
	insn_xori,
};

struct insn {
	enum opcode opcode;
	u32 match;
	enum fields fields;
};

static inline u32 build_rs(u32 arg)
{
	WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RS_MASK) << RS_SH;
}

static inline u32 build_rt(u32 arg)
{
	WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RT_MASK) << RT_SH;
}

static inline u32 build_rd(u32 arg)
{
	WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RD_MASK) << RD_SH;
}

static inline u32 build_re(u32 arg)
{
	WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RE_MASK) << RE_SH;
}

static inline u32 build_simm(s32 arg)
{
	WARN(arg > 0x7fff || arg < -0x8000,
	     KERN_WARNING "Micro-assembler field overflow\n");

	return arg & 0xffff;
}

static inline u32 build_uimm(u32 arg)
{
	WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & IMM_MASK;
}

static inline u32 build_scimm(u32 arg)
{
	WARN(arg & ~SCIMM_MASK,
	     KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & SCIMM_MASK) << SCIMM_SH;
}

static inline u32 build_func(u32 arg)
{
	WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & FUNC_MASK;
}

static inline u32 build_set(u32 arg)
{
	WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & SET_MASK;
}

static void build_insn(u32 **buf, enum opcode opc, ...);

#define I_u1u2u3(op)					\
Ip_u1u2u3(op)						\
{							\
	build_insn(buf, insn##op, a, b, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1u3(op)					\
Ip_u2u1u3(op)						\
{							\
	build_insn(buf, insn##op, b, a, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u3u1u2(op)					\
Ip_u3u1u2(op)						\
{							\
	build_insn(buf, insn##op, b, c, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1u2s3(op)					\
Ip_u1u2s3(op)						\
{							\
	build_insn(buf, insn##op, a, b, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2s3u1(op)					\
Ip_u2s3u1(op)						\
{							\
	build_insn(buf, insn##op, c, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1s3(op)					\
Ip_u2u1s3(op)						\
{							\
	build_insn(buf, insn##op, b, a, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msbu3(op)					\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, c+d-1, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msb32u3(op)				\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, c+d-33, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msbdu3(op)				\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, d-1, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1u2(op)					\
Ip_u1u2(op)						\
{							\
	build_insn(buf, insn##op, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1s2(op)					\
Ip_u1s2(op)						\
{							\
	build_insn(buf, insn##op, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1(op)					\
Ip_u1(op)						\
{							\
	build_insn(buf, insn##op, a);			\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_0(op)						\
Ip_0(op)						\
{							\
	build_insn(buf, insn##op);			\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

I_u2u1s3(_addiu)
I_u3u1u2(_addu)
I_u2u1u3(_andi)
I_u3u1u2(_and)
I_u1u2s3(_beq)
I_u1u2s3(_beql)
I_u1s2(_bgez)
I_u1s2(_bgezl)
I_u1s2(_bltz)
I_u1s2(_bltzl)
I_u1u2s3(_bne)
I_u2s3u1(_cache)
I_u1u2u3(_dmfc0)
I_u1u2u3(_dmtc0)
I_u2u1s3(_daddiu)
I_u3u1u2(_daddu)
I_u2u1u3(_dsll)
I_u2u1u3(_dsll32)
I_u2u1u3(_dsra)
I_u2u1u3(_dsrl)
I_u2u1u3(_dsrl32)
I_u2u1u3(_drotr)
I_u2u1u3(_drotr32)
I_u3u1u2(_dsubu)
I_0(_eret)
I_u2u1msbdu3(_ext)
I_u2u1msbu3(_ins)
I_u1(_j)
I_u1(_jal)
I_u1(_jr)
I_u2s3u1(_ld)
I_u2s3u1(_ll)
I_u2s3u1(_lld)
I_u1s2(_lui)
I_u2s3u1(_lw)
I_u1u2u3(_mfc0)
I_u1u2u3(_mtc0)
I_u2u1u3(_ori)
I_u3u1u2(_or)
I_0(_rfe)
I_u2s3u1(_sc)
I_u2s3u1(_scd)
I_u2s3u1(_sd)
I_u2u1u3(_sll)
I_u2u1u3(_sra)
I_u2u1u3(_srl)
I_u2u1u3(_rotr)
I_u3u1u2(_subu)
I_u2s3u1(_sw)
I_0(_tlbp)
I_0(_tlbr)
I_0(_tlbwi)
I_0(_tlbwr)
I_u3u1u2(_xor)
I_u2u1u3(_xori)
I_u2u1msbu3(_dins);
I_u2u1msb32u3(_dinsm);
I_u1(_syscall);
I_u1u2s3(_bbit0);
I_u1u2s3(_bbit1);
I_u3u1u2(_lwx)
I_u3u1u2(_ldx)

#ifdef CONFIG_CPU_CAVIUM_OCTEON
#include <asm/octeon/octeon.h>
void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
			    unsigned int c)
{
	if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
		/*
		 * As per erratum Core-14449, replace prefetches 0-4,
		 * 6-24 with 'pref 28'.
		 */
		build_insn(buf, insn_pref, c, 28, b);
	else
		build_insn(buf, insn_pref, c, a, b);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
#else
I_u2s3u1(_pref)
#endif

/* Handle labels. */
void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid)
{
	(*lab)->addr = addr;
	(*lab)->lab = lid;
	(*lab)++;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));

int ISAFUNC(uasm_in_compat_space_p)(long addr)
{
	/* Is this address in 32bit compat space? */
#ifdef CONFIG_64BIT
	return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
#else
	return 1;
#endif
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));

static int uasm_rel_highest(long val)
{
#ifdef CONFIG_64BIT
	return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
#else
	return 0;
#endif
}

static int uasm_rel_higher(long val)
{
#ifdef CONFIG_64BIT
	return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
#else
	return 0;
#endif
}

int ISAFUNC(uasm_rel_hi)(long val)
{
	return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));

int ISAFUNC(uasm_rel_lo)(long val)
{
	return ((val & 0xffff) ^ 0x8000) - 0x8000;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));

void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
{
	if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
		ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
		if (uasm_rel_higher(addr))
			ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
		if (ISAFUNC(uasm_rel_hi(addr))) {
			ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
			ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
					ISAFUNC(uasm_rel_hi)(addr));
			ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
		} else
			ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
	} else
		ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
}
UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));

void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
{
	ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
	if (ISAFUNC(uasm_rel_lo(addr))) {
		if (!ISAFUNC(uasm_in_compat_space_p)(addr))
			ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
					ISAFUNC(uasm_rel_lo(addr)));
		else
			ISAFUNC(uasm_i_addiu)(buf, rs, rs,
					ISAFUNC(uasm_rel_lo(addr)));
	}
}
UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));

/* Handle relocations. */
void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
{
	(*rel)->addr = addr;
	(*rel)->type = R_MIPS_PC16;
	(*rel)->lab = lid;
	(*rel)++;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));

static inline void __resolve_relocs(struct uasm_reloc *rel,
				    struct uasm_label *lab);

void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
				  struct uasm_label *lab)
{
	struct uasm_label *l;

	for (; rel->lab != UASM_LABEL_INVALID; rel++)
		for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
			if (rel->lab == l->lab)
				__resolve_relocs(rel, l);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));

void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end,
			       long off)
{
	for (; rel->lab != UASM_LABEL_INVALID; rel++)
		if (rel->addr >= first && rel->addr < end)
			rel->addr += off;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));

void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end,
			       long off)
{
	for (; lab->lab != UASM_LABEL_INVALID; lab++)
		if (lab->addr >= first && lab->addr < end)
			lab->addr += off;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));

void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab,
				u32 *first, u32 *end, u32 *target)
{
	long off = (long)(target - first);

	memcpy(target, first, (end - first) * sizeof(u32));

	ISAFUNC(uasm_move_relocs(rel, first, end, off));
	ISAFUNC(uasm_move_labels(lab, first, end, off));
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));

int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
{
	for (; rel->lab != UASM_LABEL_INVALID; rel++) {
		if (rel->addr == addr
		    && (rel->type == R_MIPS_PC16
			|| rel->type == R_MIPS_26))
			return 1;
	}

	return 0;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));

/* Convenience functions for labeled branches. */
void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bltz)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));

void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_b)(p, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));

void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_beqz)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));

void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_beqzl)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));

void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1,
			  unsigned int reg2, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));

void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bnez)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));

void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bgezl)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));

void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bgez)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));

void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    unsigned int bit, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));

void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    unsigned int bit, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));
Commit	Line	Data
e30ec452 TS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* A small micro-assembler. It is intentionally kept simple, does only
	7	* support a subset of instructions, and does not try to hide pipeline
	8	* effects like branch delay slots.
	9	*
70342287	10	* Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
e30ec452 TS	11	* Copyright (C) 2005, 2007 Maciej W. Rozycki
e30ec452 TS	12	* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
abc597fe	13	* Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
e30ec452 TS	14	*/
e30ec452 TS	15
e30ec452 TS	16	enum fields {
	17	RS = 0x001,
	18	RT = 0x002,
	19	RD = 0x004,
	20	RE = 0x008,
	21	SIMM = 0x010,
	22	UIMM = 0x020,
	23	BIMM = 0x040,
	24	JIMM = 0x080,
	25	FUNC = 0x100,
58b9e223 DD	26	SET = 0x200,
58b9e223 DD	27	SCIMM = 0x400
e30ec452 TS	28	};
	29
	30	#define OP_MASK 0x3f
	31	#define OP_SH 26
e30ec452 TS	32	#define RD_MASK 0x1f
	33	#define RD_SH 11
	34	#define RE_MASK 0x1f
	35	#define RE_SH 6
	36	#define IMM_MASK 0xffff
	37	#define IMM_SH 0
	38	#define JIMM_MASK 0x3ffffff
	39	#define JIMM_SH 0
	40	#define FUNC_MASK 0x3f
	41	#define FUNC_SH 0
	42	#define SET_MASK 0x7
	43	#define SET_SH 0
	44
	45	enum opcode {
	46	insn_invalid,
71a1c776 SH	47	insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
	48	insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
	49	insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
	50	insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
	51	insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
e6de1a09 SH	52	insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ldx,
	53	insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0,
	54	insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,
	55	insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
	56	insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor,
	57	insn_xori,
e30ec452 TS	58	};
	59
	60	struct insn {
	61	enum opcode opcode;
	62	u32 match;
	63	enum fields fields;
	64	};
	65
078a55fc	66	static inline u32 build_rs(u32 arg)
e30ec452	67	{
8d662c8d	68	WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	69
	70	return (arg & RS_MASK) << RS_SH;
	71	}
	72
078a55fc	73	static inline u32 build_rt(u32 arg)
e30ec452	74	{
8d662c8d	75	WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	76
	77	return (arg & RT_MASK) << RT_SH;
	78	}
	79
078a55fc	80	static inline u32 build_rd(u32 arg)
e30ec452	81	{
8d662c8d	82	WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	83
	84	return (arg & RD_MASK) << RD_SH;
	85	}
	86
078a55fc	87	static inline u32 build_re(u32 arg)
e30ec452	88	{
8d662c8d	89	WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	90
	91	return (arg & RE_MASK) << RE_SH;
	92	}
	93
078a55fc	94	static inline u32 build_simm(s32 arg)
e30ec452	95	{
8d662c8d DD	96	WARN(arg > 0x7fff \|\| arg < -0x8000,
8d662c8d DD	97	KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	98
	99	return arg & 0xffff;
	100	}
	101
078a55fc	102	static inline u32 build_uimm(u32 arg)
e30ec452	103	{
8d662c8d	104	WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	105
	106	return arg & IMM_MASK;
	107	}
	108
078a55fc	109	static inline u32 build_scimm(u32 arg)
58b9e223	110	{
8d662c8d DD	111	WARN(arg & ~SCIMM_MASK,
8d662c8d DD	112	KERN_WARNING "Micro-assembler field overflow\n");
58b9e223 DD	113
	114	return (arg & SCIMM_MASK) << SCIMM_SH;
	115	}
	116
078a55fc	117	static inline u32 build_func(u32 arg)
e30ec452	118	{
8d662c8d	119	WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	120
	121	return arg & FUNC_MASK;
	122	}
	123
078a55fc	124	static inline u32 build_set(u32 arg)
e30ec452	125	{
8d662c8d	126	WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	127
	128	return arg & SET_MASK;
	129	}
	130
078a55fc	131	static void build_insn(u32 **buf, enum opcode opc, ...);
e30ec452 TS	132
	133	#define I_u1u2u3(op) \
	134	Ip_u1u2u3(op) \
	135	{ \
	136	build_insn(buf, insn##op, a, b, c); \
22b0763a DD	137	} \
22b0763a DD	138	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	139
	140	#define I_u2u1u3(op) \
	141	Ip_u2u1u3(op) \
	142	{ \
	143	build_insn(buf, insn##op, b, a, c); \
22b0763a DD	144	} \
22b0763a DD	145	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	146
	147	#define I_u3u1u2(op) \
	148	Ip_u3u1u2(op) \
	149	{ \
	150	build_insn(buf, insn##op, b, c, a); \
22b0763a DD	151	} \
22b0763a DD	152	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	153
	154	#define I_u1u2s3(op) \
	155	Ip_u1u2s3(op) \
	156	{ \
	157	build_insn(buf, insn##op, a, b, c); \
22b0763a DD	158	} \
22b0763a DD	159	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	160
	161	#define I_u2s3u1(op) \
	162	Ip_u2s3u1(op) \
	163	{ \
	164	build_insn(buf, insn##op, c, a, b); \
22b0763a DD	165	} \
22b0763a DD	166	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	167
	168	#define I_u2u1s3(op) \
	169	Ip_u2u1s3(op) \
	170	{ \
	171	build_insn(buf, insn##op, b, a, c); \
22b0763a DD	172	} \
22b0763a DD	173	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452	174
92078e06 DD	175	#define I_u2u1msbu3(op) \
	176	Ip_u2u1msbu3(op) \
	177	{ \
	178	build_insn(buf, insn##op, b, a, c+d-1, c); \
22b0763a DD	179	} \
22b0763a DD	180	UASM_EXPORT_SYMBOL(uasm_i##op);
92078e06	181
c42aef09 DD	182	#define I_u2u1msb32u3(op) \
	183	Ip_u2u1msbu3(op) \
	184	{ \
	185	build_insn(buf, insn##op, b, a, c+d-33, c); \
	186	} \
	187	UASM_EXPORT_SYMBOL(uasm_i##op);
	188
70342287	189	#define I_u2u1msbdu3(op) \
e6de1a09 SH	190	Ip_u2u1msbu3(op) \
	191	{ \
	192	build_insn(buf, insn##op, b, a, d-1, c); \
	193	} \
	194	UASM_EXPORT_SYMBOL(uasm_i##op);
	195
e30ec452 TS	196	#define I_u1u2(op) \
	197	Ip_u1u2(op) \
	198	{ \
	199	build_insn(buf, insn##op, a, b); \
22b0763a DD	200	} \
22b0763a DD	201	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	202
	203	#define I_u1s2(op) \
	204	Ip_u1s2(op) \
	205	{ \
	206	build_insn(buf, insn##op, a, b); \
22b0763a DD	207	} \
22b0763a DD	208	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	209
	210	#define I_u1(op) \
	211	Ip_u1(op) \
	212	{ \
	213	build_insn(buf, insn##op, a); \
22b0763a DD	214	} \
22b0763a DD	215	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	216
	217	#define I_0(op) \
	218	Ip_0(op) \
	219	{ \
	220	build_insn(buf, insn##op); \
22b0763a DD	221	} \
22b0763a DD	222	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	223
	224	I_u2u1s3(_addiu)
	225	I_u3u1u2(_addu)
	226	I_u2u1u3(_andi)
	227	I_u3u1u2(_and)
	228	I_u1u2s3(_beq)
	229	I_u1u2s3(_beql)
	230	I_u1s2(_bgez)
	231	I_u1s2(_bgezl)
	232	I_u1s2(_bltz)
	233	I_u1s2(_bltzl)
	234	I_u1u2s3(_bne)
fb2a27e7	235	I_u2s3u1(_cache)
e30ec452 TS	236	I_u1u2u3(_dmfc0)
	237	I_u1u2u3(_dmtc0)
	238	I_u2u1s3(_daddiu)
	239	I_u3u1u2(_daddu)
	240	I_u2u1u3(_dsll)
	241	I_u2u1u3(_dsll32)
	242	I_u2u1u3(_dsra)
	243	I_u2u1u3(_dsrl)
	244	I_u2u1u3(_dsrl32)
92078e06	245	I_u2u1u3(_drotr)
de6d5b55	246	I_u2u1u3(_drotr32)
e30ec452 TS	247	I_u3u1u2(_dsubu)
e30ec452 TS	248	I_0(_eret)
e6de1a09 SH	249	I_u2u1msbdu3(_ext)
e6de1a09 SH	250	I_u2u1msbu3(_ins)
e30ec452 TS	251	I_u1(_j)
	252	I_u1(_jal)
	253	I_u1(_jr)
	254	I_u2s3u1(_ld)
	255	I_u2s3u1(_ll)
	256	I_u2s3u1(_lld)
	257	I_u1s2(_lui)
	258	I_u2s3u1(_lw)
	259	I_u1u2u3(_mfc0)
	260	I_u1u2u3(_mtc0)
	261	I_u2u1u3(_ori)
5808184f	262	I_u3u1u2(_or)
e30ec452 TS	263	I_0(_rfe)
	264	I_u2s3u1(_sc)
	265	I_u2s3u1(_scd)
	266	I_u2s3u1(_sd)
	267	I_u2u1u3(_sll)
	268	I_u2u1u3(_sra)
	269	I_u2u1u3(_srl)
32546f38	270	I_u2u1u3(_rotr)
e30ec452 TS	271	I_u3u1u2(_subu)
	272	I_u2s3u1(_sw)
	273	I_0(_tlbp)
32546f38	274	I_0(_tlbr)
e30ec452 TS	275	I_0(_tlbwi)
	276	I_0(_tlbwr)
	277	I_u3u1u2(_xor)
	278	I_u2u1u3(_xori)
92078e06	279	I_u2u1msbu3(_dins);
c42aef09	280	I_u2u1msb32u3(_dinsm);
58b9e223	281	I_u1(_syscall);
5b97c3f7 DD	282	I_u1u2s3(_bbit0);
5b97c3f7 DD	283	I_u1u2s3(_bbit1);
bb3d68c3 DD	284	I_u3u1u2(_lwx)
bb3d68c3 DD	285	I_u3u1u2(_ldx)
e30ec452	286
c9941158 DD	287	#ifdef CONFIG_CPU_CAVIUM_OCTEON
c9941158 DD	288	#include <asm/octeon/octeon.h>
078a55fc	289	void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
c9941158 DD	290	unsigned int c)
	291	{
	292	if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
	293	/*
	294	* As per erratum Core-14449, replace prefetches 0-4,
	295	* 6-24 with 'pref 28'.
	296	*/
	297	build_insn(buf, insn_pref, c, 28, b);
	298	else
	299	build_insn(buf, insn_pref, c, a, b);
	300	}
abc597fe	301	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
c9941158 DD	302	#else
	303	I_u2s3u1(_pref)
	304	#endif
	305
e30ec452	306	/* Handle labels. */
078a55fc	307	void ISAFUNC(uasm_build_label)(struct uasm_label *lab, u32 addr, int lid)
e30ec452 TS	308	{
	309	(*lab)->addr = addr;
	310	(*lab)->lab = lid;
	311	(*lab)++;
	312	}
abc597fe	313	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));
e30ec452	314
078a55fc	315	int ISAFUNC(uasm_in_compat_space_p)(long addr)
e30ec452 TS	316	{
	317	/* Is this address in 32bit compat space? */
	318	#ifdef CONFIG_64BIT
	319	return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
	320	#else
	321	return 1;
	322	#endif
	323	}
abc597fe	324	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));
e30ec452	325
078a55fc	326	static int uasm_rel_highest(long val)
e30ec452 TS	327	{
	328	#ifdef CONFIG_64BIT
	329	return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
	330	#else
	331	return 0;
	332	#endif
	333	}
	334
078a55fc	335	static int uasm_rel_higher(long val)
e30ec452 TS	336	{
	337	#ifdef CONFIG_64BIT
	338	return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
	339	#else
	340	return 0;
	341	#endif
	342	}
	343
078a55fc	344	int ISAFUNC(uasm_rel_hi)(long val)
e30ec452 TS	345	{
	346	return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
	347	}
abc597fe	348	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));
e30ec452	349
078a55fc	350	int ISAFUNC(uasm_rel_lo)(long val)
e30ec452 TS	351	{
	352	return ((val & 0xffff) ^ 0x8000) - 0x8000;
	353	}
abc597fe	354	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));
e30ec452	355
078a55fc	356	void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
e30ec452	357	{
abc597fe SH	358	if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
abc597fe SH	359	ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
e30ec452	360	if (uasm_rel_higher(addr))
abc597fe SH	361	ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
	362	if (ISAFUNC(uasm_rel_hi(addr))) {
	363	ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
	364	ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
	365	ISAFUNC(uasm_rel_hi)(addr));
	366	ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
e30ec452	367	} else
abc597fe	368	ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
e30ec452	369	} else
abc597fe	370	ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
e30ec452	371	}
abc597fe	372	UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));
e30ec452	373
078a55fc	374	void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
e30ec452	375	{
abc597fe SH	376	ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
	377	if (ISAFUNC(uasm_rel_lo(addr))) {
	378	if (!ISAFUNC(uasm_in_compat_space_p)(addr))
	379	ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
	380	ISAFUNC(uasm_rel_lo(addr)));
e30ec452	381	else
abc597fe SH	382	ISAFUNC(uasm_i_addiu)(buf, rs, rs,
abc597fe SH	383	ISAFUNC(uasm_rel_lo(addr)));
e30ec452 TS	384	}
e30ec452 TS	385	}
abc597fe	386	UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));
e30ec452 TS	387
e30ec452 TS	388	/* Handle relocations. */
078a55fc	389	void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc *rel, u32 addr, int lid)
e30ec452 TS	390	{
	391	(*rel)->addr = addr;
	392	(*rel)->type = R_MIPS_PC16;
	393	(*rel)->lab = lid;
	394	(*rel)++;
	395	}
abc597fe	396	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));
e30ec452	397
078a55fc PG	398	static inline void __resolve_relocs(struct uasm_reloc *rel,
078a55fc PG	399	struct uasm_label *lab);
e30ec452	400
078a55fc PG	401	void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
078a55fc PG	402	struct uasm_label *lab)
e30ec452 TS	403	{
	404	struct uasm_label *l;
	405
	406	for (; rel->lab != UASM_LABEL_INVALID; rel++)
	407	for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
	408	if (rel->lab == l->lab)
	409	__resolve_relocs(rel, l);
	410	}
abc597fe	411	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));
e30ec452	412
078a55fc PG	413	void ISAFUNC(uasm_move_relocs)(struct uasm_reloc rel, u32 first, u32 *end,
078a55fc PG	414	long off)
e30ec452 TS	415	{
	416	for (; rel->lab != UASM_LABEL_INVALID; rel++)
	417	if (rel->addr >= first && rel->addr < end)
	418	rel->addr += off;
	419	}
abc597fe	420	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));
e30ec452	421
078a55fc PG	422	void ISAFUNC(uasm_move_labels)(struct uasm_label lab, u32 first, u32 *end,
078a55fc PG	423	long off)
e30ec452 TS	424	{
	425	for (; lab->lab != UASM_LABEL_INVALID; lab++)
	426	if (lab->addr >= first && lab->addr < end)
	427	lab->addr += off;
	428	}
abc597fe	429	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));
e30ec452	430
078a55fc PG	431	void ISAFUNC(uasm_copy_handler)(struct uasm_reloc rel, struct uasm_label lab,
078a55fc PG	432	u32 first, u32 end, u32 *target)
e30ec452 TS	433	{
	434	long off = (long)(target - first);
	435
	436	memcpy(target, first, (end - first) * sizeof(u32));
	437
abc597fe SH	438	ISAFUNC(uasm_move_relocs(rel, first, end, off));
abc597fe SH	439	ISAFUNC(uasm_move_labels(lab, first, end, off));
e30ec452	440	}
abc597fe	441	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));
e30ec452	442
078a55fc	443	int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc rel, u32 addr)
e30ec452 TS	444	{
	445	for (; rel->lab != UASM_LABEL_INVALID; rel++) {
	446	if (rel->addr == addr
	447	&& (rel->type == R_MIPS_PC16
	448	\|\| rel->type == R_MIPS_26))
	449	return 1;
	450	}
	451
	452	return 0;
	453	}
abc597fe	454	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));
e30ec452 TS	455
e30ec452 TS	456	/* Convenience functions for labeled branches. */
078a55fc PG	457	void ISAFUNC(uasm_il_bltz)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	458	int lid)
e30ec452 TS	459	{
e30ec452 TS	460	uasm_r_mips_pc16(r, *p, lid);
abc597fe	461	ISAFUNC(uasm_i_bltz)(p, reg, 0);
e30ec452	462	}
abc597fe	463	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));
e30ec452	464
078a55fc	465	void ISAFUNC(uasm_il_b)(u32 p, struct uasm_reloc r, int lid)
e30ec452 TS	466	{
e30ec452 TS	467	uasm_r_mips_pc16(r, *p, lid);
abc597fe	468	ISAFUNC(uasm_i_b)(p, 0);
e30ec452	469	}
abc597fe	470	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
e30ec452	471
078a55fc PG	472	void ISAFUNC(uasm_il_beqz)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	473	int lid)
e30ec452 TS	474	{
e30ec452 TS	475	uasm_r_mips_pc16(r, *p, lid);
abc597fe	476	ISAFUNC(uasm_i_beqz)(p, reg, 0);
e30ec452	477	}
abc597fe	478	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));
e30ec452	479
078a55fc PG	480	void ISAFUNC(uasm_il_beqzl)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	481	int lid)
e30ec452 TS	482	{
e30ec452 TS	483	uasm_r_mips_pc16(r, *p, lid);
abc597fe	484	ISAFUNC(uasm_i_beqzl)(p, reg, 0);
e30ec452	485	}
abc597fe	486	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));
e30ec452	487
078a55fc PG	488	void ISAFUNC(uasm_il_bne)(u32 p, struct uasm_reloc r, unsigned int reg1,
078a55fc PG	489	unsigned int reg2, int lid)
fb2a27e7 TS	490	{
fb2a27e7 TS	491	uasm_r_mips_pc16(r, *p, lid);
abc597fe	492	ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
fb2a27e7	493	}
abc597fe	494	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));
fb2a27e7	495
078a55fc PG	496	void ISAFUNC(uasm_il_bnez)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	497	int lid)
e30ec452 TS	498	{
e30ec452 TS	499	uasm_r_mips_pc16(r, *p, lid);
abc597fe	500	ISAFUNC(uasm_i_bnez)(p, reg, 0);
e30ec452	501	}
abc597fe	502	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));
e30ec452	503
078a55fc PG	504	void ISAFUNC(uasm_il_bgezl)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	505	int lid)
e30ec452 TS	506	{
e30ec452 TS	507	uasm_r_mips_pc16(r, *p, lid);
abc597fe	508	ISAFUNC(uasm_i_bgezl)(p, reg, 0);
e30ec452	509	}
abc597fe	510	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));
e30ec452	511
078a55fc PG	512	void ISAFUNC(uasm_il_bgez)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	513	int lid)
e30ec452 TS	514	{
e30ec452 TS	515	uasm_r_mips_pc16(r, *p, lid);
abc597fe	516	ISAFUNC(uasm_i_bgez)(p, reg, 0);
e30ec452	517	}
abc597fe	518	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));
5b97c3f7	519
078a55fc PG	520	void ISAFUNC(uasm_il_bbit0)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	521	unsigned int bit, int lid)
5b97c3f7 DD	522	{
5b97c3f7 DD	523	uasm_r_mips_pc16(r, *p, lid);
abc597fe	524	ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
5b97c3f7	525	}
abc597fe	526	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));
5b97c3f7	527
078a55fc PG	528	void ISAFUNC(uasm_il_bbit1)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	529	unsigned int bit, int lid)
5b97c3f7 DD	530	{
5b97c3f7 DD	531	uasm_r_mips_pc16(r, *p, lid);
abc597fe	532	ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
5b97c3f7	533	}
abc597fe	534	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));