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[MIPS] IP27: Tighten up CPU description to fix warnings.
[mirror_ubuntu-zesty-kernel.git] / arch / mips / mm / uasm.c
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e30ec452
TS		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
9 *
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 */
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/init.h>
18
19#include <asm/inst.h>
20#include <asm/elf.h>
21#include <asm/bugs.h>
22
23#include "uasm.h"
24
25enum fields {
26 RS = 0x001,
27 RT = 0x002,
28 RD = 0x004,
29 RE = 0x008,
30 SIMM = 0x010,
31 UIMM = 0x020,
32 BIMM = 0x040,
33 JIMM = 0x080,
34 FUNC = 0x100,
35 SET = 0x200
36};
37
38#define OP_MASK 0x3f
39#define OP_SH 26
40#define RS_MASK 0x1f
41#define RS_SH 21
42#define RT_MASK 0x1f
43#define RT_SH 16
44#define RD_MASK 0x1f
45#define RD_SH 11
46#define RE_MASK 0x1f
47#define RE_SH 6
48#define IMM_MASK 0xffff
49#define IMM_SH 0
50#define JIMM_MASK 0x3ffffff
51#define JIMM_SH 0
52#define FUNC_MASK 0x3f
53#define FUNC_SH 0
54#define SET_MASK 0x7
55#define SET_SH 0
56
57enum opcode {
58 insn_invalid,
59 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
60 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
61 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0,
62 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32,
63 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld,
64 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0,
65 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
66 insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi,
67 insn_tlbwr, insn_xor, insn_xori
68};
69
70struct insn {
71 enum opcode opcode;
72 u32 match;
73 enum fields fields;
74};
75
76/* This macro sets the non-variable bits of an instruction. */
77#define M(a, b, c, d, e, f) \
78 ((a) << OP_SH \
79 | (b) << RS_SH \
80 | (c) << RT_SH \
81 | (d) << RD_SH \
82 | (e) << RE_SH \
83 | (f) << FUNC_SH)
84
85static struct insn insn_table[] __initdata = {
86 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
87 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
88 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
89 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
90 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
91 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
92 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
93 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
94 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
95 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
96 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
97 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
98 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
99 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
100 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
101 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
102 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
103 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
104 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
105 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
106 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
107 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
108 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
109 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
110 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
111 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
112 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
113 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
114 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
115 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
116 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
117 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
118 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
119 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
120 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
121 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
122 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
123 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
124 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
125 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
126 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
127 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
128 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
129 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
130 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
131 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
132 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
133 { insn_invalid, 0, 0 }
134};
135
136#undef M
137
138static inline __init u32 build_rs(u32 arg)
139{
140 if (arg & ~RS_MASK)
141 printk(KERN_WARNING "Micro-assembler field overflow\n");
142
143 return (arg & RS_MASK) << RS_SH;
144}
145
146static inline __init u32 build_rt(u32 arg)
147{
148 if (arg & ~RT_MASK)
149 printk(KERN_WARNING "Micro-assembler field overflow\n");
150
151 return (arg & RT_MASK) << RT_SH;
152}
153
154static inline __init u32 build_rd(u32 arg)
155{
156 if (arg & ~RD_MASK)
157 printk(KERN_WARNING "Micro-assembler field overflow\n");
158
159 return (arg & RD_MASK) << RD_SH;
160}
161
162static inline __init u32 build_re(u32 arg)
163{
164 if (arg & ~RE_MASK)
165 printk(KERN_WARNING "Micro-assembler field overflow\n");
166
167 return (arg & RE_MASK) << RE_SH;
168}
169
170static inline __init u32 build_simm(s32 arg)
171{
172 if (arg > 0x7fff || arg < -0x8000)
173 printk(KERN_WARNING "Micro-assembler field overflow\n");
174
175 return arg & 0xffff;
176}
177
178static inline __init u32 build_uimm(u32 arg)
179{
180 if (arg & ~IMM_MASK)
181 printk(KERN_WARNING "Micro-assembler field overflow\n");
182
183 return arg & IMM_MASK;
184}
185
186static inline __init u32 build_bimm(s32 arg)
187{
188 if (arg > 0x1ffff || arg < -0x20000)
189 printk(KERN_WARNING "Micro-assembler field overflow\n");
190
191 if (arg & 0x3)
192 printk(KERN_WARNING "Invalid micro-assembler branch target\n");
193
194 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
195}
196
197static inline __init u32 build_jimm(u32 arg)
198{
199 if (arg & ~((JIMM_MASK) << 2))
200 printk(KERN_WARNING "Micro-assembler field overflow\n");
201
202 return (arg >> 2) & JIMM_MASK;
203}
204
205static inline __init u32 build_func(u32 arg)
206{
207 if (arg & ~FUNC_MASK)
208 printk(KERN_WARNING "Micro-assembler field overflow\n");
209
210 return arg & FUNC_MASK;
211}
212
213static inline __init u32 build_set(u32 arg)
214{
215 if (arg & ~SET_MASK)
216 printk(KERN_WARNING "Micro-assembler field overflow\n");
217
218 return arg & SET_MASK;
219}
220
221/*
222 * The order of opcode arguments is implicitly left to right,
223 * starting with RS and ending with FUNC or IMM.
224 */
225static void __init build_insn(u32 **buf, enum opcode opc, ...)
226{
227 struct insn *ip = NULL;
228 unsigned int i;
229 va_list ap;
230 u32 op;
231
232 for (i = 0; insn_table[i].opcode != insn_invalid; i++)
233 if (insn_table[i].opcode == opc) {
234 ip = &insn_table[i];
235 break;
236 }
237
238 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
239 panic("Unsupported Micro-assembler instruction %d", opc);
240
241 op = ip->match;
242 va_start(ap, opc);
243 if (ip->fields & RS)
244 op |= build_rs(va_arg(ap, u32));
245 if (ip->fields & RT)
246 op |= build_rt(va_arg(ap, u32));
247 if (ip->fields & RD)
248 op |= build_rd(va_arg(ap, u32));
249 if (ip->fields & RE)
250 op |= build_re(va_arg(ap, u32));
251 if (ip->fields & SIMM)
252 op |= build_simm(va_arg(ap, s32));
253 if (ip->fields & UIMM)
254 op |= build_uimm(va_arg(ap, u32));
255 if (ip->fields & BIMM)
256 op |= build_bimm(va_arg(ap, s32));
257 if (ip->fields & JIMM)
258 op |= build_jimm(va_arg(ap, u32));
259 if (ip->fields & FUNC)
260 op |= build_func(va_arg(ap, u32));
261 if (ip->fields & SET)
262 op |= build_set(va_arg(ap, u32));
263 va_end(ap);
264
265 **buf = op;
266 (*buf)++;
267}
268
269#define I_u1u2u3(op) \
270Ip_u1u2u3(op) \
271{ \
272 build_insn(buf, insn##op, a, b, c); \
273}
274
275#define I_u2u1u3(op) \
276Ip_u2u1u3(op) \
277{ \
278 build_insn(buf, insn##op, b, a, c); \
279}
280
281#define I_u3u1u2(op) \
282Ip_u3u1u2(op) \
283{ \
284 build_insn(buf, insn##op, b, c, a); \
285}
286
287#define I_u1u2s3(op) \
288Ip_u1u2s3(op) \
289{ \
290 build_insn(buf, insn##op, a, b, c); \
291}
292
293#define I_u2s3u1(op) \
294Ip_u2s3u1(op) \
295{ \
296 build_insn(buf, insn##op, c, a, b); \
297}
298
299#define I_u2u1s3(op) \
300Ip_u2u1s3(op) \
301{ \
302 build_insn(buf, insn##op, b, a, c); \
303}
304
305#define I_u1u2(op) \
306Ip_u1u2(op) \
307{ \
308 build_insn(buf, insn##op, a, b); \
309}
310
311#define I_u1s2(op) \
312Ip_u1s2(op) \
313{ \
314 build_insn(buf, insn##op, a, b); \
315}
316
317#define I_u1(op) \
318Ip_u1(op) \
319{ \
320 build_insn(buf, insn##op, a); \
321}
322
323#define I_0(op) \
324Ip_0(op) \
325{ \
326 build_insn(buf, insn##op); \
327}
328
329I_u2u1s3(_addiu)
330I_u3u1u2(_addu)
331I_u2u1u3(_andi)
332I_u3u1u2(_and)
333I_u1u2s3(_beq)
334I_u1u2s3(_beql)
335I_u1s2(_bgez)
336I_u1s2(_bgezl)
337I_u1s2(_bltz)
338I_u1s2(_bltzl)
339I_u1u2s3(_bne)
340I_u1u2u3(_dmfc0)
341I_u1u2u3(_dmtc0)
342I_u2u1s3(_daddiu)
343I_u3u1u2(_daddu)
344I_u2u1u3(_dsll)
345I_u2u1u3(_dsll32)
346I_u2u1u3(_dsra)
347I_u2u1u3(_dsrl)
348I_u2u1u3(_dsrl32)
349I_u3u1u2(_dsubu)
350I_0(_eret)
351I_u1(_j)
352I_u1(_jal)
353I_u1(_jr)
354I_u2s3u1(_ld)
355I_u2s3u1(_ll)
356I_u2s3u1(_lld)
357I_u1s2(_lui)
358I_u2s3u1(_lw)
359I_u1u2u3(_mfc0)
360I_u1u2u3(_mtc0)
361I_u2u1u3(_ori)
362I_0(_rfe)
363I_u2s3u1(_sc)
364I_u2s3u1(_scd)
365I_u2s3u1(_sd)
366I_u2u1u3(_sll)
367I_u2u1u3(_sra)
368I_u2u1u3(_srl)
369I_u3u1u2(_subu)
370I_u2s3u1(_sw)
371I_0(_tlbp)
372I_0(_tlbwi)
373I_0(_tlbwr)
374I_u3u1u2(_xor)
375I_u2u1u3(_xori)
376
377/* Handle labels. */
378void __init uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
379{
380 (*lab)->addr = addr;
381 (*lab)->lab = lid;
382 (*lab)++;
383}
384
385int __init uasm_in_compat_space_p(long addr)
386{
387 /* Is this address in 32bit compat space? */
388#ifdef CONFIG_64BIT
389 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
390#else
391 return 1;
392#endif
393}
394
395int __init uasm_rel_highest(long val)
396{
397#ifdef CONFIG_64BIT
398 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
399#else
400 return 0;
401#endif
402}
403
404int __init uasm_rel_higher(long val)
405{
406#ifdef CONFIG_64BIT
407 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
408#else
409 return 0;
410#endif
411}
412
413int __init uasm_rel_hi(long val)
414{
415 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
416}
417
418int __init uasm_rel_lo(long val)
419{
420 return ((val & 0xffff) ^ 0x8000) - 0x8000;
421}
422
423void __init UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
424{
425 if (!uasm_in_compat_space_p(addr)) {
426 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
427 if (uasm_rel_higher(addr))
428 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
429 if (uasm_rel_hi(addr)) {
430 uasm_i_dsll(buf, rs, rs, 16);
431 uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
432 uasm_i_dsll(buf, rs, rs, 16);
433 } else
434 uasm_i_dsll32(buf, rs, rs, 0);
435 } else
436 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
437}
438
439void __init UASM_i_LA(u32 **buf, unsigned int rs, long addr)
440{
441 UASM_i_LA_mostly(buf, rs, addr);
442 if (uasm_rel_lo(addr)) {
443 if (!uasm_in_compat_space_p(addr))
444 uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
445 else
446 uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
447 }
448}
449
450/* Handle relocations. */
451void __init
452uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
453{
454 (*rel)->addr = addr;
455 (*rel)->type = R_MIPS_PC16;
456 (*rel)->lab = lid;
457 (*rel)++;
458}
459
460static inline void __init
461__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
462{
463 long laddr = (long)lab->addr;
464 long raddr = (long)rel->addr;
465
466 switch (rel->type) {
467 case R_MIPS_PC16:
468 *rel->addr |= build_bimm(laddr - (raddr + 4));
469 break;
470
471 default:
472 panic("Unsupported Micro-assembler relocation %d",
473 rel->type);
474 }
475}
476
477void __init
478uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
479{
480 struct uasm_label *l;
481
482 for (; rel->lab != UASM_LABEL_INVALID; rel++)
483 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
484 if (rel->lab == l->lab)
485 __resolve_relocs(rel, l);
486}
487
488void __init
489uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
490{
491 for (; rel->lab != UASM_LABEL_INVALID; rel++)
492 if (rel->addr >= first && rel->addr < end)
493 rel->addr += off;
494}
495
496void __init
497uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
498{
499 for (; lab->lab != UASM_LABEL_INVALID; lab++)
500 if (lab->addr >= first && lab->addr < end)
501 lab->addr += off;
502}
503
504void __init
505uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
506 u32 *end, u32 *target)
507{
508 long off = (long)(target - first);
509
510 memcpy(target, first, (end - first) * sizeof(u32));
511
512 uasm_move_relocs(rel, first, end, off);
513 uasm_move_labels(lab, first, end, off);
514}
515
516int __init uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
517{
518 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
519 if (rel->addr == addr
520 && (rel->type == R_MIPS_PC16
521 || rel->type == R_MIPS_26))
522 return 1;
523 }
524
525 return 0;
526}
527
528/* Convenience functions for labeled branches. */
529void __init
530uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
531{
532 uasm_r_mips_pc16(r, *p, lid);
533 uasm_i_bltz(p, reg, 0);
534}
535
536void __init
537uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
538{
539 uasm_r_mips_pc16(r, *p, lid);
540 uasm_i_b(p, 0);
541}
542
543void __init
544uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
545{
546 uasm_r_mips_pc16(r, *p, lid);
547 uasm_i_beqz(p, reg, 0);
548}
549
550void __init
551uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
552{
553 uasm_r_mips_pc16(r, *p, lid);
554 uasm_i_beqzl(p, reg, 0);
555}
556
557void __init
558uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
559{
560 uasm_r_mips_pc16(r, *p, lid);
561 uasm_i_bnez(p, reg, 0);
562}
563
564void __init
565uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
566{
567 uasm_r_mips_pc16(r, *p, lid);
568 uasm_i_bgezl(p, reg, 0);
569}
570
571void __init
572uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
573{
574 uasm_r_mips_pc16(r, *p, lid);
575 uasm_i_bgez(p, reg, 0);
576}
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