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e30ec452 TS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * A small micro-assembler. It is intentionally kept simple, does only | |
7 | * support a subset of instructions, and does not try to hide pipeline | |
8 | * effects like branch delay slots. | |
9 | * | |
70342287 | 10 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
e30ec452 TS |
11 | * Copyright (C) 2005, 2007 Maciej W. Rozycki |
12 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) | |
abc597fe | 13 | * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. |
e30ec452 TS |
14 | */ |
15 | ||
e30ec452 TS |
16 | enum fields { |
17 | RS = 0x001, | |
18 | RT = 0x002, | |
19 | RD = 0x004, | |
20 | RE = 0x008, | |
21 | SIMM = 0x010, | |
22 | UIMM = 0x020, | |
23 | BIMM = 0x040, | |
24 | JIMM = 0x080, | |
25 | FUNC = 0x100, | |
58b9e223 DD |
26 | SET = 0x200, |
27 | SCIMM = 0x400 | |
e30ec452 TS |
28 | }; |
29 | ||
30 | #define OP_MASK 0x3f | |
31 | #define OP_SH 26 | |
e30ec452 TS |
32 | #define RD_MASK 0x1f |
33 | #define RD_SH 11 | |
34 | #define RE_MASK 0x1f | |
35 | #define RE_SH 6 | |
36 | #define IMM_MASK 0xffff | |
37 | #define IMM_SH 0 | |
38 | #define JIMM_MASK 0x3ffffff | |
39 | #define JIMM_SH 0 | |
40 | #define FUNC_MASK 0x3f | |
41 | #define FUNC_SH 0 | |
42 | #define SET_MASK 0x7 | |
43 | #define SET_SH 0 | |
44 | ||
45 | enum opcode { | |
46 | insn_invalid, | |
71a1c776 SH |
47 | insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1, |
48 | insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, | |
49 | insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm, | |
4c12a854 | 50 | insn_divu, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll, |
71a1c776 | 51 | insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, |
49e9529b PB |
52 | insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld, |
53 | insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, | |
54 | insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, | |
f31318fd MC |
55 | insn_scd, insn_sd, insn_sll, insn_sllv, insn_sra, insn_srl, insn_srlv, |
56 | insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, | |
57 | insn_tlbwi, insn_tlbwr, insn_wait, insn_xor, insn_xori, insn_yield, | |
e30ec452 TS |
58 | }; |
59 | ||
60 | struct insn { | |
61 | enum opcode opcode; | |
62 | u32 match; | |
63 | enum fields fields; | |
64 | }; | |
65 | ||
078a55fc | 66 | static inline u32 build_rs(u32 arg) |
e30ec452 | 67 | { |
8d662c8d | 68 | WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
69 | |
70 | return (arg & RS_MASK) << RS_SH; | |
71 | } | |
72 | ||
078a55fc | 73 | static inline u32 build_rt(u32 arg) |
e30ec452 | 74 | { |
8d662c8d | 75 | WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
76 | |
77 | return (arg & RT_MASK) << RT_SH; | |
78 | } | |
79 | ||
078a55fc | 80 | static inline u32 build_rd(u32 arg) |
e30ec452 | 81 | { |
8d662c8d | 82 | WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
83 | |
84 | return (arg & RD_MASK) << RD_SH; | |
85 | } | |
86 | ||
078a55fc | 87 | static inline u32 build_re(u32 arg) |
e30ec452 | 88 | { |
8d662c8d | 89 | WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
90 | |
91 | return (arg & RE_MASK) << RE_SH; | |
92 | } | |
93 | ||
078a55fc | 94 | static inline u32 build_simm(s32 arg) |
e30ec452 | 95 | { |
8d662c8d DD |
96 | WARN(arg > 0x7fff || arg < -0x8000, |
97 | KERN_WARNING "Micro-assembler field overflow\n"); | |
e30ec452 TS |
98 | |
99 | return arg & 0xffff; | |
100 | } | |
101 | ||
078a55fc | 102 | static inline u32 build_uimm(u32 arg) |
e30ec452 | 103 | { |
8d662c8d | 104 | WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
105 | |
106 | return arg & IMM_MASK; | |
107 | } | |
108 | ||
078a55fc | 109 | static inline u32 build_scimm(u32 arg) |
58b9e223 | 110 | { |
8d662c8d DD |
111 | WARN(arg & ~SCIMM_MASK, |
112 | KERN_WARNING "Micro-assembler field overflow\n"); | |
58b9e223 DD |
113 | |
114 | return (arg & SCIMM_MASK) << SCIMM_SH; | |
115 | } | |
116 | ||
078a55fc | 117 | static inline u32 build_func(u32 arg) |
e30ec452 | 118 | { |
8d662c8d | 119 | WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
120 | |
121 | return arg & FUNC_MASK; | |
122 | } | |
123 | ||
078a55fc | 124 | static inline u32 build_set(u32 arg) |
e30ec452 | 125 | { |
8d662c8d | 126 | WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
e30ec452 TS |
127 | |
128 | return arg & SET_MASK; | |
129 | } | |
130 | ||
078a55fc | 131 | static void build_insn(u32 **buf, enum opcode opc, ...); |
e30ec452 TS |
132 | |
133 | #define I_u1u2u3(op) \ | |
134 | Ip_u1u2u3(op) \ | |
135 | { \ | |
136 | build_insn(buf, insn##op, a, b, c); \ | |
22b0763a DD |
137 | } \ |
138 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
139 | |
140 | #define I_u2u1u3(op) \ | |
141 | Ip_u2u1u3(op) \ | |
142 | { \ | |
143 | build_insn(buf, insn##op, b, a, c); \ | |
22b0763a DD |
144 | } \ |
145 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 | 146 | |
beef8e02 MC |
147 | #define I_u3u2u1(op) \ |
148 | Ip_u3u2u1(op) \ | |
149 | { \ | |
150 | build_insn(buf, insn##op, c, b, a); \ | |
151 | } \ | |
152 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
153 | ||
e30ec452 TS |
154 | #define I_u3u1u2(op) \ |
155 | Ip_u3u1u2(op) \ | |
156 | { \ | |
157 | build_insn(buf, insn##op, b, c, a); \ | |
22b0763a DD |
158 | } \ |
159 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
160 | |
161 | #define I_u1u2s3(op) \ | |
162 | Ip_u1u2s3(op) \ | |
163 | { \ | |
164 | build_insn(buf, insn##op, a, b, c); \ | |
22b0763a DD |
165 | } \ |
166 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
167 | |
168 | #define I_u2s3u1(op) \ | |
169 | Ip_u2s3u1(op) \ | |
170 | { \ | |
171 | build_insn(buf, insn##op, c, a, b); \ | |
22b0763a DD |
172 | } \ |
173 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
174 | |
175 | #define I_u2u1s3(op) \ | |
176 | Ip_u2u1s3(op) \ | |
177 | { \ | |
178 | build_insn(buf, insn##op, b, a, c); \ | |
22b0763a DD |
179 | } \ |
180 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 | 181 | |
92078e06 DD |
182 | #define I_u2u1msbu3(op) \ |
183 | Ip_u2u1msbu3(op) \ | |
184 | { \ | |
185 | build_insn(buf, insn##op, b, a, c+d-1, c); \ | |
22b0763a DD |
186 | } \ |
187 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
92078e06 | 188 | |
c42aef09 DD |
189 | #define I_u2u1msb32u3(op) \ |
190 | Ip_u2u1msbu3(op) \ | |
191 | { \ | |
192 | build_insn(buf, insn##op, b, a, c+d-33, c); \ | |
193 | } \ | |
194 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
195 | ||
70342287 | 196 | #define I_u2u1msbdu3(op) \ |
e6de1a09 SH |
197 | Ip_u2u1msbu3(op) \ |
198 | { \ | |
199 | build_insn(buf, insn##op, b, a, d-1, c); \ | |
200 | } \ | |
201 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
202 | ||
e30ec452 TS |
203 | #define I_u1u2(op) \ |
204 | Ip_u1u2(op) \ | |
205 | { \ | |
206 | build_insn(buf, insn##op, a, b); \ | |
22b0763a DD |
207 | } \ |
208 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 | 209 | |
d674dd14 PB |
210 | #define I_u2u1(op) \ |
211 | Ip_u1u2(op) \ | |
212 | { \ | |
213 | build_insn(buf, insn##op, b, a); \ | |
214 | } \ | |
215 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
216 | ||
e30ec452 TS |
217 | #define I_u1s2(op) \ |
218 | Ip_u1s2(op) \ | |
219 | { \ | |
220 | build_insn(buf, insn##op, a, b); \ | |
22b0763a DD |
221 | } \ |
222 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
223 | |
224 | #define I_u1(op) \ | |
225 | Ip_u1(op) \ | |
226 | { \ | |
227 | build_insn(buf, insn##op, a); \ | |
22b0763a DD |
228 | } \ |
229 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
230 | |
231 | #define I_0(op) \ | |
232 | Ip_0(op) \ | |
233 | { \ | |
234 | build_insn(buf, insn##op); \ | |
22b0763a DD |
235 | } \ |
236 | UASM_EXPORT_SYMBOL(uasm_i##op); | |
e30ec452 TS |
237 | |
238 | I_u2u1s3(_addiu) | |
239 | I_u3u1u2(_addu) | |
240 | I_u2u1u3(_andi) | |
241 | I_u3u1u2(_and) | |
242 | I_u1u2s3(_beq) | |
243 | I_u1u2s3(_beql) | |
244 | I_u1s2(_bgez) | |
245 | I_u1s2(_bgezl) | |
246 | I_u1s2(_bltz) | |
247 | I_u1s2(_bltzl) | |
248 | I_u1u2s3(_bne) | |
fb2a27e7 | 249 | I_u2s3u1(_cache) |
e30ec452 TS |
250 | I_u1u2u3(_dmfc0) |
251 | I_u1u2u3(_dmtc0) | |
252 | I_u2u1s3(_daddiu) | |
253 | I_u3u1u2(_daddu) | |
4c12a854 | 254 | I_u1u2(_divu) |
e30ec452 TS |
255 | I_u2u1u3(_dsll) |
256 | I_u2u1u3(_dsll32) | |
257 | I_u2u1u3(_dsra) | |
258 | I_u2u1u3(_dsrl) | |
259 | I_u2u1u3(_dsrl32) | |
92078e06 | 260 | I_u2u1u3(_drotr) |
de6d5b55 | 261 | I_u2u1u3(_drotr32) |
e30ec452 TS |
262 | I_u3u1u2(_dsubu) |
263 | I_0(_eret) | |
e6de1a09 SH |
264 | I_u2u1msbdu3(_ext) |
265 | I_u2u1msbu3(_ins) | |
e30ec452 TS |
266 | I_u1(_j) |
267 | I_u1(_jal) | |
49e9529b | 268 | I_u2u1(_jalr) |
e30ec452 TS |
269 | I_u1(_jr) |
270 | I_u2s3u1(_ld) | |
271 | I_u2s3u1(_ll) | |
272 | I_u2s3u1(_lld) | |
273 | I_u1s2(_lui) | |
274 | I_u2s3u1(_lw) | |
275 | I_u1u2u3(_mfc0) | |
276 | I_u1u2u3(_mtc0) | |
277 | I_u2u1u3(_ori) | |
5808184f | 278 | I_u3u1u2(_or) |
e30ec452 TS |
279 | I_0(_rfe) |
280 | I_u2s3u1(_sc) | |
281 | I_u2s3u1(_scd) | |
282 | I_u2s3u1(_sd) | |
283 | I_u2u1u3(_sll) | |
bef581ba | 284 | I_u3u2u1(_sllv) |
e30ec452 TS |
285 | I_u2u1u3(_sra) |
286 | I_u2u1u3(_srl) | |
f31318fd | 287 | I_u3u2u1(_srlv) |
32546f38 | 288 | I_u2u1u3(_rotr) |
e30ec452 TS |
289 | I_u3u1u2(_subu) |
290 | I_u2s3u1(_sw) | |
729ff561 | 291 | I_u1(_sync) |
e30ec452 | 292 | I_0(_tlbp) |
32546f38 | 293 | I_0(_tlbr) |
e30ec452 TS |
294 | I_0(_tlbwi) |
295 | I_0(_tlbwr) | |
53ed1389 | 296 | I_u1(_wait); |
e30ec452 TS |
297 | I_u3u1u2(_xor) |
298 | I_u2u1u3(_xori) | |
d674dd14 | 299 | I_u2u1(_yield) |
92078e06 | 300 | I_u2u1msbu3(_dins); |
c42aef09 | 301 | I_u2u1msb32u3(_dinsm); |
58b9e223 | 302 | I_u1(_syscall); |
5b97c3f7 DD |
303 | I_u1u2s3(_bbit0); |
304 | I_u1u2s3(_bbit1); | |
bb3d68c3 DD |
305 | I_u3u1u2(_lwx) |
306 | I_u3u1u2(_ldx) | |
e30ec452 | 307 | |
c9941158 DD |
308 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
309 | #include <asm/octeon/octeon.h> | |
078a55fc | 310 | void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b, |
c9941158 DD |
311 | unsigned int c) |
312 | { | |
313 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5) | |
314 | /* | |
315 | * As per erratum Core-14449, replace prefetches 0-4, | |
316 | * 6-24 with 'pref 28'. | |
317 | */ | |
318 | build_insn(buf, insn_pref, c, 28, b); | |
319 | else | |
320 | build_insn(buf, insn_pref, c, a, b); | |
321 | } | |
abc597fe | 322 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref)); |
c9941158 DD |
323 | #else |
324 | I_u2s3u1(_pref) | |
325 | #endif | |
326 | ||
e30ec452 | 327 | /* Handle labels. */ |
078a55fc | 328 | void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid) |
e30ec452 TS |
329 | { |
330 | (*lab)->addr = addr; | |
331 | (*lab)->lab = lid; | |
332 | (*lab)++; | |
333 | } | |
abc597fe | 334 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label)); |
e30ec452 | 335 | |
078a55fc | 336 | int ISAFUNC(uasm_in_compat_space_p)(long addr) |
e30ec452 TS |
337 | { |
338 | /* Is this address in 32bit compat space? */ | |
339 | #ifdef CONFIG_64BIT | |
340 | return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); | |
341 | #else | |
342 | return 1; | |
343 | #endif | |
344 | } | |
abc597fe | 345 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p)); |
e30ec452 | 346 | |
078a55fc | 347 | static int uasm_rel_highest(long val) |
e30ec452 TS |
348 | { |
349 | #ifdef CONFIG_64BIT | |
350 | return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; | |
351 | #else | |
352 | return 0; | |
353 | #endif | |
354 | } | |
355 | ||
078a55fc | 356 | static int uasm_rel_higher(long val) |
e30ec452 TS |
357 | { |
358 | #ifdef CONFIG_64BIT | |
359 | return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; | |
360 | #else | |
361 | return 0; | |
362 | #endif | |
363 | } | |
364 | ||
078a55fc | 365 | int ISAFUNC(uasm_rel_hi)(long val) |
e30ec452 TS |
366 | { |
367 | return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; | |
368 | } | |
abc597fe | 369 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi)); |
e30ec452 | 370 | |
078a55fc | 371 | int ISAFUNC(uasm_rel_lo)(long val) |
e30ec452 TS |
372 | { |
373 | return ((val & 0xffff) ^ 0x8000) - 0x8000; | |
374 | } | |
abc597fe | 375 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo)); |
e30ec452 | 376 | |
078a55fc | 377 | void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr) |
e30ec452 | 378 | { |
abc597fe SH |
379 | if (!ISAFUNC(uasm_in_compat_space_p)(addr)) { |
380 | ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr)); | |
e30ec452 | 381 | if (uasm_rel_higher(addr)) |
abc597fe SH |
382 | ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr)); |
383 | if (ISAFUNC(uasm_rel_hi(addr))) { | |
384 | ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); | |
385 | ISAFUNC(uasm_i_daddiu)(buf, rs, rs, | |
386 | ISAFUNC(uasm_rel_hi)(addr)); | |
387 | ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16); | |
e30ec452 | 388 | } else |
abc597fe | 389 | ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0); |
e30ec452 | 390 | } else |
abc597fe | 391 | ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr))); |
e30ec452 | 392 | } |
abc597fe | 393 | UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly)); |
e30ec452 | 394 | |
078a55fc | 395 | void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr) |
e30ec452 | 396 | { |
abc597fe SH |
397 | ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr); |
398 | if (ISAFUNC(uasm_rel_lo(addr))) { | |
399 | if (!ISAFUNC(uasm_in_compat_space_p)(addr)) | |
400 | ISAFUNC(uasm_i_daddiu)(buf, rs, rs, | |
401 | ISAFUNC(uasm_rel_lo(addr))); | |
e30ec452 | 402 | else |
abc597fe SH |
403 | ISAFUNC(uasm_i_addiu)(buf, rs, rs, |
404 | ISAFUNC(uasm_rel_lo(addr))); | |
e30ec452 TS |
405 | } |
406 | } | |
abc597fe | 407 | UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA)); |
e30ec452 TS |
408 | |
409 | /* Handle relocations. */ | |
078a55fc | 410 | void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid) |
e30ec452 TS |
411 | { |
412 | (*rel)->addr = addr; | |
413 | (*rel)->type = R_MIPS_PC16; | |
414 | (*rel)->lab = lid; | |
415 | (*rel)++; | |
416 | } | |
abc597fe | 417 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16)); |
e30ec452 | 418 | |
078a55fc PG |
419 | static inline void __resolve_relocs(struct uasm_reloc *rel, |
420 | struct uasm_label *lab); | |
e30ec452 | 421 | |
078a55fc PG |
422 | void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel, |
423 | struct uasm_label *lab) | |
e30ec452 TS |
424 | { |
425 | struct uasm_label *l; | |
426 | ||
427 | for (; rel->lab != UASM_LABEL_INVALID; rel++) | |
428 | for (l = lab; l->lab != UASM_LABEL_INVALID; l++) | |
429 | if (rel->lab == l->lab) | |
430 | __resolve_relocs(rel, l); | |
431 | } | |
abc597fe | 432 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs)); |
e30ec452 | 433 | |
078a55fc PG |
434 | void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end, |
435 | long off) | |
e30ec452 TS |
436 | { |
437 | for (; rel->lab != UASM_LABEL_INVALID; rel++) | |
438 | if (rel->addr >= first && rel->addr < end) | |
439 | rel->addr += off; | |
440 | } | |
abc597fe | 441 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs)); |
e30ec452 | 442 | |
078a55fc PG |
443 | void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end, |
444 | long off) | |
e30ec452 TS |
445 | { |
446 | for (; lab->lab != UASM_LABEL_INVALID; lab++) | |
447 | if (lab->addr >= first && lab->addr < end) | |
448 | lab->addr += off; | |
449 | } | |
abc597fe | 450 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels)); |
e30ec452 | 451 | |
078a55fc PG |
452 | void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab, |
453 | u32 *first, u32 *end, u32 *target) | |
e30ec452 TS |
454 | { |
455 | long off = (long)(target - first); | |
456 | ||
457 | memcpy(target, first, (end - first) * sizeof(u32)); | |
458 | ||
abc597fe SH |
459 | ISAFUNC(uasm_move_relocs(rel, first, end, off)); |
460 | ISAFUNC(uasm_move_labels(lab, first, end, off)); | |
e30ec452 | 461 | } |
abc597fe | 462 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler)); |
e30ec452 | 463 | |
078a55fc | 464 | int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr) |
e30ec452 TS |
465 | { |
466 | for (; rel->lab != UASM_LABEL_INVALID; rel++) { | |
467 | if (rel->addr == addr | |
468 | && (rel->type == R_MIPS_PC16 | |
469 | || rel->type == R_MIPS_26)) | |
470 | return 1; | |
471 | } | |
472 | ||
473 | return 0; | |
474 | } | |
abc597fe | 475 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay)); |
e30ec452 TS |
476 | |
477 | /* Convenience functions for labeled branches. */ | |
078a55fc PG |
478 | void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
479 | int lid) | |
e30ec452 TS |
480 | { |
481 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 482 | ISAFUNC(uasm_i_bltz)(p, reg, 0); |
e30ec452 | 483 | } |
abc597fe | 484 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz)); |
e30ec452 | 485 | |
078a55fc | 486 | void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid) |
e30ec452 TS |
487 | { |
488 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 489 | ISAFUNC(uasm_i_b)(p, 0); |
e30ec452 | 490 | } |
abc597fe | 491 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b)); |
e30ec452 | 492 | |
8dee5901 PB |
493 | void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1, |
494 | unsigned int r2, int lid) | |
495 | { | |
496 | uasm_r_mips_pc16(r, *p, lid); | |
497 | ISAFUNC(uasm_i_beq)(p, r1, r2, 0); | |
498 | } | |
499 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq)); | |
500 | ||
078a55fc PG |
501 | void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
502 | int lid) | |
e30ec452 TS |
503 | { |
504 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 505 | ISAFUNC(uasm_i_beqz)(p, reg, 0); |
e30ec452 | 506 | } |
abc597fe | 507 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz)); |
e30ec452 | 508 | |
078a55fc PG |
509 | void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
510 | int lid) | |
e30ec452 TS |
511 | { |
512 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 513 | ISAFUNC(uasm_i_beqzl)(p, reg, 0); |
e30ec452 | 514 | } |
abc597fe | 515 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl)); |
e30ec452 | 516 | |
078a55fc PG |
517 | void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1, |
518 | unsigned int reg2, int lid) | |
fb2a27e7 TS |
519 | { |
520 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 521 | ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0); |
fb2a27e7 | 522 | } |
abc597fe | 523 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne)); |
fb2a27e7 | 524 | |
078a55fc PG |
525 | void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
526 | int lid) | |
e30ec452 TS |
527 | { |
528 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 529 | ISAFUNC(uasm_i_bnez)(p, reg, 0); |
e30ec452 | 530 | } |
abc597fe | 531 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez)); |
e30ec452 | 532 | |
078a55fc PG |
533 | void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
534 | int lid) | |
e30ec452 TS |
535 | { |
536 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 537 | ISAFUNC(uasm_i_bgezl)(p, reg, 0); |
e30ec452 | 538 | } |
abc597fe | 539 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl)); |
e30ec452 | 540 | |
078a55fc PG |
541 | void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
542 | int lid) | |
e30ec452 TS |
543 | { |
544 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 545 | ISAFUNC(uasm_i_bgez)(p, reg, 0); |
e30ec452 | 546 | } |
abc597fe | 547 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez)); |
5b97c3f7 | 548 | |
078a55fc PG |
549 | void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
550 | unsigned int bit, int lid) | |
5b97c3f7 DD |
551 | { |
552 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 553 | ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0); |
5b97c3f7 | 554 | } |
abc597fe | 555 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0)); |
5b97c3f7 | 556 | |
078a55fc PG |
557 | void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg, |
558 | unsigned int bit, int lid) | |
5b97c3f7 DD |
559 | { |
560 | uasm_r_mips_pc16(r, *p, lid); | |
abc597fe | 561 | ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0); |
5b97c3f7 | 562 | } |
abc597fe | 563 | UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1)); |