[mirror_ubuntu-zesty-kernel.git] / arch / mips / mm / uasm.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * A small micro-assembler. It is intentionally kept simple, does only
 * support a subset of instructions, and does not try to hide pipeline
 * effects like branch delay slots.
 *
 * Copyright (C) 2004, 2005, 2006, 2008	 Thiemo Seufer
 * Copyright (C) 2005, 2007  Maciej W. Rozycki
 * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2012, 2013  MIPS Technologies, Inc.  All rights reserved.
 */

enum fields {
	RS = 0x001,
	RT = 0x002,
	RD = 0x004,
	RE = 0x008,
	SIMM = 0x010,
	UIMM = 0x020,
	BIMM = 0x040,
	JIMM = 0x080,
	FUNC = 0x100,
	SET = 0x200,
	SCIMM = 0x400
};

#define OP_MASK		0x3f
#define OP_SH		26
#define RD_MASK		0x1f
#define RD_SH		11
#define RE_MASK		0x1f
#define RE_SH		6
#define IMM_MASK	0xffff
#define IMM_SH		0
#define JIMM_MASK	0x3ffffff
#define JIMM_SH		0
#define FUNC_MASK	0x3f
#define FUNC_SH		0
#define SET_MASK	0x7
#define SET_SH		0

enum opcode {
	insn_invalid,
	insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
	insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
	insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
	insn_divu, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
	insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
	insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb,
	insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw,
	insn_lwx, insn_mfc0, insn_mfhi, insn_mflo, insn_mtc0, insn_mul,
	insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,
	insn_sd, insn_sll, insn_sllv, insn_sltiu, insn_sltu, insn_sra,
	insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,
	insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh,
	insn_xor, insn_xori, insn_yield,
};

struct insn {
	enum opcode opcode;
	u32 match;
	enum fields fields;
};

static inline u32 build_rs(u32 arg)
{
	WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RS_MASK) << RS_SH;
}

static inline u32 build_rt(u32 arg)
{
	WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RT_MASK) << RT_SH;
}

static inline u32 build_rd(u32 arg)
{
	WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RD_MASK) << RD_SH;
}

static inline u32 build_re(u32 arg)
{
	WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RE_MASK) << RE_SH;
}

static inline u32 build_simm(s32 arg)
{
	WARN(arg > 0x7fff || arg < -0x8000,
	     KERN_WARNING "Micro-assembler field overflow\n");

	return arg & 0xffff;
}

static inline u32 build_uimm(u32 arg)
{
	WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & IMM_MASK;
}

static inline u32 build_scimm(u32 arg)
{
	WARN(arg & ~SCIMM_MASK,
	     KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & SCIMM_MASK) << SCIMM_SH;
}

static inline u32 build_func(u32 arg)
{
	WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & FUNC_MASK;
}

static inline u32 build_set(u32 arg)
{
	WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & SET_MASK;
}

static void build_insn(u32 **buf, enum opcode opc, ...);

#define I_u1u2u3(op)					\
Ip_u1u2u3(op)						\
{							\
	build_insn(buf, insn##op, a, b, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_s3s1s2(op)					\
Ip_s3s1s2(op)						\
{							\
	build_insn(buf, insn##op, b, c, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1u3(op)					\
Ip_u2u1u3(op)						\
{							\
	build_insn(buf, insn##op, b, a, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u3u2u1(op)					\
Ip_u3u2u1(op)						\
{							\
	build_insn(buf, insn##op, c, b, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u3u1u2(op)					\
Ip_u3u1u2(op)						\
{							\
	build_insn(buf, insn##op, b, c, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1u2s3(op)					\
Ip_u1u2s3(op)						\
{							\
	build_insn(buf, insn##op, a, b, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2s3u1(op)					\
Ip_u2s3u1(op)						\
{							\
	build_insn(buf, insn##op, c, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1s3(op)					\
Ip_u2u1s3(op)						\
{							\
	build_insn(buf, insn##op, b, a, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msbu3(op)					\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, c+d-1, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msb32u3(op)				\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, c+d-33, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msbdu3(op)				\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, d-1, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1u2(op)					\
Ip_u1u2(op)						\
{							\
	build_insn(buf, insn##op, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1(op)					\
Ip_u1u2(op)						\
{							\
	build_insn(buf, insn##op, b, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1s2(op)					\
Ip_u1s2(op)						\
{							\
	build_insn(buf, insn##op, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1(op)					\
Ip_u1(op)						\
{							\
	build_insn(buf, insn##op, a);			\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_0(op)						\
Ip_0(op)						\
{							\
	build_insn(buf, insn##op);			\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

I_u2u1s3(_addiu)
I_u3u1u2(_addu)
I_u2u1u3(_andi)
I_u3u1u2(_and)
I_u1u2s3(_beq)
I_u1u2s3(_beql)
I_u1s2(_bgez)
I_u1s2(_bgezl)
I_u1s2(_bltz)
I_u1s2(_bltzl)
I_u1u2s3(_bne)
I_u2s3u1(_cache)
I_u1u2u3(_dmfc0)
I_u1u2u3(_dmtc0)
I_u2u1s3(_daddiu)
I_u3u1u2(_daddu)
I_u1u2(_divu)
I_u2u1u3(_dsll)
I_u2u1u3(_dsll32)
I_u2u1u3(_dsra)
I_u2u1u3(_dsrl)
I_u2u1u3(_dsrl32)
I_u2u1u3(_drotr)
I_u2u1u3(_drotr32)
I_u3u1u2(_dsubu)
I_0(_eret)
I_u2u1msbdu3(_ext)
I_u2u1msbu3(_ins)
I_u1(_j)
I_u1(_jal)
I_u2u1(_jalr)
I_u1(_jr)
I_u2s3u1(_lb)
I_u2s3u1(_ld)
I_u2s3u1(_lh)
I_u2s3u1(_ll)
I_u2s3u1(_lld)
I_u1s2(_lui)
I_u2s3u1(_lw)
I_u1u2u3(_mfc0)
I_u1(_mfhi)
I_u1(_mflo)
I_u1u2u3(_mtc0)
I_u3u1u2(_mul)
I_u2u1u3(_ori)
I_u3u1u2(_or)
I_0(_rfe)
I_u2s3u1(_sc)
I_u2s3u1(_scd)
I_u2s3u1(_sd)
I_u2u1u3(_sll)
I_u3u2u1(_sllv)
I_u2u1s3(_sltiu)
I_u3u1u2(_sltu)
I_u2u1u3(_sra)
I_u2u1u3(_srl)
I_u3u2u1(_srlv)
I_u2u1u3(_rotr)
I_u3u1u2(_subu)
I_u2s3u1(_sw)
I_u1(_sync)
I_0(_tlbp)
I_0(_tlbr)
I_0(_tlbwi)
I_0(_tlbwr)
I_u1(_wait);
I_u2u1(_wsbh)
I_u3u1u2(_xor)
I_u2u1u3(_xori)
I_u2u1(_yield)
I_u2u1msbu3(_dins);
I_u2u1msb32u3(_dinsm);
I_u1(_syscall);
I_u1u2s3(_bbit0);
I_u1u2s3(_bbit1);
I_u3u1u2(_lwx)
I_u3u1u2(_ldx)

#ifdef CONFIG_CPU_CAVIUM_OCTEON
#include <asm/octeon/octeon.h>
void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
			    unsigned int c)
{
	if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
		/*
		 * As per erratum Core-14449, replace prefetches 0-4,
		 * 6-24 with 'pref 28'.
		 */
		build_insn(buf, insn_pref, c, 28, b);
	else
		build_insn(buf, insn_pref, c, a, b);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
#else
I_u2s3u1(_pref)
#endif

/* Handle labels. */
void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid)
{
	(*lab)->addr = addr;
	(*lab)->lab = lid;
	(*lab)++;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));

int ISAFUNC(uasm_in_compat_space_p)(long addr)
{
	/* Is this address in 32bit compat space? */
#ifdef CONFIG_64BIT
	return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
#else
	return 1;
#endif
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));

static int uasm_rel_highest(long val)
{
#ifdef CONFIG_64BIT
	return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
#else
	return 0;
#endif
}

static int uasm_rel_higher(long val)
{
#ifdef CONFIG_64BIT
	return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
#else
	return 0;
#endif
}

int ISAFUNC(uasm_rel_hi)(long val)
{
	return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));

int ISAFUNC(uasm_rel_lo)(long val)
{
	return ((val & 0xffff) ^ 0x8000) - 0x8000;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));

void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
{
	if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
		ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
		if (uasm_rel_higher(addr))
			ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
		if (ISAFUNC(uasm_rel_hi(addr))) {
			ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
			ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
					ISAFUNC(uasm_rel_hi)(addr));
			ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
		} else
			ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
	} else
		ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
}
UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));

void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
{
	ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
	if (ISAFUNC(uasm_rel_lo(addr))) {
		if (!ISAFUNC(uasm_in_compat_space_p)(addr))
			ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
					ISAFUNC(uasm_rel_lo(addr)));
		else
			ISAFUNC(uasm_i_addiu)(buf, rs, rs,
					ISAFUNC(uasm_rel_lo(addr)));
	}
}
UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));

/* Handle relocations. */
void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
{
	(*rel)->addr = addr;
	(*rel)->type = R_MIPS_PC16;
	(*rel)->lab = lid;
	(*rel)++;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));

static inline void __resolve_relocs(struct uasm_reloc *rel,
				    struct uasm_label *lab);

void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
				  struct uasm_label *lab)
{
	struct uasm_label *l;

	for (; rel->lab != UASM_LABEL_INVALID; rel++)
		for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
			if (rel->lab == l->lab)
				__resolve_relocs(rel, l);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));

void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end,
			       long off)
{
	for (; rel->lab != UASM_LABEL_INVALID; rel++)
		if (rel->addr >= first && rel->addr < end)
			rel->addr += off;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));

void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end,
			       long off)
{
	for (; lab->lab != UASM_LABEL_INVALID; lab++)
		if (lab->addr >= first && lab->addr < end)
			lab->addr += off;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));

void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab,
				u32 *first, u32 *end, u32 *target)
{
	long off = (long)(target - first);

	memcpy(target, first, (end - first) * sizeof(u32));

	ISAFUNC(uasm_move_relocs(rel, first, end, off));
	ISAFUNC(uasm_move_labels(lab, first, end, off));
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));

int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
{
	for (; rel->lab != UASM_LABEL_INVALID; rel++) {
		if (rel->addr == addr
		    && (rel->type == R_MIPS_PC16
			|| rel->type == R_MIPS_26))
			return 1;
	}

	return 0;
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));

/* Convenience functions for labeled branches. */
void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bltz)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));

void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_b)(p, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));

void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1,
			  unsigned int r2, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_beq)(p, r1, r2, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq));

void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_beqz)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));

void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_beqzl)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));

void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1,
			  unsigned int reg2, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));

void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bnez)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));

void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bgezl)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));

void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bgez)(p, reg, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));

void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    unsigned int bit, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));

void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    unsigned int bit, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
}
UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));
Commit	Line	Data
e30ec452 TS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* A small micro-assembler. It is intentionally kept simple, does only
	7	* support a subset of instructions, and does not try to hide pipeline
	8	* effects like branch delay slots.
	9	*
70342287	10	* Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
e30ec452 TS	11	* Copyright (C) 2005, 2007 Maciej W. Rozycki
e30ec452 TS	12	* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
abc597fe	13	* Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
e30ec452 TS	14	*/
e30ec452 TS	15
e30ec452 TS	16	enum fields {
	17	RS = 0x001,
	18	RT = 0x002,
	19	RD = 0x004,
	20	RE = 0x008,
	21	SIMM = 0x010,
	22	UIMM = 0x020,
	23	BIMM = 0x040,
	24	JIMM = 0x080,
	25	FUNC = 0x100,
58b9e223 DD	26	SET = 0x200,
58b9e223 DD	27	SCIMM = 0x400
e30ec452 TS	28	};
	29
	30	#define OP_MASK 0x3f
	31	#define OP_SH 26
e30ec452 TS	32	#define RD_MASK 0x1f
	33	#define RD_SH 11
	34	#define RE_MASK 0x1f
	35	#define RE_SH 6
	36	#define IMM_MASK 0xffff
	37	#define IMM_SH 0
	38	#define JIMM_MASK 0x3ffffff
	39	#define JIMM_SH 0
	40	#define FUNC_MASK 0x3f
	41	#define FUNC_SH 0
	42	#define SET_MASK 0x7
	43	#define SET_SH 0
	44
	45	enum opcode {
	46	insn_invalid,
71a1c776 SH	47	insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
	48	insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
	49	insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
4c12a854	50	insn_divu, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
71a1c776	51	insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
82488818 MC	52	insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb,
	53	insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw,
	54	insn_lwx, insn_mfc0, insn_mfhi, insn_mflo, insn_mtc0, insn_mul,
	55	insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,
	56	insn_sd, insn_sll, insn_sllv, insn_sltiu, insn_sltu, insn_sra,
	57	insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,
	58	insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh,
	59	insn_xor, insn_xori, insn_yield,
e30ec452 TS	60	};
	61
	62	struct insn {
	63	enum opcode opcode;
	64	u32 match;
	65	enum fields fields;
	66	};
	67
078a55fc	68	static inline u32 build_rs(u32 arg)
e30ec452	69	{
8d662c8d	70	WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	71
	72	return (arg & RS_MASK) << RS_SH;
	73	}
	74
078a55fc	75	static inline u32 build_rt(u32 arg)
e30ec452	76	{
8d662c8d	77	WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	78
	79	return (arg & RT_MASK) << RT_SH;
	80	}
	81
078a55fc	82	static inline u32 build_rd(u32 arg)
e30ec452	83	{
8d662c8d	84	WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	85
	86	return (arg & RD_MASK) << RD_SH;
	87	}
	88
078a55fc	89	static inline u32 build_re(u32 arg)
e30ec452	90	{
8d662c8d	91	WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	92
	93	return (arg & RE_MASK) << RE_SH;
	94	}
	95
078a55fc	96	static inline u32 build_simm(s32 arg)
e30ec452	97	{
8d662c8d DD	98	WARN(arg > 0x7fff \|\| arg < -0x8000,
8d662c8d DD	99	KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	100
	101	return arg & 0xffff;
	102	}
	103
078a55fc	104	static inline u32 build_uimm(u32 arg)
e30ec452	105	{
8d662c8d	106	WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	107
	108	return arg & IMM_MASK;
	109	}
	110
078a55fc	111	static inline u32 build_scimm(u32 arg)
58b9e223	112	{
8d662c8d DD	113	WARN(arg & ~SCIMM_MASK,
8d662c8d DD	114	KERN_WARNING "Micro-assembler field overflow\n");
58b9e223 DD	115
	116	return (arg & SCIMM_MASK) << SCIMM_SH;
	117	}
	118
078a55fc	119	static inline u32 build_func(u32 arg)
e30ec452	120	{
8d662c8d	121	WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	122
	123	return arg & FUNC_MASK;
	124	}
	125
078a55fc	126	static inline u32 build_set(u32 arg)
e30ec452	127	{
8d662c8d	128	WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	129
	130	return arg & SET_MASK;
	131	}
	132
078a55fc	133	static void build_insn(u32 **buf, enum opcode opc, ...);
e30ec452 TS	134
	135	#define I_u1u2u3(op) \
	136	Ip_u1u2u3(op) \
	137	{ \
	138	build_insn(buf, insn##op, a, b, c); \
22b0763a DD	139	} \
22b0763a DD	140	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452	141
9d987369 MC	142	#define I_s3s1s2(op) \
	143	Ip_s3s1s2(op) \
	144	{ \
	145	build_insn(buf, insn##op, b, c, a); \
	146	} \
	147	UASM_EXPORT_SYMBOL(uasm_i##op);
	148
e30ec452 TS	149	#define I_u2u1u3(op) \
	150	Ip_u2u1u3(op) \
	151	{ \
	152	build_insn(buf, insn##op, b, a, c); \
22b0763a DD	153	} \
22b0763a DD	154	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452	155
beef8e02 MC	156	#define I_u3u2u1(op) \
	157	Ip_u3u2u1(op) \
	158	{ \
	159	build_insn(buf, insn##op, c, b, a); \
	160	} \
	161	UASM_EXPORT_SYMBOL(uasm_i##op);
	162
e30ec452 TS	163	#define I_u3u1u2(op) \
	164	Ip_u3u1u2(op) \
	165	{ \
	166	build_insn(buf, insn##op, b, c, a); \
22b0763a DD	167	} \
22b0763a DD	168	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	169
	170	#define I_u1u2s3(op) \
	171	Ip_u1u2s3(op) \
	172	{ \
	173	build_insn(buf, insn##op, a, b, c); \
22b0763a DD	174	} \
22b0763a DD	175	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	176
	177	#define I_u2s3u1(op) \
	178	Ip_u2s3u1(op) \
	179	{ \
	180	build_insn(buf, insn##op, c, a, b); \
22b0763a DD	181	} \
22b0763a DD	182	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	183
	184	#define I_u2u1s3(op) \
	185	Ip_u2u1s3(op) \
	186	{ \
	187	build_insn(buf, insn##op, b, a, c); \
22b0763a DD	188	} \
22b0763a DD	189	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452	190
92078e06 DD	191	#define I_u2u1msbu3(op) \
	192	Ip_u2u1msbu3(op) \
	193	{ \
	194	build_insn(buf, insn##op, b, a, c+d-1, c); \
22b0763a DD	195	} \
22b0763a DD	196	UASM_EXPORT_SYMBOL(uasm_i##op);
92078e06	197
c42aef09 DD	198	#define I_u2u1msb32u3(op) \
	199	Ip_u2u1msbu3(op) \
	200	{ \
	201	build_insn(buf, insn##op, b, a, c+d-33, c); \
	202	} \
	203	UASM_EXPORT_SYMBOL(uasm_i##op);
	204
70342287	205	#define I_u2u1msbdu3(op) \
e6de1a09 SH	206	Ip_u2u1msbu3(op) \
	207	{ \
	208	build_insn(buf, insn##op, b, a, d-1, c); \
	209	} \
	210	UASM_EXPORT_SYMBOL(uasm_i##op);
	211
e30ec452 TS	212	#define I_u1u2(op) \
	213	Ip_u1u2(op) \
	214	{ \
	215	build_insn(buf, insn##op, a, b); \
22b0763a DD	216	} \
22b0763a DD	217	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452	218
d674dd14 PB	219	#define I_u2u1(op) \
	220	Ip_u1u2(op) \
	221	{ \
	222	build_insn(buf, insn##op, b, a); \
	223	} \
	224	UASM_EXPORT_SYMBOL(uasm_i##op);
	225
e30ec452 TS	226	#define I_u1s2(op) \
	227	Ip_u1s2(op) \
	228	{ \
	229	build_insn(buf, insn##op, a, b); \
22b0763a DD	230	} \
22b0763a DD	231	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	232
	233	#define I_u1(op) \
	234	Ip_u1(op) \
	235	{ \
	236	build_insn(buf, insn##op, a); \
22b0763a DD	237	} \
22b0763a DD	238	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	239
	240	#define I_0(op) \
	241	Ip_0(op) \
	242	{ \
	243	build_insn(buf, insn##op); \
22b0763a DD	244	} \
22b0763a DD	245	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	246
	247	I_u2u1s3(_addiu)
	248	I_u3u1u2(_addu)
	249	I_u2u1u3(_andi)
	250	I_u3u1u2(_and)
	251	I_u1u2s3(_beq)
	252	I_u1u2s3(_beql)
	253	I_u1s2(_bgez)
	254	I_u1s2(_bgezl)
	255	I_u1s2(_bltz)
	256	I_u1s2(_bltzl)
	257	I_u1u2s3(_bne)
fb2a27e7	258	I_u2s3u1(_cache)
e30ec452 TS	259	I_u1u2u3(_dmfc0)
	260	I_u1u2u3(_dmtc0)
	261	I_u2u1s3(_daddiu)
	262	I_u3u1u2(_daddu)
4c12a854	263	I_u1u2(_divu)
e30ec452 TS	264	I_u2u1u3(_dsll)
	265	I_u2u1u3(_dsll32)
	266	I_u2u1u3(_dsra)
	267	I_u2u1u3(_dsrl)
	268	I_u2u1u3(_dsrl32)
92078e06	269	I_u2u1u3(_drotr)
de6d5b55	270	I_u2u1u3(_drotr32)
e30ec452 TS	271	I_u3u1u2(_dsubu)
e30ec452 TS	272	I_0(_eret)
e6de1a09 SH	273	I_u2u1msbdu3(_ext)
e6de1a09 SH	274	I_u2u1msbu3(_ins)
e30ec452 TS	275	I_u1(_j)
e30ec452 TS	276	I_u1(_jal)
49e9529b	277	I_u2u1(_jalr)
e30ec452	278	I_u1(_jr)
82488818	279	I_u2s3u1(_lb)
e30ec452	280	I_u2s3u1(_ld)
d6b3314b	281	I_u2s3u1(_lh)
e30ec452 TS	282	I_u2s3u1(_ll)
	283	I_u2s3u1(_lld)
	284	I_u1s2(_lui)
	285	I_u2s3u1(_lw)
	286	I_u1u2u3(_mfc0)
f3ec7a23	287	I_u1(_mfhi)
16d21a81	288	I_u1(_mflo)
e30ec452	289	I_u1u2u3(_mtc0)
a8e897ad	290	I_u3u1u2(_mul)
e30ec452	291	I_u2u1u3(_ori)
5808184f	292	I_u3u1u2(_or)
e30ec452 TS	293	I_0(_rfe)
	294	I_u2s3u1(_sc)
	295	I_u2s3u1(_scd)
	296	I_u2s3u1(_sd)
	297	I_u2u1u3(_sll)
bef581ba	298	I_u3u2u1(_sllv)
390363ed	299	I_u2u1s3(_sltiu)
e8ef868b	300	I_u3u1u2(_sltu)
e30ec452 TS	301	I_u2u1u3(_sra)
e30ec452 TS	302	I_u2u1u3(_srl)
f31318fd	303	I_u3u2u1(_srlv)
32546f38	304	I_u2u1u3(_rotr)
e30ec452 TS	305	I_u3u1u2(_subu)
e30ec452 TS	306	I_u2s3u1(_sw)
729ff561	307	I_u1(_sync)
e30ec452	308	I_0(_tlbp)
32546f38	309	I_0(_tlbr)
e30ec452 TS	310	I_0(_tlbwi)
e30ec452 TS	311	I_0(_tlbwr)
53ed1389	312	I_u1(_wait);
ab9e4fa0	313	I_u2u1(_wsbh)
e30ec452 TS	314	I_u3u1u2(_xor)
e30ec452 TS	315	I_u2u1u3(_xori)
d674dd14	316	I_u2u1(_yield)
92078e06	317	I_u2u1msbu3(_dins);
c42aef09	318	I_u2u1msb32u3(_dinsm);
58b9e223	319	I_u1(_syscall);
5b97c3f7 DD	320	I_u1u2s3(_bbit0);
5b97c3f7 DD	321	I_u1u2s3(_bbit1);
bb3d68c3 DD	322	I_u3u1u2(_lwx)
bb3d68c3 DD	323	I_u3u1u2(_ldx)
e30ec452	324
c9941158 DD	325	#ifdef CONFIG_CPU_CAVIUM_OCTEON
c9941158 DD	326	#include <asm/octeon/octeon.h>
078a55fc	327	void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
c9941158 DD	328	unsigned int c)
	329	{
	330	if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
	331	/*
	332	* As per erratum Core-14449, replace prefetches 0-4,
	333	* 6-24 with 'pref 28'.
	334	*/
	335	build_insn(buf, insn_pref, c, 28, b);
	336	else
	337	build_insn(buf, insn_pref, c, a, b);
	338	}
abc597fe	339	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
c9941158 DD	340	#else
	341	I_u2s3u1(_pref)
	342	#endif
	343
e30ec452	344	/* Handle labels. */
078a55fc	345	void ISAFUNC(uasm_build_label)(struct uasm_label *lab, u32 addr, int lid)
e30ec452 TS	346	{
	347	(*lab)->addr = addr;
	348	(*lab)->lab = lid;
	349	(*lab)++;
	350	}
abc597fe	351	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));
e30ec452	352
078a55fc	353	int ISAFUNC(uasm_in_compat_space_p)(long addr)
e30ec452 TS	354	{
	355	/* Is this address in 32bit compat space? */
	356	#ifdef CONFIG_64BIT
	357	return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
	358	#else
	359	return 1;
	360	#endif
	361	}
abc597fe	362	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));
e30ec452	363
078a55fc	364	static int uasm_rel_highest(long val)
e30ec452 TS	365	{
	366	#ifdef CONFIG_64BIT
	367	return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
	368	#else
	369	return 0;
	370	#endif
	371	}
	372
078a55fc	373	static int uasm_rel_higher(long val)
e30ec452 TS	374	{
	375	#ifdef CONFIG_64BIT
	376	return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
	377	#else
	378	return 0;
	379	#endif
	380	}
	381
078a55fc	382	int ISAFUNC(uasm_rel_hi)(long val)
e30ec452 TS	383	{
	384	return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
	385	}
abc597fe	386	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));
e30ec452	387
078a55fc	388	int ISAFUNC(uasm_rel_lo)(long val)
e30ec452 TS	389	{
	390	return ((val & 0xffff) ^ 0x8000) - 0x8000;
	391	}
abc597fe	392	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));
e30ec452	393
078a55fc	394	void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
e30ec452	395	{
abc597fe SH	396	if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
abc597fe SH	397	ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
e30ec452	398	if (uasm_rel_higher(addr))
abc597fe SH	399	ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
	400	if (ISAFUNC(uasm_rel_hi(addr))) {
	401	ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
	402	ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
	403	ISAFUNC(uasm_rel_hi)(addr));
	404	ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
e30ec452	405	} else
abc597fe	406	ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
e30ec452	407	} else
abc597fe	408	ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
e30ec452	409	}
abc597fe	410	UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));
e30ec452	411
078a55fc	412	void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
e30ec452	413	{
abc597fe SH	414	ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
	415	if (ISAFUNC(uasm_rel_lo(addr))) {
	416	if (!ISAFUNC(uasm_in_compat_space_p)(addr))
	417	ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
	418	ISAFUNC(uasm_rel_lo(addr)));
e30ec452	419	else
abc597fe SH	420	ISAFUNC(uasm_i_addiu)(buf, rs, rs,
abc597fe SH	421	ISAFUNC(uasm_rel_lo(addr)));
e30ec452 TS	422	}
e30ec452 TS	423	}
abc597fe	424	UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));
e30ec452 TS	425
e30ec452 TS	426	/* Handle relocations. */
078a55fc	427	void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc *rel, u32 addr, int lid)
e30ec452 TS	428	{
	429	(*rel)->addr = addr;
	430	(*rel)->type = R_MIPS_PC16;
	431	(*rel)->lab = lid;
	432	(*rel)++;
	433	}
abc597fe	434	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));
e30ec452	435
078a55fc PG	436	static inline void __resolve_relocs(struct uasm_reloc *rel,
078a55fc PG	437	struct uasm_label *lab);
e30ec452	438
078a55fc PG	439	void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
078a55fc PG	440	struct uasm_label *lab)
e30ec452 TS	441	{
	442	struct uasm_label *l;
	443
	444	for (; rel->lab != UASM_LABEL_INVALID; rel++)
	445	for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
	446	if (rel->lab == l->lab)
	447	__resolve_relocs(rel, l);
	448	}
abc597fe	449	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));
e30ec452	450
078a55fc PG	451	void ISAFUNC(uasm_move_relocs)(struct uasm_reloc rel, u32 first, u32 *end,
078a55fc PG	452	long off)
e30ec452 TS	453	{
	454	for (; rel->lab != UASM_LABEL_INVALID; rel++)
	455	if (rel->addr >= first && rel->addr < end)
	456	rel->addr += off;
	457	}
abc597fe	458	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));
e30ec452	459
078a55fc PG	460	void ISAFUNC(uasm_move_labels)(struct uasm_label lab, u32 first, u32 *end,
078a55fc PG	461	long off)
e30ec452 TS	462	{
	463	for (; lab->lab != UASM_LABEL_INVALID; lab++)
	464	if (lab->addr >= first && lab->addr < end)
	465	lab->addr += off;
	466	}
abc597fe	467	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));
e30ec452	468
078a55fc PG	469	void ISAFUNC(uasm_copy_handler)(struct uasm_reloc rel, struct uasm_label lab,
078a55fc PG	470	u32 first, u32 end, u32 *target)
e30ec452 TS	471	{
	472	long off = (long)(target - first);
	473
	474	memcpy(target, first, (end - first) * sizeof(u32));
	475
abc597fe SH	476	ISAFUNC(uasm_move_relocs(rel, first, end, off));
abc597fe SH	477	ISAFUNC(uasm_move_labels(lab, first, end, off));
e30ec452	478	}
abc597fe	479	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));
e30ec452	480
078a55fc	481	int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc rel, u32 addr)
e30ec452 TS	482	{
	483	for (; rel->lab != UASM_LABEL_INVALID; rel++) {
	484	if (rel->addr == addr
	485	&& (rel->type == R_MIPS_PC16
	486	\|\| rel->type == R_MIPS_26))
	487	return 1;
	488	}
	489
	490	return 0;
	491	}
abc597fe	492	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));
e30ec452 TS	493
e30ec452 TS	494	/* Convenience functions for labeled branches. */
078a55fc PG	495	void ISAFUNC(uasm_il_bltz)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	496	int lid)
e30ec452 TS	497	{
e30ec452 TS	498	uasm_r_mips_pc16(r, *p, lid);
abc597fe	499	ISAFUNC(uasm_i_bltz)(p, reg, 0);
e30ec452	500	}
abc597fe	501	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));
e30ec452	502
078a55fc	503	void ISAFUNC(uasm_il_b)(u32 p, struct uasm_reloc r, int lid)
e30ec452 TS	504	{
e30ec452 TS	505	uasm_r_mips_pc16(r, *p, lid);
abc597fe	506	ISAFUNC(uasm_i_b)(p, 0);
e30ec452	507	}
abc597fe	508	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
e30ec452	509
8dee5901 PB	510	void ISAFUNC(uasm_il_beq)(u32 p, struct uasm_reloc r, unsigned int r1,
	511	unsigned int r2, int lid)
	512	{
	513	uasm_r_mips_pc16(r, *p, lid);
	514	ISAFUNC(uasm_i_beq)(p, r1, r2, 0);
	515	}
	516	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq));
	517
078a55fc PG	518	void ISAFUNC(uasm_il_beqz)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	519	int lid)
e30ec452 TS	520	{
e30ec452 TS	521	uasm_r_mips_pc16(r, *p, lid);
abc597fe	522	ISAFUNC(uasm_i_beqz)(p, reg, 0);
e30ec452	523	}
abc597fe	524	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));
e30ec452	525
078a55fc PG	526	void ISAFUNC(uasm_il_beqzl)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	527	int lid)
e30ec452 TS	528	{
e30ec452 TS	529	uasm_r_mips_pc16(r, *p, lid);
abc597fe	530	ISAFUNC(uasm_i_beqzl)(p, reg, 0);
e30ec452	531	}
abc597fe	532	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));
e30ec452	533
078a55fc PG	534	void ISAFUNC(uasm_il_bne)(u32 p, struct uasm_reloc r, unsigned int reg1,
078a55fc PG	535	unsigned int reg2, int lid)
fb2a27e7 TS	536	{
fb2a27e7 TS	537	uasm_r_mips_pc16(r, *p, lid);
abc597fe	538	ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
fb2a27e7	539	}
abc597fe	540	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));
fb2a27e7	541
078a55fc PG	542	void ISAFUNC(uasm_il_bnez)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	543	int lid)
e30ec452 TS	544	{
e30ec452 TS	545	uasm_r_mips_pc16(r, *p, lid);
abc597fe	546	ISAFUNC(uasm_i_bnez)(p, reg, 0);
e30ec452	547	}
abc597fe	548	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));
e30ec452	549
078a55fc PG	550	void ISAFUNC(uasm_il_bgezl)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	551	int lid)
e30ec452 TS	552	{
e30ec452 TS	553	uasm_r_mips_pc16(r, *p, lid);
abc597fe	554	ISAFUNC(uasm_i_bgezl)(p, reg, 0);
e30ec452	555	}
abc597fe	556	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));
e30ec452	557
078a55fc PG	558	void ISAFUNC(uasm_il_bgez)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	559	int lid)
e30ec452 TS	560	{
e30ec452 TS	561	uasm_r_mips_pc16(r, *p, lid);
abc597fe	562	ISAFUNC(uasm_i_bgez)(p, reg, 0);
e30ec452	563	}
abc597fe	564	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));
5b97c3f7	565
078a55fc PG	566	void ISAFUNC(uasm_il_bbit0)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	567	unsigned int bit, int lid)
5b97c3f7 DD	568	{
5b97c3f7 DD	569	uasm_r_mips_pc16(r, *p, lid);
abc597fe	570	ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
5b97c3f7	571	}
abc597fe	572	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));
5b97c3f7	573
078a55fc PG	574	void ISAFUNC(uasm_il_bbit1)(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc PG	575	unsigned int bit, int lid)
5b97c3f7 DD	576	{
5b97c3f7 DD	577	uasm_r_mips_pc16(r, *p, lid);
abc597fe	578	ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
5b97c3f7	579	}
abc597fe	580	UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));