[mirror_ubuntu-zesty-kernel.git] / arch / mips / mm / uasm.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * A small micro-assembler. It is intentionally kept simple, does only
 * support a subset of instructions, and does not try to hide pipeline
 * effects like branch delay slots.
 *
 * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
 * Copyright (C) 2005, 2007  Maciej W. Rozycki
 * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>

#include <asm/inst.h>
#include <asm/elf.h>
#include <asm/bugs.h>
#include <asm/uasm.h>

enum fields {
	RS = 0x001,
	RT = 0x002,
	RD = 0x004,
	RE = 0x008,
	SIMM = 0x010,
	UIMM = 0x020,
	BIMM = 0x040,
	JIMM = 0x080,
	FUNC = 0x100,
	SET = 0x200,
	SCIMM = 0x400
};

#define OP_MASK		0x3f
#define OP_SH		26
#define RS_MASK		0x1f
#define RS_SH		21
#define RT_MASK		0x1f
#define RT_SH		16
#define RD_MASK		0x1f
#define RD_SH		11
#define RE_MASK		0x1f
#define RE_SH		6
#define IMM_MASK	0xffff
#define IMM_SH		0
#define JIMM_MASK	0x3ffffff
#define JIMM_SH		0
#define FUNC_MASK	0x3f
#define FUNC_SH		0
#define SET_MASK	0x7
#define SET_SH		0
#define SCIMM_MASK	0xfffff
#define SCIMM_SH	6

enum opcode {
	insn_invalid,
	insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
	insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
	insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
	insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
	insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret,
	insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld,
	insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
	insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
	insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,
	insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
	insn_dins, insn_syscall
};

struct insn {
	enum opcode opcode;
	u32 match;
	enum fields fields;
};

/* This macro sets the non-variable bits of an instruction. */
#define M(a, b, c, d, e, f)					\
	((a) << OP_SH						\
	 | (b) << RS_SH						\
	 | (c) << RT_SH						\
	 | (d) << RD_SH						\
	 | (e) << RE_SH						\
	 | (f) << FUNC_SH)

static struct insn insn_table[] __cpuinitdata = {
	{ insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
	{ insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
	{ insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
	{ insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
	{ insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
	{ insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
	{ insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
	{ insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
	{ insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
	{ insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
	{ insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
	{ insn_cache,  M(cache_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
	{ insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
	{ insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
	{ insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
	{ insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
	{ insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
	{ insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
	{ insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
	{ insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
	{ insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
	{ insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
	{ insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
	{ insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
	{ insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
	{ insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },
	{ insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
	{ insn_ld,  M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_lld,  M(lld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_lui,  M(lui_op, 0, 0, 0, 0, 0),  RT | SIMM },
	{ insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
	{ insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
	{ insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },
	{ insn_ori,  M(ori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
	{ insn_pref,  M(pref_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_rfe,  M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0 },
	{ insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_scd,  M(scd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
	{ insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
	{ insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
	{ insn_rotr,  M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE },
	{ insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
	{ insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
	{ insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
	{ insn_tlbr,  M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0 },
	{ insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },
	{ insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
	{ insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
	{ insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
	{ insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
	{ insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
	{ insn_invalid, 0, 0 }
};

#undef M

static inline __cpuinit u32 build_rs(u32 arg)
{
	if (arg & ~RS_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RS_MASK) << RS_SH;
}

static inline __cpuinit u32 build_rt(u32 arg)
{
	if (arg & ~RT_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RT_MASK) << RT_SH;
}

static inline __cpuinit u32 build_rd(u32 arg)
{
	if (arg & ~RD_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RD_MASK) << RD_SH;
}

static inline __cpuinit u32 build_re(u32 arg)
{
	if (arg & ~RE_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RE_MASK) << RE_SH;
}

static inline __cpuinit u32 build_simm(s32 arg)
{
	if (arg > 0x7fff || arg < -0x8000)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return arg & 0xffff;
}

static inline __cpuinit u32 build_uimm(u32 arg)
{
	if (arg & ~IMM_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return arg & IMM_MASK;
}

static inline __cpuinit u32 build_bimm(s32 arg)
{
	if (arg > 0x1ffff || arg < -0x20000)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	if (arg & 0x3)
		printk(KERN_WARNING "Invalid micro-assembler branch target\n");

	return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
}

static inline __cpuinit u32 build_jimm(u32 arg)
{
	if (arg & ~((JIMM_MASK) << 2))
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return (arg >> 2) & JIMM_MASK;
}

static inline __cpuinit u32 build_scimm(u32 arg)
{
	if (arg & ~SCIMM_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & SCIMM_MASK) << SCIMM_SH;
}

static inline __cpuinit u32 build_func(u32 arg)
{
	if (arg & ~FUNC_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return arg & FUNC_MASK;
}

static inline __cpuinit u32 build_set(u32 arg)
{
	if (arg & ~SET_MASK)
		printk(KERN_WARNING "Micro-assembler field overflow\n");

	return arg & SET_MASK;
}

/*
 * The order of opcode arguments is implicitly left to right,
 * starting with RS and ending with FUNC or IMM.
 */
static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
{
	struct insn *ip = NULL;
	unsigned int i;
	va_list ap;
	u32 op;

	for (i = 0; insn_table[i].opcode != insn_invalid; i++)
		if (insn_table[i].opcode == opc) {
			ip = &insn_table[i];
			break;
		}

	if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
		panic("Unsupported Micro-assembler instruction %d", opc);

	op = ip->match;
	va_start(ap, opc);
	if (ip->fields & RS)
		op |= build_rs(va_arg(ap, u32));
	if (ip->fields & RT)
		op |= build_rt(va_arg(ap, u32));
	if (ip->fields & RD)
		op |= build_rd(va_arg(ap, u32));
	if (ip->fields & RE)
		op |= build_re(va_arg(ap, u32));
	if (ip->fields & SIMM)
		op |= build_simm(va_arg(ap, s32));
	if (ip->fields & UIMM)
		op |= build_uimm(va_arg(ap, u32));
	if (ip->fields & BIMM)
		op |= build_bimm(va_arg(ap, s32));
	if (ip->fields & JIMM)
		op |= build_jimm(va_arg(ap, u32));
	if (ip->fields & FUNC)
		op |= build_func(va_arg(ap, u32));
	if (ip->fields & SET)
		op |= build_set(va_arg(ap, u32));
	if (ip->fields & SCIMM)
		op |= build_scimm(va_arg(ap, u32));
	va_end(ap);

	**buf = op;
	(*buf)++;
}

#define I_u1u2u3(op)					\
Ip_u1u2u3(op)						\
{							\
	build_insn(buf, insn##op, a, b, c);		\
}

#define I_u2u1u3(op)					\
Ip_u2u1u3(op)						\
{							\
	build_insn(buf, insn##op, b, a, c);		\
}

#define I_u3u1u2(op)					\
Ip_u3u1u2(op)						\
{							\
	build_insn(buf, insn##op, b, c, a);		\
}

#define I_u1u2s3(op)					\
Ip_u1u2s3(op)						\
{							\
	build_insn(buf, insn##op, a, b, c);		\
}

#define I_u2s3u1(op)					\
Ip_u2s3u1(op)						\
{							\
	build_insn(buf, insn##op, c, a, b);		\
}

#define I_u2u1s3(op)					\
Ip_u2u1s3(op)						\
{							\
	build_insn(buf, insn##op, b, a, c);		\
}

#define I_u2u1msbu3(op)					\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, c+d-1, c);	\
}

#define I_u1u2(op)					\
Ip_u1u2(op)						\
{							\
	build_insn(buf, insn##op, a, b);		\
}

#define I_u1s2(op)					\
Ip_u1s2(op)						\
{							\
	build_insn(buf, insn##op, a, b);		\
}

#define I_u1(op)					\
Ip_u1(op)						\
{							\
	build_insn(buf, insn##op, a);			\
}

#define I_0(op)						\
Ip_0(op)						\
{							\
	build_insn(buf, insn##op);			\
}

I_u2u1s3(_addiu)
I_u3u1u2(_addu)
I_u2u1u3(_andi)
I_u3u1u2(_and)
I_u1u2s3(_beq)
I_u1u2s3(_beql)
I_u1s2(_bgez)
I_u1s2(_bgezl)
I_u1s2(_bltz)
I_u1s2(_bltzl)
I_u1u2s3(_bne)
I_u2s3u1(_cache)
I_u1u2u3(_dmfc0)
I_u1u2u3(_dmtc0)
I_u2u1s3(_daddiu)
I_u3u1u2(_daddu)
I_u2u1u3(_dsll)
I_u2u1u3(_dsll32)
I_u2u1u3(_dsra)
I_u2u1u3(_dsrl)
I_u2u1u3(_dsrl32)
I_u2u1u3(_drotr)
I_u2u1u3(_drotr32)
I_u3u1u2(_dsubu)
I_0(_eret)
I_u1(_j)
I_u1(_jal)
I_u1(_jr)
I_u2s3u1(_ld)
I_u2s3u1(_ll)
I_u2s3u1(_lld)
I_u1s2(_lui)
I_u2s3u1(_lw)
I_u1u2u3(_mfc0)
I_u1u2u3(_mtc0)
I_u2u1u3(_ori)
I_u3u1u2(_or)
I_u2s3u1(_pref)
I_0(_rfe)
I_u2s3u1(_sc)
I_u2s3u1(_scd)
I_u2s3u1(_sd)
I_u2u1u3(_sll)
I_u2u1u3(_sra)
I_u2u1u3(_srl)
I_u2u1u3(_rotr)
I_u3u1u2(_subu)
I_u2s3u1(_sw)
I_0(_tlbp)
I_0(_tlbr)
I_0(_tlbwi)
I_0(_tlbwr)
I_u3u1u2(_xor)
I_u2u1u3(_xori)
I_u2u1msbu3(_dins);
I_u1(_syscall);

/* Handle labels. */
void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
{
	(*lab)->addr = addr;
	(*lab)->lab = lid;
	(*lab)++;
}

int __cpuinit uasm_in_compat_space_p(long addr)
{
	/* Is this address in 32bit compat space? */
#ifdef CONFIG_64BIT
	return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
#else
	return 1;
#endif
}

static int __cpuinit uasm_rel_highest(long val)
{
#ifdef CONFIG_64BIT
	return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
#else
	return 0;
#endif
}

static int __cpuinit uasm_rel_higher(long val)
{
#ifdef CONFIG_64BIT
	return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
#else
	return 0;
#endif
}

int __cpuinit uasm_rel_hi(long val)
{
	return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
}

int __cpuinit uasm_rel_lo(long val)
{
	return ((val & 0xffff) ^ 0x8000) - 0x8000;
}

void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
{
	if (!uasm_in_compat_space_p(addr)) {
		uasm_i_lui(buf, rs, uasm_rel_highest(addr));
		if (uasm_rel_higher(addr))
			uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
		if (uasm_rel_hi(addr)) {
			uasm_i_dsll(buf, rs, rs, 16);
			uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
			uasm_i_dsll(buf, rs, rs, 16);
		} else
			uasm_i_dsll32(buf, rs, rs, 0);
	} else
		uasm_i_lui(buf, rs, uasm_rel_hi(addr));
}

void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
{
	UASM_i_LA_mostly(buf, rs, addr);
	if (uasm_rel_lo(addr)) {
		if (!uasm_in_compat_space_p(addr))
			uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
		else
			uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
	}
}

/* Handle relocations. */
void __cpuinit
uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
{
	(*rel)->addr = addr;
	(*rel)->type = R_MIPS_PC16;
	(*rel)->lab = lid;
	(*rel)++;
}

static inline void __cpuinit
__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
{
	long laddr = (long)lab->addr;
	long raddr = (long)rel->addr;

	switch (rel->type) {
	case R_MIPS_PC16:
		*rel->addr |= build_bimm(laddr - (raddr + 4));
		break;

	default:
		panic("Unsupported Micro-assembler relocation %d",
		      rel->type);
	}
}

void __cpuinit
uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
{
	struct uasm_label *l;

	for (; rel->lab != UASM_LABEL_INVALID; rel++)
		for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
			if (rel->lab == l->lab)
				__resolve_relocs(rel, l);
}

void __cpuinit
uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
{
	for (; rel->lab != UASM_LABEL_INVALID; rel++)
		if (rel->addr >= first && rel->addr < end)
			rel->addr += off;
}

void __cpuinit
uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
{
	for (; lab->lab != UASM_LABEL_INVALID; lab++)
		if (lab->addr >= first && lab->addr < end)
			lab->addr += off;
}

void __cpuinit
uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
		  u32 *end, u32 *target)
{
	long off = (long)(target - first);

	memcpy(target, first, (end - first) * sizeof(u32));

	uasm_move_relocs(rel, first, end, off);
	uasm_move_labels(lab, first, end, off);
}

int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
{
	for (; rel->lab != UASM_LABEL_INVALID; rel++) {
		if (rel->addr == addr
		    && (rel->type == R_MIPS_PC16
			|| rel->type == R_MIPS_26))
			return 1;
	}

	return 0;
}

/* Convenience functions for labeled branches. */
void __cpuinit
uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bltz(p, reg, 0);
}

void __cpuinit
uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_b(p, 0);
}

void __cpuinit
uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_beqz(p, reg, 0);
}

void __cpuinit
uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_beqzl(p, reg, 0);
}

void __cpuinit
uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
	unsigned int reg2, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bne(p, reg1, reg2, 0);
}

void __cpuinit
uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bnez(p, reg, 0);
}

void __cpuinit
uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bgezl(p, reg, 0);
}

void __cpuinit
uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bgez(p, reg, 0);
}
Commit	Line	Data
e30ec452 TS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* A small micro-assembler. It is intentionally kept simple, does only
	7	* support a subset of instructions, and does not try to hide pipeline
	8	* effects like branch delay slots.
	9	*
	10	* Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
	11	* Copyright (C) 2005, 2007 Maciej W. Rozycki
	12	* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/types.h>
	17	#include <linux/init.h>
	18
	19	#include <asm/inst.h>
	20	#include <asm/elf.h>
	21	#include <asm/bugs.h>
3482d713	22	#include <asm/uasm.h>
e30ec452 TS	23
	24	enum fields {
	25	RS = 0x001,
	26	RT = 0x002,
	27	RD = 0x004,
	28	RE = 0x008,
	29	SIMM = 0x010,
	30	UIMM = 0x020,
	31	BIMM = 0x040,
	32	JIMM = 0x080,
	33	FUNC = 0x100,
58b9e223 DD	34	SET = 0x200,
58b9e223 DD	35	SCIMM = 0x400
e30ec452 TS	36	};
	37
	38	#define OP_MASK 0x3f
	39	#define OP_SH 26
	40	#define RS_MASK 0x1f
	41	#define RS_SH 21
	42	#define RT_MASK 0x1f
	43	#define RT_SH 16
	44	#define RD_MASK 0x1f
	45	#define RD_SH 11
	46	#define RE_MASK 0x1f
	47	#define RE_SH 6
	48	#define IMM_MASK 0xffff
	49	#define IMM_SH 0
	50	#define JIMM_MASK 0x3ffffff
	51	#define JIMM_SH 0
	52	#define FUNC_MASK 0x3f
	53	#define FUNC_SH 0
	54	#define SET_MASK 0x7
	55	#define SET_SH 0
58b9e223 DD	56	#define SCIMM_MASK 0xfffff
58b9e223 DD	57	#define SCIMM_SH 6
e30ec452 TS	58
	59	enum opcode {
	60	insn_invalid,
	61	insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
	62	insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
fb2a27e7 TS	63	insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
fb2a27e7 TS	64	insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
de6d5b55 DD	65	insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret,
	66	insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld,
	67	insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
	68	insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
	69	insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,
	70	insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
58b9e223	71	insn_dins, insn_syscall
e30ec452 TS	72	};
	73
	74	struct insn {
	75	enum opcode opcode;
	76	u32 match;
	77	enum fields fields;
	78	};
	79
	80	/* This macro sets the non-variable bits of an instruction. */
	81	#define M(a, b, c, d, e, f) \
	82	((a) << OP_SH \
	83	\| (b) << RS_SH \
	84	\| (c) << RT_SH \
	85	\| (d) << RD_SH \
	86	\| (e) << RE_SH \
	87	\| (f) << FUNC_SH)
	88
234fcd14	89	static struct insn insn_table[] __cpuinitdata = {
e30ec452 TS	90	{ insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	91	{ insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS \| RT \| RD },
	92	{ insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS \| RT \| RD },
	93	{ insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS \| RT \| UIMM },
	94	{ insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS \| RT \| BIMM },
	95	{ insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS \| RT \| BIMM },
	96	{ insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS \| BIMM },
	97	{ insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS \| BIMM },
	98	{ insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS \| BIMM },
	99	{ insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS \| BIMM },
	100	{ insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS \| RT \| BIMM },
fb2a27e7	101	{ insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
e30ec452 TS	102	{ insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	103	{ insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS \| RT \| RD },
	104	{ insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT \| RD \| SET},
	105	{ insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT \| RD \| SET},
	106	{ insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT \| RD \| RE },
	107	{ insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT \| RD \| RE },
	108	{ insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT \| RD \| RE },
	109	{ insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT \| RD \| RE },
	110	{ insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT \| RD \| RE },
92078e06	111	{ insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT \| RD \| RE },
de6d5b55	112	{ insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT \| RD \| RE },
e30ec452 TS	113	{ insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS \| RT \| RD },
	114	{ insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
	115	{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
	116	{ insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
	117	{ insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
	118	{ insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	119	{ insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	120	{ insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	121	{ insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT \| SIMM },
	122	{ insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	123	{ insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT \| RD \| SET},
	124	{ insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT \| RD \| SET},
5808184f	125	{ insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS \| RT \| RD },
e30ec452	126	{ insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS \| RT \| UIMM },
fb2a27e7	127	{ insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
e30ec452 TS	128	{ insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
	129	{ insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	130	{ insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	131	{ insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	132	{ insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT \| RD \| RE },
	133	{ insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT \| RD \| RE },
	134	{ insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT \| RD \| RE },
32546f38	135	{ insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT \| RD \| RE },
e30ec452 TS	136	{ insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS \| RT \| RD },
	137	{ insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS \| RT \| SIMM },
	138	{ insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
32546f38	139	{ insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
e30ec452 TS	140	{ insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
	141	{ insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
	142	{ insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS \| RT \| RD },
	143	{ insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS \| RT \| UIMM },
92078e06	144	{ insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS \| RT \| RD \| RE },
58b9e223	145	{ insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
e30ec452 TS	146	{ insn_invalid, 0, 0 }
	147	};
	148
	149	#undef M
	150
234fcd14	151	static inline __cpuinit u32 build_rs(u32 arg)
e30ec452 TS	152	{
	153	if (arg & ~RS_MASK)
	154	printk(KERN_WARNING "Micro-assembler field overflow\n");
	155
	156	return (arg & RS_MASK) << RS_SH;
	157	}
	158
234fcd14	159	static inline __cpuinit u32 build_rt(u32 arg)
e30ec452 TS	160	{
	161	if (arg & ~RT_MASK)
	162	printk(KERN_WARNING "Micro-assembler field overflow\n");
	163
	164	return (arg & RT_MASK) << RT_SH;
	165	}
	166
234fcd14	167	static inline __cpuinit u32 build_rd(u32 arg)
e30ec452 TS	168	{
	169	if (arg & ~RD_MASK)
	170	printk(KERN_WARNING "Micro-assembler field overflow\n");
	171
	172	return (arg & RD_MASK) << RD_SH;
	173	}
	174
234fcd14	175	static inline __cpuinit u32 build_re(u32 arg)
e30ec452 TS	176	{
	177	if (arg & ~RE_MASK)
	178	printk(KERN_WARNING "Micro-assembler field overflow\n");
	179
	180	return (arg & RE_MASK) << RE_SH;
	181	}
	182
234fcd14	183	static inline __cpuinit u32 build_simm(s32 arg)
e30ec452 TS	184	{
	185	if (arg > 0x7fff \|\| arg < -0x8000)
	186	printk(KERN_WARNING "Micro-assembler field overflow\n");
	187
	188	return arg & 0xffff;
	189	}
	190
234fcd14	191	static inline __cpuinit u32 build_uimm(u32 arg)
e30ec452 TS	192	{
	193	if (arg & ~IMM_MASK)
	194	printk(KERN_WARNING "Micro-assembler field overflow\n");
	195
	196	return arg & IMM_MASK;
	197	}
	198
234fcd14	199	static inline __cpuinit u32 build_bimm(s32 arg)
e30ec452 TS	200	{
	201	if (arg > 0x1ffff \|\| arg < -0x20000)
	202	printk(KERN_WARNING "Micro-assembler field overflow\n");
	203
	204	if (arg & 0x3)
	205	printk(KERN_WARNING "Invalid micro-assembler branch target\n");
	206
	207	return ((arg < 0) ? (1 << 15) : 0) \| ((arg >> 2) & 0x7fff);
	208	}
	209
234fcd14	210	static inline __cpuinit u32 build_jimm(u32 arg)
e30ec452 TS	211	{
	212	if (arg & ~((JIMM_MASK) << 2))
	213	printk(KERN_WARNING "Micro-assembler field overflow\n");
	214
	215	return (arg >> 2) & JIMM_MASK;
	216	}
	217
58b9e223 DD	218	static inline __cpuinit u32 build_scimm(u32 arg)
	219	{
	220	if (arg & ~SCIMM_MASK)
	221	printk(KERN_WARNING "Micro-assembler field overflow\n");
	222
	223	return (arg & SCIMM_MASK) << SCIMM_SH;
	224	}
	225
234fcd14	226	static inline __cpuinit u32 build_func(u32 arg)
e30ec452 TS	227	{
	228	if (arg & ~FUNC_MASK)
	229	printk(KERN_WARNING "Micro-assembler field overflow\n");
	230
	231	return arg & FUNC_MASK;
	232	}
	233
234fcd14	234	static inline __cpuinit u32 build_set(u32 arg)
e30ec452 TS	235	{
	236	if (arg & ~SET_MASK)
	237	printk(KERN_WARNING "Micro-assembler field overflow\n");
	238
	239	return arg & SET_MASK;
	240	}
	241
	242	/*
	243	* The order of opcode arguments is implicitly left to right,
	244	* starting with RS and ending with FUNC or IMM.
	245	*/
234fcd14	246	static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
e30ec452 TS	247	{
	248	struct insn *ip = NULL;
	249	unsigned int i;
	250	va_list ap;
	251	u32 op;
	252
	253	for (i = 0; insn_table[i].opcode != insn_invalid; i++)
	254	if (insn_table[i].opcode == opc) {
	255	ip = &insn_table[i];
	256	break;
	257	}
	258
	259	if (!ip \|\| (opc == insn_daddiu && r4k_daddiu_bug()))
	260	panic("Unsupported Micro-assembler instruction %d", opc);
	261
	262	op = ip->match;
	263	va_start(ap, opc);
	264	if (ip->fields & RS)
	265	op \|= build_rs(va_arg(ap, u32));
	266	if (ip->fields & RT)
	267	op \|= build_rt(va_arg(ap, u32));
	268	if (ip->fields & RD)
	269	op \|= build_rd(va_arg(ap, u32));
	270	if (ip->fields & RE)
	271	op \|= build_re(va_arg(ap, u32));
	272	if (ip->fields & SIMM)
	273	op \|= build_simm(va_arg(ap, s32));
	274	if (ip->fields & UIMM)
	275	op \|= build_uimm(va_arg(ap, u32));
	276	if (ip->fields & BIMM)
	277	op \|= build_bimm(va_arg(ap, s32));
	278	if (ip->fields & JIMM)
	279	op \|= build_jimm(va_arg(ap, u32));
	280	if (ip->fields & FUNC)
	281	op \|= build_func(va_arg(ap, u32));
	282	if (ip->fields & SET)
	283	op \|= build_set(va_arg(ap, u32));
58b9e223 DD	284	if (ip->fields & SCIMM)
58b9e223 DD	285	op \|= build_scimm(va_arg(ap, u32));
e30ec452 TS	286	va_end(ap);
	287
	288	**buf = op;
	289	(*buf)++;
	290	}
	291
	292	#define I_u1u2u3(op) \
	293	Ip_u1u2u3(op) \
	294	{ \
	295	build_insn(buf, insn##op, a, b, c); \
	296	}
	297
	298	#define I_u2u1u3(op) \
	299	Ip_u2u1u3(op) \
	300	{ \
	301	build_insn(buf, insn##op, b, a, c); \
	302	}
	303
	304	#define I_u3u1u2(op) \
	305	Ip_u3u1u2(op) \
	306	{ \
	307	build_insn(buf, insn##op, b, c, a); \
	308	}
	309
	310	#define I_u1u2s3(op) \
	311	Ip_u1u2s3(op) \
	312	{ \
	313	build_insn(buf, insn##op, a, b, c); \
	314	}
	315
	316	#define I_u2s3u1(op) \
	317	Ip_u2s3u1(op) \
	318	{ \
	319	build_insn(buf, insn##op, c, a, b); \
	320	}
	321
	322	#define I_u2u1s3(op) \
	323	Ip_u2u1s3(op) \
	324	{ \
	325	build_insn(buf, insn##op, b, a, c); \
	326	}
	327
92078e06 DD	328	#define I_u2u1msbu3(op) \
	329	Ip_u2u1msbu3(op) \
	330	{ \
	331	build_insn(buf, insn##op, b, a, c+d-1, c); \
	332	}
	333
e30ec452 TS	334	#define I_u1u2(op) \
	335	Ip_u1u2(op) \
	336	{ \
	337	build_insn(buf, insn##op, a, b); \
	338	}
	339
	340	#define I_u1s2(op) \
	341	Ip_u1s2(op) \
	342	{ \
	343	build_insn(buf, insn##op, a, b); \
	344	}
	345
	346	#define I_u1(op) \
	347	Ip_u1(op) \
	348	{ \
	349	build_insn(buf, insn##op, a); \
	350	}
	351
	352	#define I_0(op) \
	353	Ip_0(op) \
	354	{ \
	355	build_insn(buf, insn##op); \
	356	}
	357
	358	I_u2u1s3(_addiu)
	359	I_u3u1u2(_addu)
	360	I_u2u1u3(_andi)
	361	I_u3u1u2(_and)
	362	I_u1u2s3(_beq)
	363	I_u1u2s3(_beql)
	364	I_u1s2(_bgez)
	365	I_u1s2(_bgezl)
	366	I_u1s2(_bltz)
	367	I_u1s2(_bltzl)
	368	I_u1u2s3(_bne)
fb2a27e7	369	I_u2s3u1(_cache)
e30ec452 TS	370	I_u1u2u3(_dmfc0)
	371	I_u1u2u3(_dmtc0)
	372	I_u2u1s3(_daddiu)
	373	I_u3u1u2(_daddu)
	374	I_u2u1u3(_dsll)
	375	I_u2u1u3(_dsll32)
	376	I_u2u1u3(_dsra)
	377	I_u2u1u3(_dsrl)
	378	I_u2u1u3(_dsrl32)
92078e06	379	I_u2u1u3(_drotr)
de6d5b55	380	I_u2u1u3(_drotr32)
e30ec452 TS	381	I_u3u1u2(_dsubu)
	382	I_0(_eret)
	383	I_u1(_j)
	384	I_u1(_jal)
	385	I_u1(_jr)
	386	I_u2s3u1(_ld)
	387	I_u2s3u1(_ll)
	388	I_u2s3u1(_lld)
	389	I_u1s2(_lui)
	390	I_u2s3u1(_lw)
	391	I_u1u2u3(_mfc0)
	392	I_u1u2u3(_mtc0)
	393	I_u2u1u3(_ori)
5808184f	394	I_u3u1u2(_or)
fb2a27e7	395	I_u2s3u1(_pref)
e30ec452 TS	396	I_0(_rfe)
	397	I_u2s3u1(_sc)
	398	I_u2s3u1(_scd)
	399	I_u2s3u1(_sd)
	400	I_u2u1u3(_sll)
	401	I_u2u1u3(_sra)
	402	I_u2u1u3(_srl)
32546f38	403	I_u2u1u3(_rotr)
e30ec452 TS	404	I_u3u1u2(_subu)
	405	I_u2s3u1(_sw)
	406	I_0(_tlbp)
32546f38	407	I_0(_tlbr)
e30ec452 TS	408	I_0(_tlbwi)
	409	I_0(_tlbwr)
	410	I_u3u1u2(_xor)
	411	I_u2u1u3(_xori)
92078e06	412	I_u2u1msbu3(_dins);
58b9e223	413	I_u1(_syscall);
e30ec452 TS	414
e30ec452 TS	415	/* Handle labels. */
234fcd14	416	void __cpuinit uasm_build_label(struct uasm_label *lab, u32 addr, int lid)
e30ec452 TS	417	{
	418	(*lab)->addr = addr;
	419	(*lab)->lab = lid;
	420	(*lab)++;
	421	}
	422
234fcd14	423	int __cpuinit uasm_in_compat_space_p(long addr)
e30ec452 TS	424	{
	425	/* Is this address in 32bit compat space? */
	426	#ifdef CONFIG_64BIT
	427	return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
	428	#else
	429	return 1;
	430	#endif
	431	}
	432
17f61e61	433	static int __cpuinit uasm_rel_highest(long val)
e30ec452 TS	434	{
	435	#ifdef CONFIG_64BIT
	436	return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
	437	#else
	438	return 0;
	439	#endif
	440	}
	441
17f61e61	442	static int __cpuinit uasm_rel_higher(long val)
e30ec452 TS	443	{
	444	#ifdef CONFIG_64BIT
	445	return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
	446	#else
	447	return 0;
	448	#endif
	449	}
	450
234fcd14	451	int __cpuinit uasm_rel_hi(long val)
e30ec452 TS	452	{
	453	return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
	454	}
	455
234fcd14	456	int __cpuinit uasm_rel_lo(long val)
e30ec452 TS	457	{
	458	return ((val & 0xffff) ^ 0x8000) - 0x8000;
	459	}
	460
234fcd14	461	void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
e30ec452 TS	462	{
	463	if (!uasm_in_compat_space_p(addr)) {
	464	uasm_i_lui(buf, rs, uasm_rel_highest(addr));
	465	if (uasm_rel_higher(addr))
	466	uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
	467	if (uasm_rel_hi(addr)) {
	468	uasm_i_dsll(buf, rs, rs, 16);
	469	uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
	470	uasm_i_dsll(buf, rs, rs, 16);
	471	} else
	472	uasm_i_dsll32(buf, rs, rs, 0);
	473	} else
	474	uasm_i_lui(buf, rs, uasm_rel_hi(addr));
	475	}
	476
234fcd14	477	void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
e30ec452 TS	478	{
	479	UASM_i_LA_mostly(buf, rs, addr);
	480	if (uasm_rel_lo(addr)) {
	481	if (!uasm_in_compat_space_p(addr))
	482	uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
	483	else
	484	uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
	485	}
	486	}
	487
	488	/* Handle relocations. */
234fcd14	489	void __cpuinit
e30ec452 TS	490	uasm_r_mips_pc16(struct uasm_reloc *rel, u32 addr, int lid)
	491	{
	492	(*rel)->addr = addr;
	493	(*rel)->type = R_MIPS_PC16;
	494	(*rel)->lab = lid;
	495	(*rel)++;
	496	}
	497
234fcd14	498	static inline void __cpuinit
e30ec452 TS	499	__resolve_relocs(struct uasm_reloc rel, struct uasm_label lab)
	500	{
	501	long laddr = (long)lab->addr;
	502	long raddr = (long)rel->addr;
	503
	504	switch (rel->type) {
	505	case R_MIPS_PC16:
	506	*rel->addr \|= build_bimm(laddr - (raddr + 4));
	507	break;
	508
	509	default:
	510	panic("Unsupported Micro-assembler relocation %d",
	511	rel->type);
	512	}
	513	}
	514
234fcd14	515	void __cpuinit
e30ec452 TS	516	uasm_resolve_relocs(struct uasm_reloc rel, struct uasm_label lab)
	517	{
	518	struct uasm_label *l;
	519
	520	for (; rel->lab != UASM_LABEL_INVALID; rel++)
	521	for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
	522	if (rel->lab == l->lab)
	523	__resolve_relocs(rel, l);
	524	}
	525
234fcd14	526	void __cpuinit
e30ec452 TS	527	uasm_move_relocs(struct uasm_reloc rel, u32 first, u32 *end, long off)
	528	{
	529	for (; rel->lab != UASM_LABEL_INVALID; rel++)
	530	if (rel->addr >= first && rel->addr < end)
	531	rel->addr += off;
	532	}
	533
234fcd14	534	void __cpuinit
e30ec452 TS	535	uasm_move_labels(struct uasm_label lab, u32 first, u32 *end, long off)
	536	{
	537	for (; lab->lab != UASM_LABEL_INVALID; lab++)
	538	if (lab->addr >= first && lab->addr < end)
	539	lab->addr += off;
	540	}
	541
234fcd14	542	void __cpuinit
e30ec452 TS	543	uasm_copy_handler(struct uasm_reloc rel, struct uasm_label lab, u32 *first,
	544	u32 end, u32 target)
	545	{
	546	long off = (long)(target - first);
	547
	548	memcpy(target, first, (end - first) * sizeof(u32));
	549
	550	uasm_move_relocs(rel, first, end, off);
	551	uasm_move_labels(lab, first, end, off);
	552	}
	553
234fcd14	554	int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc rel, u32 addr)
e30ec452 TS	555	{
	556	for (; rel->lab != UASM_LABEL_INVALID; rel++) {
	557	if (rel->addr == addr
	558	&& (rel->type == R_MIPS_PC16
	559	\|\| rel->type == R_MIPS_26))
	560	return 1;
	561	}
	562
	563	return 0;
	564	}
	565
	566	/* Convenience functions for labeled branches. */
234fcd14	567	void __cpuinit
e30ec452 TS	568	uasm_il_bltz(u32 p, struct uasm_reloc r, unsigned int reg, int lid)
	569	{
	570	uasm_r_mips_pc16(r, *p, lid);
	571	uasm_i_bltz(p, reg, 0);
	572	}
	573
234fcd14	574	void __cpuinit
e30ec452 TS	575	uasm_il_b(u32 p, struct uasm_reloc r, int lid)
	576	{
	577	uasm_r_mips_pc16(r, *p, lid);
	578	uasm_i_b(p, 0);
	579	}
	580
234fcd14	581	void __cpuinit
e30ec452 TS	582	uasm_il_beqz(u32 p, struct uasm_reloc r, unsigned int reg, int lid)
	583	{
	584	uasm_r_mips_pc16(r, *p, lid);
	585	uasm_i_beqz(p, reg, 0);
	586	}
	587
234fcd14	588	void __cpuinit
e30ec452 TS	589	uasm_il_beqzl(u32 p, struct uasm_reloc r, unsigned int reg, int lid)
	590	{
	591	uasm_r_mips_pc16(r, *p, lid);
	592	uasm_i_beqzl(p, reg, 0);
	593	}
	594
fb2a27e7 TS	595	void __cpuinit
	596	uasm_il_bne(u32 p, struct uasm_reloc r, unsigned int reg1,
	597	unsigned int reg2, int lid)
	598	{
	599	uasm_r_mips_pc16(r, *p, lid);
	600	uasm_i_bne(p, reg1, reg2, 0);
	601	}
	602
234fcd14	603	void __cpuinit
e30ec452 TS	604	uasm_il_bnez(u32 p, struct uasm_reloc r, unsigned int reg, int lid)
	605	{
	606	uasm_r_mips_pc16(r, *p, lid);
	607	uasm_i_bnez(p, reg, 0);
	608	}
	609
234fcd14	610	void __cpuinit
e30ec452 TS	611	uasm_il_bgezl(u32 p, struct uasm_reloc r, unsigned int reg, int lid)
	612	{
	613	uasm_r_mips_pc16(r, *p, lid);
	614	uasm_i_bgezl(p, reg, 0);
	615	}
	616
234fcd14	617	void __cpuinit
e30ec452 TS	618	uasm_il_bgez(u32 p, struct uasm_reloc r, unsigned int reg, int lid)
	619	{
	620	uasm_r_mips_pc16(r, *p, lid);
	621	uasm_i_bgez(p, reg, 0);
	622	}