[mirror_ubuntu-artful-kernel.git] / arch / mips / mm / uasm.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * A small micro-assembler. It is intentionally kept simple, does only
 * support a subset of instructions, and does not try to hide pipeline
 * effects like branch delay slots.
 *
 * Copyright (C) 2004, 2005, 2006, 2008	 Thiemo Seufer
 * Copyright (C) 2005, 2007  Maciej W. Rozycki
 * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2012, 2013  MIPS Technologies, Inc.  All rights reserved.
 */

enum fields {
	RS = 0x001,
	RT = 0x002,
	RD = 0x004,
	RE = 0x008,
	SIMM = 0x010,
	UIMM = 0x020,
	BIMM = 0x040,
	JIMM = 0x080,
	FUNC = 0x100,
	SET = 0x200,
	SCIMM = 0x400,
	SIMM9 = 0x800,
};

#define OP_MASK		0x3f
#define OP_SH		26
#define RD_MASK		0x1f
#define RD_SH		11
#define RE_MASK		0x1f
#define RE_SH		6
#define IMM_MASK	0xffff
#define IMM_SH		0
#define JIMM_MASK	0x3ffffff
#define JIMM_SH		0
#define FUNC_MASK	0x3f
#define FUNC_SH		0
#define SET_MASK	0x7
#define SET_SH		0
#define SIMM9_SH	7
#define SIMM9_MASK	0x1ff

enum opcode {
	insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
	insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez,
	insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1,
	insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu,
	insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu, insn_dmfc0,
	insn_dmtc0, insn_dmultu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd,
	insn_dsll, insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav,
	insn_dsrl, insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext,
	insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu,
	insn_ld, insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu,
	insn_ll, insn_lld, insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0,
	insn_mfhc0, insn_mfhi, insn_mflo, insn_movn, insn_movz, insn_mtc0,
	insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_nor,
	insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb,
	insn_sc, insn_scd, insn_sd, insn_sh, insn_sll, insn_sllv,
	insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srl,
	insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp,
	insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor,
	insn_xori, insn_yield,
	insn_invalid /* insn_invalid must be last */
};

struct insn {
	u32 match;
	enum fields fields;
};

static inline u32 build_rs(u32 arg)
{
	WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RS_MASK) << RS_SH;
}

static inline u32 build_rt(u32 arg)
{
	WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RT_MASK) << RT_SH;
}

static inline u32 build_rd(u32 arg)
{
	WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RD_MASK) << RD_SH;
}

static inline u32 build_re(u32 arg)
{
	WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & RE_MASK) << RE_SH;
}

static inline u32 build_simm(s32 arg)
{
	WARN(arg > 0x7fff || arg < -0x8000,
	     KERN_WARNING "Micro-assembler field overflow\n");

	return arg & 0xffff;
}

static inline u32 build_uimm(u32 arg)
{
	WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & IMM_MASK;
}

static inline u32 build_scimm(u32 arg)
{
	WARN(arg & ~SCIMM_MASK,
	     KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & SCIMM_MASK) << SCIMM_SH;
}

static inline u32 build_scimm9(s32 arg)
{
	WARN((arg > 0xff || arg < -0x100),
	       KERN_WARNING "Micro-assembler field overflow\n");

	return (arg & SIMM9_MASK) << SIMM9_SH;
}

static inline u32 build_func(u32 arg)
{
	WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & FUNC_MASK;
}

static inline u32 build_set(u32 arg)
{
	WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");

	return arg & SET_MASK;
}

static void build_insn(u32 **buf, enum opcode opc, ...);

#define I_u1u2u3(op)					\
Ip_u1u2u3(op)						\
{							\
	build_insn(buf, insn##op, a, b, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_s3s1s2(op)					\
Ip_s3s1s2(op)						\
{							\
	build_insn(buf, insn##op, b, c, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1u3(op)					\
Ip_u2u1u3(op)						\
{							\
	build_insn(buf, insn##op, b, a, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u3u2u1(op)					\
Ip_u3u2u1(op)						\
{							\
	build_insn(buf, insn##op, c, b, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u3u1u2(op)					\
Ip_u3u1u2(op)						\
{							\
	build_insn(buf, insn##op, b, c, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1u2s3(op)					\
Ip_u1u2s3(op)						\
{							\
	build_insn(buf, insn##op, a, b, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2s3u1(op)					\
Ip_u2s3u1(op)						\
{							\
	build_insn(buf, insn##op, c, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1s3(op)					\
Ip_u2u1s3(op)						\
{							\
	build_insn(buf, insn##op, b, a, c);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msbu3(op)					\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, c+d-1, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msb32u3(op)				\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, c+d-33, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msb32msb3(op)				\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, c+d-33, c-32);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1msbdu3(op)				\
Ip_u2u1msbu3(op)					\
{							\
	build_insn(buf, insn##op, b, a, d-1, c);	\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1u2(op)					\
Ip_u1u2(op)						\
{							\
	build_insn(buf, insn##op, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u2u1(op)					\
Ip_u1u2(op)						\
{							\
	build_insn(buf, insn##op, b, a);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1s2(op)					\
Ip_u1s2(op)						\
{							\
	build_insn(buf, insn##op, a, b);		\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_u1(op)					\
Ip_u1(op)						\
{							\
	build_insn(buf, insn##op, a);			\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

#define I_0(op)						\
Ip_0(op)						\
{							\
	build_insn(buf, insn##op);			\
}							\
UASM_EXPORT_SYMBOL(uasm_i##op);

I_u2u1s3(_addiu)
I_u3u1u2(_addu)
I_u2u1u3(_andi)
I_u3u1u2(_and)
I_u1u2s3(_beq)
I_u1u2s3(_beql)
I_u1s2(_bgez)
I_u1s2(_bgezl)
I_u1s2(_bgtz)
I_u1s2(_blez)
I_u1s2(_bltz)
I_u1s2(_bltzl)
I_u1u2s3(_bne)
I_u1(_break)
I_u2s3u1(_cache)
I_u1u2(_cfc1)
I_u2u1(_cfcmsa)
I_u1u2(_ctc1)
I_u2u1(_ctcmsa)
I_u1u2(_ddivu)
I_u1u2u3(_dmfc0)
I_u1u2u3(_dmtc0)
I_u1u2(_dmultu)
I_u2u1s3(_daddiu)
I_u3u1u2(_daddu)
I_u1(_di);
I_u1u2(_divu)
I_u2u1(_dsbh);
I_u2u1(_dshd);
I_u2u1u3(_dsll)
I_u2u1u3(_dsll32)
I_u3u2u1(_dsllv)
I_u2u1u3(_dsra)
I_u2u1u3(_dsra32)
I_u3u2u1(_dsrav)
I_u2u1u3(_dsrl)
I_u2u1u3(_dsrl32)
I_u3u2u1(_dsrlv)
I_u2u1u3(_drotr)
I_u2u1u3(_drotr32)
I_u3u1u2(_dsubu)
I_0(_eret)
I_u2u1msbdu3(_ext)
I_u2u1msbu3(_ins)
I_u1(_j)
I_u1(_jal)
I_u2u1(_jalr)
I_u1(_jr)
I_u2s3u1(_lb)
I_u2s3u1(_lbu)
I_u2s3u1(_ld)
I_u2s3u1(_lh)
I_u2s3u1(_lhu)
I_u2s3u1(_ll)
I_u2s3u1(_lld)
I_u1s2(_lui)
I_u2s3u1(_lw)
I_u2s3u1(_lwu)
I_u1u2u3(_mfc0)
I_u1u2u3(_mfhc0)
I_u3u1u2(_movn)
I_u3u1u2(_movz)
I_u1(_mfhi)
I_u1(_mflo)
I_u1u2u3(_mtc0)
I_u1u2u3(_mthc0)
I_u1(_mthi)
I_u1(_mtlo)
I_u3u1u2(_mul)
I_u1u2(_multu)
I_u3u1u2(_nor)
I_u3u1u2(_or)
I_u2u1u3(_ori)
I_0(_rfe)
I_u2s3u1(_sb)
I_u2s3u1(_sc)
I_u2s3u1(_scd)
I_u2s3u1(_sd)
I_u2s3u1(_sh)
I_u2u1u3(_sll)
I_u3u2u1(_sllv)
I_s3s1s2(_slt)
I_u2u1s3(_slti)
I_u2u1s3(_sltiu)
I_u3u1u2(_sltu)
I_u2u1u3(_sra)
I_u2u1u3(_srl)
I_u3u2u1(_srlv)
I_u2u1u3(_rotr)
I_u3u1u2(_subu)
I_u2s3u1(_sw)
I_u1(_sync)
I_0(_tlbp)
I_0(_tlbr)
I_0(_tlbwi)
I_0(_tlbwr)
I_u1(_wait);
I_u2u1(_wsbh)
I_u3u1u2(_xor)
I_u2u1u3(_xori)
I_u2u1(_yield)
I_u2u1msbu3(_dins);
I_u2u1msb32u3(_dinsm);
I_u2u1msb32msb3(_dinsu);
I_u1(_syscall);
I_u1u2s3(_bbit0);
I_u1u2s3(_bbit1);
I_u3u1u2(_lwx)
I_u3u1u2(_ldx)
I_u1u2(_ldpte)
I_u2u1u3(_lddir)

#ifdef CONFIG_CPU_CAVIUM_OCTEON
#include <asm/octeon/octeon.h>
void uasm_i_pref(u32 **buf, unsigned int a, signed int b,
			    unsigned int c)
{
	if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5)
		/*
		 * As per erratum Core-14449, replace prefetches 0-4,
		 * 6-24 with 'pref 28'.
		 */
		build_insn(buf, insn_pref, c, 28, b);
	else
		build_insn(buf, insn_pref, c, a, b);
}
UASM_EXPORT_SYMBOL(uasm_i_pref);
#else
I_u2s3u1(_pref)
#endif

/* Handle labels. */
void uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
{
	(*lab)->addr = addr;
	(*lab)->lab = lid;
	(*lab)++;
}
UASM_EXPORT_SYMBOL(uasm_build_label);

int uasm_in_compat_space_p(long addr)
{
	/* Is this address in 32bit compat space? */
	return addr == (int)addr;
}
UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);

static int uasm_rel_highest(long val)
{
#ifdef CONFIG_64BIT
	return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
#else
	return 0;
#endif
}

static int uasm_rel_higher(long val)
{
#ifdef CONFIG_64BIT
	return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
#else
	return 0;
#endif
}

int uasm_rel_hi(long val)
{
	return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
}
UASM_EXPORT_SYMBOL(uasm_rel_hi);

int uasm_rel_lo(long val)
{
	return ((val & 0xffff) ^ 0x8000) - 0x8000;
}
UASM_EXPORT_SYMBOL(uasm_rel_lo);

void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
{
	if (!uasm_in_compat_space_p(addr)) {
		uasm_i_lui(buf, rs, uasm_rel_highest(addr));
		if (uasm_rel_higher(addr))
			uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
		if (uasm_rel_hi(addr)) {
			uasm_i_dsll(buf, rs, rs, 16);
			uasm_i_daddiu(buf, rs, rs,
					uasm_rel_hi(addr));
			uasm_i_dsll(buf, rs, rs, 16);
		} else
			uasm_i_dsll32(buf, rs, rs, 0);
	} else
		uasm_i_lui(buf, rs, uasm_rel_hi(addr));
}
UASM_EXPORT_SYMBOL(UASM_i_LA_mostly);

void UASM_i_LA(u32 **buf, unsigned int rs, long addr)
{
	UASM_i_LA_mostly(buf, rs, addr);
	if (uasm_rel_lo(addr)) {
		if (!uasm_in_compat_space_p(addr))
			uasm_i_daddiu(buf, rs, rs,
					uasm_rel_lo(addr));
		else
			uasm_i_addiu(buf, rs, rs,
					uasm_rel_lo(addr));
	}
}
UASM_EXPORT_SYMBOL(UASM_i_LA);

/* Handle relocations. */
void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
{
	(*rel)->addr = addr;
	(*rel)->type = R_MIPS_PC16;
	(*rel)->lab = lid;
	(*rel)++;
}
UASM_EXPORT_SYMBOL(uasm_r_mips_pc16);

static inline void __resolve_relocs(struct uasm_reloc *rel,
				    struct uasm_label *lab);

void uasm_resolve_relocs(struct uasm_reloc *rel,
				  struct uasm_label *lab)
{
	struct uasm_label *l;

	for (; rel->lab != UASM_LABEL_INVALID; rel++)
		for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
			if (rel->lab == l->lab)
				__resolve_relocs(rel, l);
}
UASM_EXPORT_SYMBOL(uasm_resolve_relocs);

void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end,
			       long off)
{
	for (; rel->lab != UASM_LABEL_INVALID; rel++)
		if (rel->addr >= first && rel->addr < end)
			rel->addr += off;
}
UASM_EXPORT_SYMBOL(uasm_move_relocs);

void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end,
			       long off)
{
	for (; lab->lab != UASM_LABEL_INVALID; lab++)
		if (lab->addr >= first && lab->addr < end)
			lab->addr += off;
}
UASM_EXPORT_SYMBOL(uasm_move_labels);

void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
				u32 *first, u32 *end, u32 *target)
{
	long off = (long)(target - first);

	memcpy(target, first, (end - first) * sizeof(u32));

	uasm_move_relocs(rel, first, end, off);
	uasm_move_labels(lab, first, end, off);
}
UASM_EXPORT_SYMBOL(uasm_copy_handler);

int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
{
	for (; rel->lab != UASM_LABEL_INVALID; rel++) {
		if (rel->addr == addr
		    && (rel->type == R_MIPS_PC16
			|| rel->type == R_MIPS_26))
			return 1;
	}

	return 0;
}
UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay);

/* Convenience functions for labeled branches. */
void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bltz(p, reg, 0);
}
UASM_EXPORT_SYMBOL(uasm_il_bltz);

void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_b(p, 0);
}
UASM_EXPORT_SYMBOL(uasm_il_b);

void uasm_il_beq(u32 **p, struct uasm_reloc **r, unsigned int r1,
			  unsigned int r2, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_beq(p, r1, r2, 0);
}
UASM_EXPORT_SYMBOL(uasm_il_beq);

void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_beqz(p, reg, 0);
}
UASM_EXPORT_SYMBOL(uasm_il_beqz);

void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_beqzl(p, reg, 0);
}
UASM_EXPORT_SYMBOL(uasm_il_beqzl);

void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
			  unsigned int reg2, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bne(p, reg1, reg2, 0);
}
UASM_EXPORT_SYMBOL(uasm_il_bne);

void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bnez(p, reg, 0);
}
UASM_EXPORT_SYMBOL(uasm_il_bnez);

void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bgezl(p, reg, 0);
}
UASM_EXPORT_SYMBOL(uasm_il_bgezl);

void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg,
			   int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bgez(p, reg, 0);
}
UASM_EXPORT_SYMBOL(uasm_il_bgez);

void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    unsigned int bit, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bbit0(p, reg, bit, 0);
}
UASM_EXPORT_SYMBOL(uasm_il_bbit0);

void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
			    unsigned int bit, int lid)
{
	uasm_r_mips_pc16(r, *p, lid);
	uasm_i_bbit1(p, reg, bit, 0);
}
UASM_EXPORT_SYMBOL(uasm_il_bbit1);
Commit	Line	Data
e30ec452 TS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* A small micro-assembler. It is intentionally kept simple, does only
	7	* support a subset of instructions, and does not try to hide pipeline
	8	* effects like branch delay slots.
	9	*
70342287	10	* Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
e30ec452 TS	11	* Copyright (C) 2005, 2007 Maciej W. Rozycki
e30ec452 TS	12	* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
abc597fe	13	* Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
e30ec452 TS	14	*/
e30ec452 TS	15
e30ec452 TS	16	enum fields {
	17	RS = 0x001,
	18	RT = 0x002,
	19	RD = 0x004,
	20	RE = 0x008,
	21	SIMM = 0x010,
	22	UIMM = 0x020,
	23	BIMM = 0x040,
	24	JIMM = 0x080,
	25	FUNC = 0x100,
58b9e223	26	SET = 0x200,
51eec48e LY	27	SCIMM = 0x400,
51eec48e LY	28	SIMM9 = 0x800,
e30ec452 TS	29	};
	30
	31	#define OP_MASK 0x3f
	32	#define OP_SH 26
e30ec452 TS	33	#define RD_MASK 0x1f
	34	#define RD_SH 11
	35	#define RE_MASK 0x1f
	36	#define RE_SH 6
	37	#define IMM_MASK 0xffff
	38	#define IMM_SH 0
	39	#define JIMM_MASK 0x3ffffff
	40	#define JIMM_SH 0
	41	#define FUNC_MASK 0x3f
	42	#define FUNC_SH 0
	43	#define SET_MASK 0x7
	44	#define SET_SH 0
51eec48e LY	45	#define SIMM9_SH 7
51eec48e LY	46	#define SIMM9_MASK 0x1ff
e30ec452 TS	47
e30ec452 TS	48	enum opcode {
71a1c776	49	insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
dc190129 DD	50	insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez,
	51	insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1,
	52	insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu,
	53	insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu, insn_dmfc0,
	54	insn_dmtc0, insn_dmultu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd,
	55	insn_dsll, insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav,
	56	insn_dsrl, insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext,
	57	insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu,
	58	insn_ld, insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu,
	59	insn_ll, insn_lld, insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0,
	60	insn_mfhc0, insn_mfhi, insn_mflo, insn_movn, insn_movz, insn_mtc0,
	61	insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_nor,
	62	insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb,
	63	insn_sc, insn_scd, insn_sd, insn_sh, insn_sll, insn_sllv,
	64	insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srl,
9f730a60 JH	65	insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp,
9f730a60 JH	66	insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor,
dc190129	67	insn_xori, insn_yield,
ce807d5f	68	insn_invalid /* insn_invalid must be last */
e30ec452 TS	69	};
	70
	71	struct insn {
e30ec452 TS	72	u32 match;
	73	enum fields fields;
	74	};
	75
078a55fc	76	static inline u32 build_rs(u32 arg)
e30ec452	77	{
8d662c8d	78	WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	79
	80	return (arg & RS_MASK) << RS_SH;
	81	}
	82
078a55fc	83	static inline u32 build_rt(u32 arg)
e30ec452	84	{
8d662c8d	85	WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	86
	87	return (arg & RT_MASK) << RT_SH;
	88	}
	89
078a55fc	90	static inline u32 build_rd(u32 arg)
e30ec452	91	{
8d662c8d	92	WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	93
	94	return (arg & RD_MASK) << RD_SH;
	95	}
	96
078a55fc	97	static inline u32 build_re(u32 arg)
e30ec452	98	{
8d662c8d	99	WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	100
	101	return (arg & RE_MASK) << RE_SH;
	102	}
	103
078a55fc	104	static inline u32 build_simm(s32 arg)
e30ec452	105	{
8d662c8d DD	106	WARN(arg > 0x7fff \|\| arg < -0x8000,
8d662c8d DD	107	KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	108
	109	return arg & 0xffff;
	110	}
	111
078a55fc	112	static inline u32 build_uimm(u32 arg)
e30ec452	113	{
8d662c8d	114	WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	115
	116	return arg & IMM_MASK;
	117	}
	118
078a55fc	119	static inline u32 build_scimm(u32 arg)
58b9e223	120	{
8d662c8d DD	121	WARN(arg & ~SCIMM_MASK,
8d662c8d DD	122	KERN_WARNING "Micro-assembler field overflow\n");
58b9e223 DD	123
	124	return (arg & SCIMM_MASK) << SCIMM_SH;
	125	}
	126
51eec48e LY	127	static inline u32 build_scimm9(s32 arg)
	128	{
	129	WARN((arg > 0xff \|\| arg < -0x100),
	130	KERN_WARNING "Micro-assembler field overflow\n");
	131
	132	return (arg & SIMM9_MASK) << SIMM9_SH;
	133	}
	134
078a55fc	135	static inline u32 build_func(u32 arg)
e30ec452	136	{
8d662c8d	137	WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	138
	139	return arg & FUNC_MASK;
	140	}
	141
078a55fc	142	static inline u32 build_set(u32 arg)
e30ec452	143	{
8d662c8d	144	WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
e30ec452 TS	145
	146	return arg & SET_MASK;
	147	}
	148
078a55fc	149	static void build_insn(u32 **buf, enum opcode opc, ...);
e30ec452 TS	150
	151	#define I_u1u2u3(op) \
	152	Ip_u1u2u3(op) \
	153	{ \
	154	build_insn(buf, insn##op, a, b, c); \
22b0763a DD	155	} \
22b0763a DD	156	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452	157
9d987369 MC	158	#define I_s3s1s2(op) \
	159	Ip_s3s1s2(op) \
	160	{ \
	161	build_insn(buf, insn##op, b, c, a); \
	162	} \
	163	UASM_EXPORT_SYMBOL(uasm_i##op);
	164
e30ec452 TS	165	#define I_u2u1u3(op) \
	166	Ip_u2u1u3(op) \
	167	{ \
	168	build_insn(buf, insn##op, b, a, c); \
22b0763a DD	169	} \
22b0763a DD	170	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452	171
beef8e02 MC	172	#define I_u3u2u1(op) \
	173	Ip_u3u2u1(op) \
	174	{ \
	175	build_insn(buf, insn##op, c, b, a); \
	176	} \
	177	UASM_EXPORT_SYMBOL(uasm_i##op);
	178
e30ec452 TS	179	#define I_u3u1u2(op) \
	180	Ip_u3u1u2(op) \
	181	{ \
	182	build_insn(buf, insn##op, b, c, a); \
22b0763a DD	183	} \
22b0763a DD	184	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	185
	186	#define I_u1u2s3(op) \
	187	Ip_u1u2s3(op) \
	188	{ \
	189	build_insn(buf, insn##op, a, b, c); \
22b0763a DD	190	} \
22b0763a DD	191	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	192
	193	#define I_u2s3u1(op) \
	194	Ip_u2s3u1(op) \
	195	{ \
	196	build_insn(buf, insn##op, c, a, b); \
22b0763a DD	197	} \
22b0763a DD	198	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	199
	200	#define I_u2u1s3(op) \
	201	Ip_u2u1s3(op) \
	202	{ \
	203	build_insn(buf, insn##op, b, a, c); \
22b0763a DD	204	} \
22b0763a DD	205	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452	206
92078e06 DD	207	#define I_u2u1msbu3(op) \
	208	Ip_u2u1msbu3(op) \
	209	{ \
	210	build_insn(buf, insn##op, b, a, c+d-1, c); \
22b0763a DD	211	} \
22b0763a DD	212	UASM_EXPORT_SYMBOL(uasm_i##op);
92078e06	213
c42aef09 DD	214	#define I_u2u1msb32u3(op) \
	215	Ip_u2u1msbu3(op) \
	216	{ \
	217	build_insn(buf, insn##op, b, a, c+d-33, c); \
	218	} \
	219	UASM_EXPORT_SYMBOL(uasm_i##op);
	220
dc190129 DD	221	#define I_u2u1msb32msb3(op) \
	222	Ip_u2u1msbu3(op) \
	223	{ \
	224	build_insn(buf, insn##op, b, a, c+d-33, c-32); \
	225	} \
	226	UASM_EXPORT_SYMBOL(uasm_i##op);
	227
70342287	228	#define I_u2u1msbdu3(op) \
e6de1a09 SH	229	Ip_u2u1msbu3(op) \
	230	{ \
	231	build_insn(buf, insn##op, b, a, d-1, c); \
	232	} \
	233	UASM_EXPORT_SYMBOL(uasm_i##op);
	234
e30ec452 TS	235	#define I_u1u2(op) \
	236	Ip_u1u2(op) \
	237	{ \
	238	build_insn(buf, insn##op, a, b); \
22b0763a DD	239	} \
22b0763a DD	240	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452	241
d674dd14 PB	242	#define I_u2u1(op) \
	243	Ip_u1u2(op) \
	244	{ \
	245	build_insn(buf, insn##op, b, a); \
	246	} \
	247	UASM_EXPORT_SYMBOL(uasm_i##op);
	248
e30ec452 TS	249	#define I_u1s2(op) \
	250	Ip_u1s2(op) \
	251	{ \
	252	build_insn(buf, insn##op, a, b); \
22b0763a DD	253	} \
22b0763a DD	254	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	255
	256	#define I_u1(op) \
	257	Ip_u1(op) \
	258	{ \
	259	build_insn(buf, insn##op, a); \
22b0763a DD	260	} \
22b0763a DD	261	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	262
	263	#define I_0(op) \
	264	Ip_0(op) \
	265	{ \
	266	build_insn(buf, insn##op); \
22b0763a DD	267	} \
22b0763a DD	268	UASM_EXPORT_SYMBOL(uasm_i##op);
e30ec452 TS	269
	270	I_u2u1s3(_addiu)
	271	I_u3u1u2(_addu)
	272	I_u2u1u3(_andi)
	273	I_u3u1u2(_and)
	274	I_u1u2s3(_beq)
	275	I_u1u2s3(_beql)
	276	I_u1s2(_bgez)
	277	I_u1s2(_bgezl)
dc190129 DD	278	I_u1s2(_bgtz)
dc190129 DD	279	I_u1s2(_blez)
e30ec452 TS	280	I_u1s2(_bltz)
	281	I_u1s2(_bltzl)
	282	I_u1u2s3(_bne)
dc190129	283	I_u1(_break)
fb2a27e7	284	I_u2s3u1(_cache)
c29732a1	285	I_u1u2(_cfc1)
59e3559f	286	I_u2u1(_cfcmsa)
c29732a1	287	I_u1u2(_ctc1)
59e3559f	288	I_u2u1(_ctcmsa)
dc190129	289	I_u1u2(_ddivu)
e30ec452 TS	290	I_u1u2u3(_dmfc0)
e30ec452 TS	291	I_u1u2u3(_dmtc0)
dc190129	292	I_u1u2(_dmultu)
e30ec452 TS	293	I_u2u1s3(_daddiu)
e30ec452 TS	294	I_u3u1u2(_daddu)
61c64cf9	295	I_u1(_di);
4c12a854	296	I_u1u2(_divu)
dc190129 DD	297	I_u2u1(_dsbh);
dc190129 DD	298	I_u2u1(_dshd);
e30ec452 TS	299	I_u2u1u3(_dsll)
e30ec452 TS	300	I_u2u1u3(_dsll32)
dc190129	301	I_u3u2u1(_dsllv)
e30ec452	302	I_u2u1u3(_dsra)
dc190129 DD	303	I_u2u1u3(_dsra32)
dc190129 DD	304	I_u3u2u1(_dsrav)
e30ec452 TS	305	I_u2u1u3(_dsrl)
e30ec452 TS	306	I_u2u1u3(_dsrl32)
dc190129	307	I_u3u2u1(_dsrlv)
92078e06	308	I_u2u1u3(_drotr)
de6d5b55	309	I_u2u1u3(_drotr32)
e30ec452 TS	310	I_u3u1u2(_dsubu)
e30ec452 TS	311	I_0(_eret)
e6de1a09 SH	312	I_u2u1msbdu3(_ext)
e6de1a09 SH	313	I_u2u1msbu3(_ins)
e30ec452 TS	314	I_u1(_j)
e30ec452 TS	315	I_u1(_jal)
49e9529b	316	I_u2u1(_jalr)
e30ec452	317	I_u1(_jr)
82488818	318	I_u2s3u1(_lb)
dc190129	319	I_u2s3u1(_lbu)
e30ec452	320	I_u2s3u1(_ld)
d6b3314b	321	I_u2s3u1(_lh)
bfbfa9d6	322	I_u2s3u1(_lhu)
e30ec452 TS	323	I_u2s3u1(_ll)
	324	I_u2s3u1(_lld)
	325	I_u1s2(_lui)
	326	I_u2s3u1(_lw)
dc190129	327	I_u2s3u1(_lwu)
e30ec452	328	I_u1u2u3(_mfc0)
e2965cd0	329	I_u1u2u3(_mfhc0)
dc190129 DD	330	I_u3u1u2(_movn)
dc190129 DD	331	I_u3u1u2(_movz)
f3ec7a23	332	I_u1(_mfhi)
16d21a81	333	I_u1(_mflo)
e30ec452	334	I_u1u2u3(_mtc0)
e2965cd0	335	I_u1u2u3(_mthc0)
9f730a60 JH	336	I_u1(_mthi)
9f730a60 JH	337	I_u1(_mtlo)
a8e897ad	338	I_u3u1u2(_mul)
dc190129 DD	339	I_u1u2(_multu)
dc190129 DD	340	I_u3u1u2(_nor)
5808184f	341	I_u3u1u2(_or)
dc190129	342	I_u2u1u3(_ori)
e30ec452	343	I_0(_rfe)
dc190129	344	I_u2s3u1(_sb)
e30ec452 TS	345	I_u2s3u1(_sc)
	346	I_u2s3u1(_scd)
	347	I_u2s3u1(_sd)
dc190129	348	I_u2s3u1(_sh)
e30ec452	349	I_u2u1u3(_sll)
bef581ba	350	I_u3u2u1(_sllv)
7682f9e8	351	I_s3s1s2(_slt)
dc190129	352	I_u2u1s3(_slti)
390363ed	353	I_u2u1s3(_sltiu)
e8ef868b	354	I_u3u1u2(_sltu)
e30ec452 TS	355	I_u2u1u3(_sra)
e30ec452 TS	356	I_u2u1u3(_srl)
f31318fd	357	I_u3u2u1(_srlv)
32546f38	358	I_u2u1u3(_rotr)
e30ec452 TS	359	I_u3u1u2(_subu)
e30ec452 TS	360	I_u2s3u1(_sw)
729ff561	361	I_u1(_sync)
e30ec452	362	I_0(_tlbp)
32546f38	363	I_0(_tlbr)
e30ec452 TS	364	I_0(_tlbwi)
e30ec452 TS	365	I_0(_tlbwr)
53ed1389	366	I_u1(_wait);
ab9e4fa0	367	I_u2u1(_wsbh)
e30ec452 TS	368	I_u3u1u2(_xor)
e30ec452 TS	369	I_u2u1u3(_xori)
d674dd14	370	I_u2u1(_yield)
92078e06	371	I_u2u1msbu3(_dins);
c42aef09	372	I_u2u1msb32u3(_dinsm);
dc190129	373	I_u2u1msb32msb3(_dinsu);
58b9e223	374	I_u1(_syscall);
5b97c3f7 DD	375	I_u1u2s3(_bbit0);
5b97c3f7 DD	376	I_u1u2s3(_bbit1);
bb3d68c3 DD	377	I_u3u1u2(_lwx)
bb3d68c3 DD	378	I_u3u1u2(_ldx)
380cd582 HC	379	I_u1u2(_ldpte)
380cd582 HC	380	I_u2u1u3(_lddir)
e30ec452	381
c9941158 DD	382	#ifdef CONFIG_CPU_CAVIUM_OCTEON
c9941158 DD	383	#include <asm/octeon/octeon.h>
33679a50	384	void uasm_i_pref(u32 **buf, unsigned int a, signed int b,
c9941158 DD	385	unsigned int c)
c9941158 DD	386	{
e3d0ead5	387	if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5)
c9941158 DD	388	/*
	389	* As per erratum Core-14449, replace prefetches 0-4,
	390	* 6-24 with 'pref 28'.
	391	*/
	392	build_insn(buf, insn_pref, c, 28, b);
	393	else
	394	build_insn(buf, insn_pref, c, a, b);
	395	}
33679a50	396	UASM_EXPORT_SYMBOL(uasm_i_pref);
c9941158 DD	397	#else
	398	I_u2s3u1(_pref)
	399	#endif
	400
e30ec452	401	/* Handle labels. */
33679a50	402	void uasm_build_label(struct uasm_label *lab, u32 addr, int lid)
e30ec452 TS	403	{
	404	(*lab)->addr = addr;
	405	(*lab)->lab = lid;
	406	(*lab)++;
	407	}
33679a50	408	UASM_EXPORT_SYMBOL(uasm_build_label);
e30ec452	409
33679a50	410	int uasm_in_compat_space_p(long addr)
e30ec452 TS	411	{
e30ec452 TS	412	/* Is this address in 32bit compat space? */
f7d9afea	413	return addr == (int)addr;
e30ec452	414	}
33679a50	415	UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
e30ec452	416
078a55fc	417	static int uasm_rel_highest(long val)
e30ec452 TS	418	{
	419	#ifdef CONFIG_64BIT
	420	return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
	421	#else
	422	return 0;
	423	#endif
	424	}
	425
078a55fc	426	static int uasm_rel_higher(long val)
e30ec452 TS	427	{
	428	#ifdef CONFIG_64BIT
	429	return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
	430	#else
	431	return 0;
	432	#endif
	433	}
	434
33679a50	435	int uasm_rel_hi(long val)
e30ec452 TS	436	{
	437	return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
	438	}
33679a50	439	UASM_EXPORT_SYMBOL(uasm_rel_hi);
e30ec452	440
33679a50	441	int uasm_rel_lo(long val)
e30ec452 TS	442	{
	443	return ((val & 0xffff) ^ 0x8000) - 0x8000;
	444	}
33679a50	445	UASM_EXPORT_SYMBOL(uasm_rel_lo);
e30ec452	446
33679a50	447	void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
e30ec452	448	{
33679a50 PB	449	if (!uasm_in_compat_space_p(addr)) {
33679a50 PB	450	uasm_i_lui(buf, rs, uasm_rel_highest(addr));
e30ec452	451	if (uasm_rel_higher(addr))
33679a50 PB	452	uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
	453	if (uasm_rel_hi(addr)) {
	454	uasm_i_dsll(buf, rs, rs, 16);
	455	uasm_i_daddiu(buf, rs, rs,
	456	uasm_rel_hi(addr));
	457	uasm_i_dsll(buf, rs, rs, 16);
e30ec452	458	} else
33679a50	459	uasm_i_dsll32(buf, rs, rs, 0);
e30ec452	460	} else
33679a50	461	uasm_i_lui(buf, rs, uasm_rel_hi(addr));
e30ec452	462	}
33679a50	463	UASM_EXPORT_SYMBOL(UASM_i_LA_mostly);
e30ec452	464
33679a50	465	void UASM_i_LA(u32 **buf, unsigned int rs, long addr)
e30ec452	466	{
33679a50 PB	467	UASM_i_LA_mostly(buf, rs, addr);
	468	if (uasm_rel_lo(addr)) {
	469	if (!uasm_in_compat_space_p(addr))
	470	uasm_i_daddiu(buf, rs, rs,
	471	uasm_rel_lo(addr));
e30ec452	472	else
33679a50 PB	473	uasm_i_addiu(buf, rs, rs,
33679a50 PB	474	uasm_rel_lo(addr));
e30ec452 TS	475	}
e30ec452 TS	476	}
33679a50	477	UASM_EXPORT_SYMBOL(UASM_i_LA);
e30ec452 TS	478
e30ec452 TS	479	/* Handle relocations. */
33679a50	480	void uasm_r_mips_pc16(struct uasm_reloc *rel, u32 addr, int lid)
e30ec452 TS	481	{
	482	(*rel)->addr = addr;
	483	(*rel)->type = R_MIPS_PC16;
	484	(*rel)->lab = lid;
	485	(*rel)++;
	486	}
33679a50	487	UASM_EXPORT_SYMBOL(uasm_r_mips_pc16);
e30ec452	488
078a55fc PG	489	static inline void __resolve_relocs(struct uasm_reloc *rel,
078a55fc PG	490	struct uasm_label *lab);
e30ec452	491
33679a50	492	void uasm_resolve_relocs(struct uasm_reloc *rel,
078a55fc	493	struct uasm_label *lab)
e30ec452 TS	494	{
	495	struct uasm_label *l;
	496
	497	for (; rel->lab != UASM_LABEL_INVALID; rel++)
	498	for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
	499	if (rel->lab == l->lab)
	500	__resolve_relocs(rel, l);
	501	}
33679a50	502	UASM_EXPORT_SYMBOL(uasm_resolve_relocs);
e30ec452	503
33679a50	504	void uasm_move_relocs(struct uasm_reloc rel, u32 first, u32 *end,
078a55fc	505	long off)
e30ec452 TS	506	{
	507	for (; rel->lab != UASM_LABEL_INVALID; rel++)
	508	if (rel->addr >= first && rel->addr < end)
	509	rel->addr += off;
	510	}
33679a50	511	UASM_EXPORT_SYMBOL(uasm_move_relocs);
e30ec452	512
33679a50	513	void uasm_move_labels(struct uasm_label lab, u32 first, u32 *end,
078a55fc	514	long off)
e30ec452 TS	515	{
	516	for (; lab->lab != UASM_LABEL_INVALID; lab++)
	517	if (lab->addr >= first && lab->addr < end)
	518	lab->addr += off;
	519	}
33679a50	520	UASM_EXPORT_SYMBOL(uasm_move_labels);
e30ec452	521
33679a50	522	void uasm_copy_handler(struct uasm_reloc rel, struct uasm_label lab,
078a55fc	523	u32 first, u32 end, u32 *target)
e30ec452 TS	524	{
	525	long off = (long)(target - first);
	526
	527	memcpy(target, first, (end - first) * sizeof(u32));
	528
33679a50 PB	529	uasm_move_relocs(rel, first, end, off);
33679a50 PB	530	uasm_move_labels(lab, first, end, off);
e30ec452	531	}
33679a50	532	UASM_EXPORT_SYMBOL(uasm_copy_handler);
e30ec452	533
33679a50	534	int uasm_insn_has_bdelay(struct uasm_reloc rel, u32 addr)
e30ec452 TS	535	{
	536	for (; rel->lab != UASM_LABEL_INVALID; rel++) {
	537	if (rel->addr == addr
	538	&& (rel->type == R_MIPS_PC16
	539	\|\| rel->type == R_MIPS_26))
	540	return 1;
	541	}
	542
	543	return 0;
	544	}
33679a50	545	UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay);
e30ec452 TS	546
e30ec452 TS	547	/* Convenience functions for labeled branches. */
33679a50	548	void uasm_il_bltz(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc	549	int lid)
e30ec452 TS	550	{
e30ec452 TS	551	uasm_r_mips_pc16(r, *p, lid);
33679a50	552	uasm_i_bltz(p, reg, 0);
e30ec452	553	}
33679a50	554	UASM_EXPORT_SYMBOL(uasm_il_bltz);
e30ec452	555
33679a50	556	void uasm_il_b(u32 p, struct uasm_reloc r, int lid)
e30ec452 TS	557	{
e30ec452 TS	558	uasm_r_mips_pc16(r, *p, lid);
33679a50	559	uasm_i_b(p, 0);
e30ec452	560	}
33679a50	561	UASM_EXPORT_SYMBOL(uasm_il_b);
e30ec452	562
33679a50	563	void uasm_il_beq(u32 p, struct uasm_reloc r, unsigned int r1,
8dee5901 PB	564	unsigned int r2, int lid)
	565	{
	566	uasm_r_mips_pc16(r, *p, lid);
33679a50	567	uasm_i_beq(p, r1, r2, 0);
8dee5901	568	}
33679a50	569	UASM_EXPORT_SYMBOL(uasm_il_beq);
8dee5901	570
33679a50	571	void uasm_il_beqz(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc	572	int lid)
e30ec452 TS	573	{
e30ec452 TS	574	uasm_r_mips_pc16(r, *p, lid);
33679a50	575	uasm_i_beqz(p, reg, 0);
e30ec452	576	}
33679a50	577	UASM_EXPORT_SYMBOL(uasm_il_beqz);
e30ec452	578
33679a50	579	void uasm_il_beqzl(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc	580	int lid)
e30ec452 TS	581	{
e30ec452 TS	582	uasm_r_mips_pc16(r, *p, lid);
33679a50	583	uasm_i_beqzl(p, reg, 0);
e30ec452	584	}
33679a50	585	UASM_EXPORT_SYMBOL(uasm_il_beqzl);
e30ec452	586
33679a50	587	void uasm_il_bne(u32 p, struct uasm_reloc r, unsigned int reg1,
078a55fc	588	unsigned int reg2, int lid)
fb2a27e7 TS	589	{
fb2a27e7 TS	590	uasm_r_mips_pc16(r, *p, lid);
33679a50	591	uasm_i_bne(p, reg1, reg2, 0);
fb2a27e7	592	}
33679a50	593	UASM_EXPORT_SYMBOL(uasm_il_bne);
fb2a27e7	594
33679a50	595	void uasm_il_bnez(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc	596	int lid)
e30ec452 TS	597	{
e30ec452 TS	598	uasm_r_mips_pc16(r, *p, lid);
33679a50	599	uasm_i_bnez(p, reg, 0);
e30ec452	600	}
33679a50	601	UASM_EXPORT_SYMBOL(uasm_il_bnez);
e30ec452	602
33679a50	603	void uasm_il_bgezl(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc	604	int lid)
e30ec452 TS	605	{
e30ec452 TS	606	uasm_r_mips_pc16(r, *p, lid);
33679a50	607	uasm_i_bgezl(p, reg, 0);
e30ec452	608	}
33679a50	609	UASM_EXPORT_SYMBOL(uasm_il_bgezl);
e30ec452	610
33679a50	611	void uasm_il_bgez(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc	612	int lid)
e30ec452 TS	613	{
e30ec452 TS	614	uasm_r_mips_pc16(r, *p, lid);
33679a50	615	uasm_i_bgez(p, reg, 0);
e30ec452	616	}
33679a50	617	UASM_EXPORT_SYMBOL(uasm_il_bgez);
5b97c3f7	618
33679a50	619	void uasm_il_bbit0(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc	620	unsigned int bit, int lid)
5b97c3f7 DD	621	{
5b97c3f7 DD	622	uasm_r_mips_pc16(r, *p, lid);
33679a50	623	uasm_i_bbit0(p, reg, bit, 0);
5b97c3f7	624	}
33679a50	625	UASM_EXPORT_SYMBOL(uasm_il_bbit0);
5b97c3f7	626
33679a50	627	void uasm_il_bbit1(u32 p, struct uasm_reloc r, unsigned int reg,
078a55fc	628	unsigned int bit, int lid)
5b97c3f7 DD	629	{
5b97c3f7 DD	630	uasm_r_mips_pc16(r, *p, lid);
33679a50	631	uasm_i_bbit1(p, reg, bit, 0);
5b97c3f7	632	}
33679a50	633	UASM_EXPORT_SYMBOL(uasm_il_bbit1);