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1da177e4 LT |
1 | /* |
2 | * BRIEF MODULE DESCRIPTION | |
3 | * Momentum Computer Ocelot-G (CP7000G) - board dependent boot routines | |
4 | * | |
5 | * Copyright (C) 1996, 1997, 2001 Ralf Baechle | |
6 | * Copyright (C) 2000 RidgeRun, Inc. | |
7 | * Copyright (C) 2001 Red Hat, Inc. | |
8 | * Copyright (C) 2002 Momentum Computer | |
9 | * | |
10 | * Author: Matthew Dharm, Momentum Computer | |
11 | * mdharm@momenco.com | |
12 | * | |
13 | * Author: RidgeRun, Inc. | |
14 | * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com | |
15 | * | |
16 | * Copyright 2001 MontaVista Software Inc. | |
17 | * Author: jsun@mvista.com or jsun@junsun.net | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or modify it | |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2 of the License, or (at your | |
22 | * option) any later version. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
25 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
26 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
27 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
28 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
29 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
30 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
31 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
33 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
34 | * | |
35 | * You should have received a copy of the GNU General Public License along | |
36 | * with this program; if not, write to the Free Software Foundation, Inc., | |
37 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
38 | * | |
39 | */ | |
40 | #include <linux/config.h> | |
41 | #include <linux/init.h> | |
42 | #include <linux/kernel.h> | |
43 | #include <linux/types.h> | |
44 | #include <linux/mm.h> | |
45 | #include <linux/swap.h> | |
46 | #include <linux/ioport.h> | |
47 | #include <linux/sched.h> | |
48 | #include <linux/interrupt.h> | |
49 | #include <linux/pci.h> | |
fcdb27ad | 50 | #include <linux/pm.h> |
1da177e4 LT |
51 | #include <linux/timex.h> |
52 | #include <linux/vmalloc.h> | |
fcdb27ad | 53 | |
1da177e4 LT |
54 | #include <asm/time.h> |
55 | #include <asm/bootinfo.h> | |
56 | #include <asm/page.h> | |
57 | #include <asm/io.h> | |
58 | #include <asm/gt64240.h> | |
59 | #include <asm/irq.h> | |
60 | #include <asm/pci.h> | |
61 | #include <asm/processor.h> | |
62 | #include <asm/ptrace.h> | |
63 | #include <asm/reboot.h> | |
64 | #include <linux/bootmem.h> | |
65 | ||
66 | #include "ocelot_pld.h" | |
67 | ||
68 | #ifdef CONFIG_GALILLEO_GT64240_ETH | |
69 | extern unsigned char prom_mac_addr_base[6]; | |
70 | #endif | |
71 | ||
72 | unsigned long marvell_base; | |
73 | ||
74 | /* These functions are used for rebooting or halting the machine*/ | |
75 | extern void momenco_ocelot_restart(char *command); | |
76 | extern void momenco_ocelot_halt(void); | |
77 | extern void momenco_ocelot_power_off(void); | |
78 | ||
79 | extern void gt64240_time_init(void); | |
80 | extern void momenco_ocelot_irq_setup(void); | |
81 | ||
82 | static char reset_reason; | |
83 | ||
84 | static unsigned long ENTRYLO(unsigned long paddr) | |
85 | { | |
86 | return ((paddr & PAGE_MASK) | | |
87 | (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL | | |
88 | _CACHE_UNCACHED)) >> 6; | |
89 | } | |
90 | ||
91 | /* setup code for a handoff from a version 2 PMON 2000 PROM */ | |
92 | void PMON_v2_setup(void) | |
93 | { | |
94 | /* A wired TLB entry for the GT64240 and the serial port. The | |
95 | GT64240 is going to be hit on every IRQ anyway - there's | |
96 | absolutely no point in letting it be a random TLB entry, as | |
97 | it'll just cause needless churning of the TLB. And we use | |
98 | the other half for the serial port, which is just a PITA | |
99 | otherwise :) | |
100 | ||
101 | Device Physical Virtual | |
102 | GT64240 Internal Regs 0xf4000000 0xe0000000 | |
103 | UARTs (CS2) 0xfd000000 0xe0001000 | |
104 | */ | |
105 | add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), | |
106 | 0xf4000000, PM_64K); | |
107 | add_wired_entry(ENTRYLO(0xfd000000), ENTRYLO(0xfd001000), | |
108 | 0xfd000000, PM_4K); | |
109 | ||
110 | /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM | |
111 | in the CS[012] region. We can't use ioremap() yet. The NVRAM | |
112 | is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. | |
113 | ||
114 | Ocelot PLD (CS0) 0xfc000000 0xe0020000 | |
115 | NVRAM (CS1) 0xfc800000 0xe0030000 | |
116 | */ | |
117 | add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000), | |
118 | 0xfc000000, PM_64K); | |
119 | add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000), | |
120 | 0xfc800000, PM_64K); | |
121 | ||
122 | marvell_base = 0xf4000000; | |
123 | } | |
124 | ||
125 | extern int rm7k_tcache_enabled; | |
126 | ||
127 | /* | |
128 | * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache() | |
129 | */ | |
130 | #define Page_Invalidate_T 0x16 | |
131 | static void __init setup_l3cache(unsigned long size) | |
132 | { | |
133 | int register i; | |
134 | ||
135 | printk("Enabling L3 cache..."); | |
136 | ||
137 | /* Enable the L3 cache in the GT64120A's CPU Configuration register */ | |
138 | MV_WRITE(0, MV_READ(0) | (1<<14)); | |
139 | ||
140 | /* Enable the L3 cache in the CPU */ | |
141 | set_c0_config(1<<12 /* CONF_TE */); | |
142 | ||
143 | /* Clear the cache */ | |
144 | write_c0_taglo(0); | |
145 | write_c0_taghi(0); | |
146 | ||
147 | for (i=0; i < size; i+= 4096) { | |
148 | __asm__ __volatile__ ( | |
149 | ".set noreorder\n\t" | |
150 | ".set mips3\n\t" | |
151 | "cache %1, (%0)\n\t" | |
152 | ".set mips0\n\t" | |
153 | ".set reorder" | |
154 | : | |
155 | : "r" (KSEG0ADDR(i)), | |
156 | "i" (Page_Invalidate_T)); | |
157 | } | |
158 | ||
159 | /* Let the RM7000 MM code know that the tertiary cache is enabled */ | |
160 | rm7k_tcache_enabled = 1; | |
161 | ||
162 | printk("Done\n"); | |
163 | } | |
164 | ||
c83cfc9c | 165 | void __init plat_setup(void) |
1da177e4 LT |
166 | { |
167 | void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache); | |
168 | unsigned int tmpword; | |
169 | ||
170 | board_time_init = gt64240_time_init; | |
171 | ||
172 | _machine_restart = momenco_ocelot_restart; | |
173 | _machine_halt = momenco_ocelot_halt; | |
fcdb27ad | 174 | pm_power_off = momenco_ocelot_power_off; |
1da177e4 LT |
175 | |
176 | /* | |
177 | * initrd_start = (ulong)ocelot_initrd_start; | |
178 | * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size; | |
179 | * initrd_below_start_ok = 1; | |
180 | */ | |
181 | ||
182 | /* do handoff reconfiguration */ | |
183 | PMON_v2_setup(); | |
184 | ||
185 | #ifdef CONFIG_GALILLEO_GT64240_ETH | |
186 | /* get the mac addr */ | |
187 | memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6); | |
188 | #endif | |
189 | ||
190 | /* Turn off the Bit-Error LED */ | |
191 | OCELOT_PLD_WRITE(0x80, INTCLR); | |
192 | ||
193 | tmpword = OCELOT_PLD_READ(BOARDREV); | |
194 | if (tmpword < 26) | |
195 | printk("Momenco Ocelot-G: Board Assembly Rev. %c\n", 'A'+tmpword); | |
196 | else | |
197 | printk("Momenco Ocelot-G: Board Assembly Revision #0x%x\n", tmpword); | |
198 | ||
199 | tmpword = OCELOT_PLD_READ(PLD1_ID); | |
200 | printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15); | |
201 | tmpword = OCELOT_PLD_READ(PLD2_ID); | |
202 | printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15); | |
203 | tmpword = OCELOT_PLD_READ(RESET_STATUS); | |
204 | printk("Reset reason: 0x%x\n", tmpword); | |
205 | reset_reason = tmpword; | |
206 | OCELOT_PLD_WRITE(0xff, RESET_STATUS); | |
207 | ||
208 | tmpword = OCELOT_PLD_READ(BOARD_STATUS); | |
209 | printk("Board Status register: 0x%02x\n", tmpword); | |
210 | printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); | |
211 | printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); | |
212 | printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not"); | |
213 | printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1); | |
214 | printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3))); | |
215 | ||
216 | if (tmpword&12) | |
217 | l3func((1<<(((tmpword&12) >> 2)+20))); | |
218 | ||
219 | switch(tmpword &3) { | |
220 | case 3: | |
221 | /* 512MiB -- two banks of 256MiB */ | |
222 | add_memory_region( 0x0<<20, 0x100<<20, BOOT_MEM_RAM); | |
223 | /* | |
224 | add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM); | |
225 | */ | |
226 | break; | |
227 | case 2: | |
228 | /* 256MiB -- two banks of 128MiB */ | |
229 | add_memory_region( 0x0<<20, 0x80<<20, BOOT_MEM_RAM); | |
230 | add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM); | |
231 | break; | |
232 | case 1: | |
233 | /* 128MiB -- 64MiB per bank */ | |
234 | add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM); | |
235 | add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); | |
236 | break; | |
237 | case 0: | |
238 | /* 64MiB */ | |
239 | add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM); | |
240 | break; | |
241 | } | |
242 | ||
243 | /* FIXME: Fix up the DiskOnChip mapping */ | |
244 | MV_WRITE(0x468, 0xfef73); | |
1da177e4 LT |
245 | } |
246 | ||
1da177e4 LT |
247 | /* This needs to be one of the first initcalls, because no I/O port access |
248 | can work before this */ | |
249 | ||
250 | static int io_base_ioremap(void) | |
251 | { | |
252 | /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */ | |
253 | unsigned long io_remap_range; | |
254 | ||
255 | io_remap_range = (unsigned long) ioremap(0xc0000000, 0x30000000); | |
256 | if (!io_remap_range) | |
257 | panic("Could not ioremap I/O port range"); | |
258 | ||
259 | set_io_port_base(io_remap_range - 0xc0000000); | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | module_init(io_base_ioremap); |