[mirror_ubuntu-artful-kernel.git] / arch / mips / mti-sead3 / sead3-pic32-bus.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/errno.h>

#define PIC32_NULL	0x00
#define PIC32_RD	0x01
#define PIC32_SYSRD	0x02
#define PIC32_WR	0x10
#define PIC32_SYSWR	0x20
#define PIC32_IRQ_CLR	0x40
#define PIC32_STATUS	0x80

#define DELAY() udelay(100)	/* FIXME: needed? */

/* spinlock to ensure atomic access to PIC32 */
static DEFINE_SPINLOCK(pic32_bus_lock);

/* FIXME: io_remap these */
static void __iomem *bus_xfer	= (void __iomem *)0xbf000600;
static void __iomem *bus_status = (void __iomem *)0xbf000060;

static inline unsigned int ioready(void)
{
	return readl(bus_status) & 1;
}

static inline void wait_ioready(void)
{
	do { } while (!ioready());
}

static inline void wait_ioclear(void)
{
	do { } while (ioready());
}

static inline void check_ioclear(void)
{
	if (ioready()) {
		pr_debug("ioclear: initially busy\n");
		do {
			(void) readl(bus_xfer);
			DELAY();
		} while (ioready());
		pr_debug("ioclear: cleared busy\n");
	}
}

u32 pic32_bus_readl(u32 reg)
{
	unsigned long flags;
	u32 status, val;

	spin_lock_irqsave(&pic32_bus_lock, flags);

	check_ioclear();

	writel((PIC32_RD << 24) | (reg & 0x00ffffff), bus_xfer);
	DELAY();
	wait_ioready();
	status = readl(bus_xfer);
	DELAY();
	val = readl(bus_xfer);
	wait_ioclear();

	pr_debug("pic32_bus_readl: *%x -> %x (status=%x)\n", reg, val, status);

	spin_unlock_irqrestore(&pic32_bus_lock, flags);

	return val;
}

void pic32_bus_writel(u32 val, u32 reg)
{
	unsigned long flags;
	u32 status;

	spin_lock_irqsave(&pic32_bus_lock, flags);

	check_ioclear();

	writel((PIC32_WR << 24) | (reg & 0x00ffffff), bus_xfer);
	DELAY();
	writel(val, bus_xfer);
	DELAY();
	wait_ioready();
	status = readl(bus_xfer);
	wait_ioclear();

	pr_debug("pic32_bus_writel: *%x <- %x (status=%x)\n", reg, val, status);

	spin_unlock_irqrestore(&pic32_bus_lock, flags);
}
Commit	Line	Data
3070033a SH	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
	7	*/
	8	#include <linux/delay.h>
	9	#include <linux/kernel.h>
	10	#include <linux/spinlock.h>
	11	#include <linux/init.h>
	12	#include <linux/io.h>
	13	#include <linux/errno.h>
	14
	15	#define PIC32_NULL 0x00
	16	#define PIC32_RD 0x01
	17	#define PIC32_SYSRD 0x02
	18	#define PIC32_WR 0x10
	19	#define PIC32_SYSWR 0x20
70342287	20	#define PIC32_IRQ_CLR 0x40
3070033a SH	21	#define PIC32_STATUS 0x80
3070033a SH	22
70342287	23	#define DELAY() udelay(100) /* FIXME: needed? */
3070033a SH	24
	25	/* spinlock to ensure atomic access to PIC32 */
	26	static DEFINE_SPINLOCK(pic32_bus_lock);
	27
	28	/* FIXME: io_remap these */
70342287	29	static void __iomem bus_xfer = (void __iomem )0xbf000600;
3070033a SH	30	static void __iomem bus_status = (void __iomem )0xbf000060;
	31
	32	static inline unsigned int ioready(void)
	33	{
	34	return readl(bus_status) & 1;
	35	}
	36
	37	static inline void wait_ioready(void)
	38	{
	39	do { } while (!ioready());
	40	}
	41
	42	static inline void wait_ioclear(void)
	43	{
	44	do { } while (ioready());
	45	}
	46
	47	static inline void check_ioclear(void)
	48	{
	49	if (ioready()) {
	50	pr_debug("ioclear: initially busy\n");
	51	do {
	52	(void) readl(bus_xfer);
	53	DELAY();
	54	} while (ioready());
	55	pr_debug("ioclear: cleared busy\n");
	56	}
	57	}
	58
	59	u32 pic32_bus_readl(u32 reg)
	60	{
	61	unsigned long flags;
	62	u32 status, val;
	63
	64	spin_lock_irqsave(&pic32_bus_lock, flags);
	65
	66	check_ioclear();
	67
	68	writel((PIC32_RD << 24) \| (reg & 0x00ffffff), bus_xfer);
	69	DELAY();
	70	wait_ioready();
	71	status = readl(bus_xfer);
	72	DELAY();
	73	val = readl(bus_xfer);
	74	wait_ioclear();
	75
	76	pr_debug("pic32_bus_readl: *%x -> %x (status=%x)\n", reg, val, status);
	77
	78	spin_unlock_irqrestore(&pic32_bus_lock, flags);
	79
	80	return val;
	81	}
	82
	83	void pic32_bus_writel(u32 val, u32 reg)
	84	{
	85	unsigned long flags;
	86	u32 status;
	87
	88	spin_lock_irqsave(&pic32_bus_lock, flags);
	89
	90	check_ioclear();
	91
	92	writel((PIC32_WR << 24) \| (reg & 0x00ffffff), bus_xfer);
	93	DELAY();
94	writel(val, bus_xfer);
95	DELAY();
96	wait_ioready();
97	status = readl(bus_xfer);
98	wait_ioclear();
99
100	pr_debug("pic32_bus_writel: *%x <- %x (status=%x)\n", reg, val, status);
101
102	spin_unlock_irqrestore(&pic32_bus_lock, flags);
103	}