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5c642506 J |
1 | /* |
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | |
3 | * reserved. | |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the NetLogic | |
9 | * license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or without | |
12 | * modification, are permitted provided that the following conditions | |
13 | * are met: | |
14 | * | |
15 | * 1. Redistributions of source code must retain the above copyright | |
16 | * notice, this list of conditions and the following disclaimer. | |
17 | * 2. Redistributions in binary form must reproduce the above copyright | |
18 | * notice, this list of conditions and the following disclaimer in | |
19 | * the documentation and/or other materials provided with the | |
20 | * distribution. | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | |
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | |
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | |
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | |
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | |
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | |
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | |
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/init.h> | |
fc69910f | 38 | #include <linux/sched/task_stack.h> |
5c642506 J |
39 | #include <linux/smp.h> |
40 | #include <linux/irq.h> | |
41 | ||
42 | #include <asm/mmu_context.h> | |
43 | ||
44 | #include <asm/netlogic/interrupt.h> | |
45 | #include <asm/netlogic/mips-extns.h> | |
0c965407 J |
46 | #include <asm/netlogic/haldefs.h> |
47 | #include <asm/netlogic/common.h> | |
5c642506 | 48 | |
65040e22 J |
49 | #if defined(CONFIG_CPU_XLP) |
50 | #include <asm/netlogic/xlp-hal/iomap.h> | |
66d29985 | 51 | #include <asm/netlogic/xlp-hal/xlp.h> |
65040e22 J |
52 | #include <asm/netlogic/xlp-hal/pic.h> |
53 | #elif defined(CONFIG_CPU_XLR) | |
5c642506 J |
54 | #include <asm/netlogic/xlr/iomap.h> |
55 | #include <asm/netlogic/xlr/pic.h> | |
66d29985 | 56 | #include <asm/netlogic/xlr/xlr.h> |
65040e22 J |
57 | #else |
58 | #error "Unknown CPU" | |
59 | #endif | |
5c642506 | 60 | |
0c965407 | 61 | void nlm_send_ipi_single(int logical_cpu, unsigned int action) |
5c642506 | 62 | { |
c2736525 | 63 | unsigned int hwtid; |
77ae798f J |
64 | uint64_t picbase; |
65 | ||
c2736525 J |
66 | /* node id is part of hwtid, and needed for send_ipi */ |
67 | hwtid = cpu_logical_map(logical_cpu); | |
68 | picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase; | |
5c642506 J |
69 | |
70 | if (action & SMP_CALL_FUNCTION) | |
c2736525 | 71 | nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_FUNCTION, 0); |
0c965407 | 72 | if (action & SMP_RESCHEDULE_YOURSELF) |
c2736525 | 73 | nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_RESCHEDULE, 0); |
5c642506 J |
74 | } |
75 | ||
76 | void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) | |
77 | { | |
78 | int cpu; | |
79 | ||
80 | for_each_cpu(cpu, mask) { | |
0c965407 | 81 | nlm_send_ipi_single(cpu, action); |
5c642506 J |
82 | } |
83 | } | |
84 | ||
85 | /* IRQ_IPI_SMP_FUNCTION Handler */ | |
bd0b9ac4 | 86 | void nlm_smp_function_ipi_handler(struct irq_desc *desc) |
5c642506 | 87 | { |
31429d1a | 88 | unsigned int irq = irq_desc_get_irq(desc); |
220d9122 J |
89 | clear_c0_eimr(irq); |
90 | ack_c0_eirr(irq); | |
4ace6139 | 91 | generic_smp_call_function_interrupt(); |
220d9122 | 92 | set_c0_eimr(irq); |
5c642506 J |
93 | } |
94 | ||
95 | /* IRQ_IPI_SMP_RESCHEDULE handler */ | |
bd0b9ac4 | 96 | void nlm_smp_resched_ipi_handler(struct irq_desc *desc) |
5c642506 | 97 | { |
31429d1a | 98 | unsigned int irq = irq_desc_get_irq(desc); |
220d9122 J |
99 | clear_c0_eimr(irq); |
100 | ack_c0_eirr(irq); | |
65040e22 | 101 | scheduler_ipi(); |
220d9122 | 102 | set_c0_eimr(irq); |
5c642506 J |
103 | } |
104 | ||
105 | /* | |
106 | * Called before going into mips code, early cpu init | |
107 | */ | |
0c965407 | 108 | void nlm_early_init_secondary(int cpu) |
5c642506 | 109 | { |
65040e22 | 110 | change_c0_config(CONF_CM_CMASK, 0x3); |
65040e22 | 111 | #ifdef CONFIG_CPU_XLP |
5b6ff35d | 112 | xlp_mmu_init(); |
0c965407 | 113 | #endif |
77ae798f | 114 | write_c0_ebase(nlm_current_node()->ebase); |
5c642506 J |
115 | } |
116 | ||
117 | /* | |
118 | * Code to run on secondary just after probing the CPU | |
119 | */ | |
078a55fc | 120 | static void nlm_init_secondary(void) |
5c642506 | 121 | { |
38541742 J |
122 | int hwtid; |
123 | ||
124 | hwtid = hard_smp_processor_id(); | |
f875a832 | 125 | cpu_set_core(¤t_cpu_data, hwtid / NLM_THREADS_PER_CORE); |
c2736525 | 126 | current_cpu_data.package = nlm_nodeid(); |
ed21cfe2 | 127 | nlm_percpu_init(hwtid); |
38541742 | 128 | nlm_smp_irq_init(hwtid); |
5c642506 J |
129 | } |
130 | ||
b3ea5818 HD |
131 | void nlm_prepare_cpus(unsigned int max_cpus) |
132 | { | |
133 | /* declare we are SMT capable */ | |
134 | smp_num_siblings = nlm_threads_per_core; | |
135 | } | |
136 | ||
5c642506 J |
137 | void nlm_smp_finish(void) |
138 | { | |
39263eeb | 139 | local_irq_enable(); |
5c642506 J |
140 | } |
141 | ||
5c642506 J |
142 | /* |
143 | * Boot all other cpus in the system, initialize them, and bring them into | |
144 | * the boot function | |
145 | */ | |
5c642506 J |
146 | unsigned long nlm_next_gp; |
147 | unsigned long nlm_next_sp; | |
62b734d2 | 148 | static cpumask_t phys_cpu_present_mask; |
5c642506 | 149 | |
d595d423 | 150 | int nlm_boot_secondary(int logical_cpu, struct task_struct *idle) |
5c642506 | 151 | { |
c2736525 J |
152 | uint64_t picbase; |
153 | int hwtid; | |
154 | ||
155 | hwtid = cpu_logical_map(logical_cpu); | |
156 | picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase; | |
5c642506 | 157 | |
77ae798f J |
158 | nlm_next_sp = (unsigned long)__KSTK_TOS(idle); |
159 | nlm_next_gp = (unsigned long)task_thread_info(idle); | |
5c642506 | 160 | |
77ae798f | 161 | /* barrier for sp/gp store above */ |
5c642506 | 162 | __sync(); |
c2736525 | 163 | nlm_pic_send_ipi(picbase, hwtid, 1, 1); /* NMI */ |
d595d423 PB |
164 | |
165 | return 0; | |
5c642506 J |
166 | } |
167 | ||
168 | void __init nlm_smp_setup(void) | |
169 | { | |
170 | unsigned int boot_cpu; | |
98d4884c | 171 | int num_cpus, i, ncore, node; |
919f9abb | 172 | volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); |
5c642506 J |
173 | |
174 | boot_cpu = hard_smp_processor_id(); | |
62b734d2 | 175 | cpumask_clear(&phys_cpu_present_mask); |
5c642506 | 176 | |
62b734d2 | 177 | cpumask_set_cpu(boot_cpu, &phys_cpu_present_mask); |
5c642506 J |
178 | __cpu_number_map[boot_cpu] = 0; |
179 | __cpu_logical_map[0] = boot_cpu; | |
0b5f9c00 | 180 | set_cpu_possible(0, true); |
5c642506 J |
181 | |
182 | num_cpus = 1; | |
183 | for (i = 0; i < NR_CPUS; i++) { | |
b2788965 | 184 | /* |
919f9abb | 185 | * cpu_ready array is not set for the boot_cpu, |
0c965407 | 186 | * it is only set for ASPs (see smpboot.S) |
b2788965 | 187 | */ |
919f9abb | 188 | if (cpu_ready[i]) { |
62b734d2 | 189 | cpumask_set_cpu(i, &phys_cpu_present_mask); |
5c642506 J |
190 | __cpu_number_map[i] = num_cpus; |
191 | __cpu_logical_map[num_cpus] = i; | |
0b5f9c00 | 192 | set_cpu_possible(num_cpus, true); |
c2736525 | 193 | node = nlm_hwtid_to_node(i); |
98d4884c | 194 | cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask); |
5c642506 J |
195 | ++num_cpus; |
196 | } | |
197 | } | |
198 | ||
729d8e09 TH |
199 | pr_info("Physical CPU mask: %*pb\n", |
200 | cpumask_pr_args(&phys_cpu_present_mask)); | |
201 | pr_info("Possible CPU mask: %*pb\n", | |
202 | cpumask_pr_args(cpu_possible_mask)); | |
62b734d2 | 203 | |
2e240ddd | 204 | /* check with the cores we have woken up */ |
77ae798f J |
205 | for (ncore = 0, i = 0; i < NLM_NR_NODES; i++) |
206 | ncore += hweight32(nlm_get_node(i)->coremask); | |
207 | ||
77ae798f J |
208 | pr_info("Detected (%dc%dt) %d Slave CPU(s)\n", ncore, |
209 | nlm_threads_per_core, num_cpus); | |
62b734d2 J |
210 | |
211 | /* switch NMI handler to boot CPUs */ | |
66d29985 | 212 | nlm_set_nmi_handler(nlm_boot_secondary_cpus); |
5c642506 J |
213 | } |
214 | ||
2a37b1ae | 215 | static int nlm_parse_cpumask(cpumask_t *wakeup_mask) |
66d29985 J |
216 | { |
217 | uint32_t core0_thr_mask, core_thr_mask; | |
2a37b1ae | 218 | int threadmode, i, j; |
66d29985 | 219 | |
2a37b1ae | 220 | core0_thr_mask = 0; |
77ae798f | 221 | for (i = 0; i < NLM_THREADS_PER_CORE; i++) |
2a37b1ae J |
222 | if (cpumask_test_cpu(i, wakeup_mask)) |
223 | core0_thr_mask |= (1 << i); | |
66d29985 J |
224 | switch (core0_thr_mask) { |
225 | case 1: | |
226 | nlm_threads_per_core = 1; | |
227 | threadmode = 0; | |
228 | break; | |
229 | case 3: | |
230 | nlm_threads_per_core = 2; | |
231 | threadmode = 2; | |
232 | break; | |
233 | case 0xf: | |
234 | nlm_threads_per_core = 4; | |
235 | threadmode = 3; | |
236 | break; | |
237 | default: | |
238 | goto unsupp; | |
239 | } | |
240 | ||
241 | /* Verify other cores CPU masks */ | |
77ae798f | 242 | for (i = 0; i < NR_CPUS; i += NLM_THREADS_PER_CORE) { |
2a37b1ae | 243 | core_thr_mask = 0; |
77ae798f | 244 | for (j = 0; j < NLM_THREADS_PER_CORE; j++) |
2a37b1ae J |
245 | if (cpumask_test_cpu(i + j, wakeup_mask)) |
246 | core_thr_mask |= (1 << j); | |
247 | if (core_thr_mask != 0 && core_thr_mask != core0_thr_mask) | |
66d29985 | 248 | goto unsupp; |
66d29985 J |
249 | } |
250 | return threadmode; | |
251 | ||
252 | unsupp: | |
729d8e09 | 253 | panic("Unsupported CPU mask %*pb", cpumask_pr_args(wakeup_mask)); |
66d29985 J |
254 | return 0; |
255 | } | |
256 | ||
078a55fc | 257 | int nlm_wakeup_secondary_cpus(void) |
66d29985 | 258 | { |
53c83219 | 259 | u32 *reset_data; |
66d29985 J |
260 | int threadmode; |
261 | ||
66d29985 | 262 | /* verify the mask and setup core config variables */ |
2a37b1ae | 263 | threadmode = nlm_parse_cpumask(&nlm_cpumask); |
66d29985 J |
264 | |
265 | /* Setup CPU init parameters */ | |
53c83219 J |
266 | reset_data = nlm_get_boot_data(BOOT_THREAD_MODE); |
267 | *reset_data = threadmode; | |
66d29985 J |
268 | |
269 | #ifdef CONFIG_CPU_XLP | |
270 | xlp_wakeup_secondary_cpus(); | |
271 | #else | |
272 | xlr_wakeup_secondary_cpus(); | |
273 | #endif | |
274 | return 0; | |
275 | } | |
276 | ||
ff2c8252 | 277 | const struct plat_smp_ops nlm_smp_ops = { |
5c642506 J |
278 | .send_ipi_single = nlm_send_ipi_single, |
279 | .send_ipi_mask = nlm_send_ipi_mask, | |
280 | .init_secondary = nlm_init_secondary, | |
281 | .smp_finish = nlm_smp_finish, | |
5c642506 J |
282 | .boot_secondary = nlm_boot_secondary, |
283 | .smp_setup = nlm_smp_setup, | |
284 | .prepare_cpus = nlm_prepare_cpus, | |
285 | }; |