[mirror_ubuntu-artful-kernel.git] / arch / mips / netlogic / common / smpboot.S

/*
 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
 * reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the NetLogic
 * license below:
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */


#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#include <asm/asmmacro.h>
#include <asm/addrspace.h>

#include <asm/netlogic/common.h>

#include <asm/netlogic/xlp-hal/iomap.h>
#include <asm/netlogic/xlp-hal/xlp.h>
#include <asm/netlogic/xlp-hal/sys.h>
#include <asm/netlogic/xlp-hal/cpucontrol.h>

#define CP0_EBASE	$15

	.set	noreorder
	.set	noat
	.set	arch=xlr		/* for mfcr/mtcr, XLR is sufficient */

/* Called by the boot cpu to wake up its sibling threads */
NESTED(xlp_boot_core0_siblings, PT_SIZE, sp)
	/* CPU register contents lost when enabling threads, save them first */
	SAVE_ALL
	sync
	/* find the location to which nlm_boot_siblings was relocated */
	li	t0, CKSEG1ADDR(RESET_VEC_PHYS)
	dla	t1, nlm_reset_entry
	dla	t2, nlm_boot_siblings
	dsubu	t2, t1
	daddu	t2, t0
	/* call it */
	jalr	t2
	nop
	RESTORE_ALL
	jr	ra
	nop
END(xlp_boot_core0_siblings)

NESTED(nlm_boot_secondary_cpus, 16, sp)
	/* Initialize CP0 Status */
	move	t1, zero
#ifdef CONFIG_64BIT
	ori	t1, ST0_KX
#endif
	mtc0	t1, CP0_STATUS
	PTR_LA	t1, nlm_next_sp
	PTR_L	sp, 0(t1)
	PTR_LA	t1, nlm_next_gp
	PTR_L	gp, 0(t1)

	/* a0 has the processor id */
	mfc0	a0, CP0_EBASE, 1
	andi	a0, 0x3ff		/* a0 <- node/core */
	PTR_LA	t0, nlm_early_init_secondary
	jalr	t0
	nop

	PTR_LA	t0, smp_bootstrap
	jr	t0
	nop
END(nlm_boot_secondary_cpus)

/*
 * In case of RMIboot bootloader which is used on XLR boards, the CPUs
 * be already woken up and waiting in bootloader code.
 * This will get them out of the bootloader code and into linux. Needed
 * because the bootloader area will be taken and initialized by linux.
 */
NESTED(nlm_rmiboot_preboot, 16, sp)
	mfc0	t0, $15, 1	/* read ebase */
	andi	t0, 0x1f	/* t0 has the processor_id() */
	andi	t2, t0, 0x3	/* thread num */
	sll	t0, 2		/* offset in cpu array */

	li	t3, CKSEG1ADDR(RESET_DATA_PHYS)
	ADDIU	t1, t3, BOOT_CPU_READY
	ADDU	t1, t0
	li	t3, 1
	sw	t3, 0(t1)

	bnez	t2, 1f		/* skip thread programming */
	nop			/* for thread id != 0 */

	/*
	 * XLR MMU setup only for first thread in core
	 */
	li	t0, 0x400
	mfcr	t1, t0
	li	t2, 6		/* XLR thread mode mask */
	nor	t3, t2, zero
	and	t2, t1, t2	/* t2 - current thread mode */
	li	v0, CKSEG1ADDR(RESET_DATA_PHYS)
	lw	v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
	sll	v1, 1
	beq	v1, t2, 1f	/* same as request value */
	nop			/* nothing to do */

	and	t2, t1, t3	/* mask out old thread mode */
	or	t1, t2, v1	/* put in new value */
	mtcr	t1, t0		/* update core control */

	/* wait for NMI to hit */
1:	wait
	b	1b
	nop
END(nlm_rmiboot_preboot)
Commit	Line	Data
65040e22 J	1	/*
	2	* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
	3	* reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the NetLogic
	9	* license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or without
	12	* modification, are permitted provided that the following conditions
	13	* are met:
	14	*
	15	* 1. Redistributions of source code must retain the above copyright
	16	* notice, this list of conditions and the following disclaimer.
	17	* 2. Redistributions in binary form must reproduce the above copyright
	18	* notice, this list of conditions and the following disclaimer in
	19	* the documentation and/or other materials provided with the
	20	* distribution.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
	23	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	24	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	25	* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	27	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	28	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
	29	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
	30	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
	31	* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
	32	* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
65040e22 J	35
	36	#include <asm/asm.h>
	37	#include <asm/asm-offsets.h>
	38	#include <asm/regdef.h>
	39	#include <asm/mipsregs.h>
	40	#include <asm/stackframe.h>
	41	#include <asm/asmmacro.h>
	42	#include <asm/addrspace.h>
	43
66d29985 J	44	#include <asm/netlogic/common.h>
66d29985 J	45
65040e22 J	46	#include <asm/netlogic/xlp-hal/iomap.h>
	47	#include <asm/netlogic/xlp-hal/xlp.h>
	48	#include <asm/netlogic/xlp-hal/sys.h>
	49	#include <asm/netlogic/xlp-hal/cpucontrol.h>
	50
70342287	51	#define CP0_EBASE $15
66d29985	52
65040e22	53	.set noreorder
66d29985	54	.set noat
9584c55a	55	.set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
65040e22	56
a3deecfa J	57	/* Called by the boot cpu to wake up its sibling threads */
	58	NESTED(xlp_boot_core0_siblings, PT_SIZE, sp)
	59	/* CPU register contents lost when enabling threads, save them first */
65040e22 J	60	SAVE_ALL
	61	sync
	62	/* find the location to which nlm_boot_siblings was relocated */
	63	li t0, CKSEG1ADDR(RESET_VEC_PHYS)
	64	dla t1, nlm_reset_entry
	65	dla t2, nlm_boot_siblings
	66	dsubu t2, t1
	67	daddu t2, t0
	68	/* call it */
a3deecfa	69	jalr t2
65040e22	70	nop
a3deecfa J	71	RESTORE_ALL
	72	jr ra
	73	nop
	74	END(xlp_boot_core0_siblings)
65040e22	75
66d29985	76	NESTED(nlm_boot_secondary_cpus, 16, sp)
51d1eac0 J	77	/* Initialize CP0 Status */
	78	move t1, zero
	79	#ifdef CONFIG_64BIT
	80	ori t1, ST0_KX
	81	#endif
	82	mtc0 t1, CP0_STATUS
66d29985	83	PTR_LA t1, nlm_next_sp
65040e22 J	84	PTR_L sp, 0(t1)
	85	PTR_LA t1, nlm_next_gp
	86	PTR_L gp, 0(t1)
	87
	88	/* a0 has the processor id */
feddaf7d J	89	mfc0 a0, CP0_EBASE, 1
feddaf7d J	90	andi a0, 0x3ff /* a0 <- node/core */
65040e22 J	91	PTR_LA t0, nlm_early_init_secondary
	92	jalr t0
	93	nop
	94
	95	PTR_LA t0, smp_bootstrap
	96	jr t0
	97	nop
66d29985	98	END(nlm_boot_secondary_cpus)
66d29985 J	99
	100	/*
	101	* In case of RMIboot bootloader which is used on XLR boards, the CPUs
	102	* be already woken up and waiting in bootloader code.
	103	* This will get them out of the bootloader code and into linux. Needed
d3b94285	104	* because the bootloader area will be taken and initialized by linux.
66d29985	105	*/
66d29985	106	NESTED(nlm_rmiboot_preboot, 16, sp)
cedc8ef8 J	107	mfc0 t0, $15, 1 /* read ebase */
	108	andi t0, 0x1f /* t0 has the processor_id() */
	109	andi t2, t0, 0x3 /* thread num */
	110	sll t0, 2 /* offset in cpu array */
66d29985	111
919f9abb J	112	li t3, CKSEG1ADDR(RESET_DATA_PHYS)
	113	ADDIU t1, t3, BOOT_CPU_READY
	114	ADDU t1, t0
66d29985 J	115	li t3, 1
	116	sw t3, 0(t1)
	117
cedc8ef8 J	118	bnez t2, 1f /* skip thread programming */
cedc8ef8 J	119	nop /* for thread id != 0 */
66d29985 J	120
66d29985 J	121	/*
cedc8ef8	122	* XLR MMU setup only for first thread in core
66d29985 J	123	*/
	124	li t0, 0x400
	125	mfcr t1, t0
70342287	126	li t2, 6 /* XLR thread mode mask */
66d29985	127	nor t3, t2, zero
cedc8ef8	128	and t2, t1, t2 /* t2 - current thread mode */
66d29985	129	li v0, CKSEG1ADDR(RESET_DATA_PHYS)
cedc8ef8	130	lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
66d29985	131	sll v1, 1
70342287	132	beq v1, t2, 1f /* same as request value */
cedc8ef8	133	nop /* nothing to do */
66d29985	134
cedc8ef8 J	135	and t2, t1, t3 /* mask out old thread mode */
	136	or t1, t2, v1 /* put in new value */
	137	mtcr t1, t0 /* update core control */
66d29985	138
d3b94285	139	/* wait for NMI to hit */
66d29985	140	1: wait
fd5f527c	141	b 1b
66d29985 J	142	nop
66d29985 J	143	END(nlm_rmiboot_preboot)