[mirror_ubuntu-artful-kernel.git] / arch / mips / netlogic / xlp / nlm_hal.c

/*
 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
 * reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the NetLogic
 * license below:
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/delay.h>

#include <asm/mipsregs.h>
#include <asm/time.h>

#include <asm/netlogic/common.h>
#include <asm/netlogic/haldefs.h>
#include <asm/netlogic/xlp-hal/iomap.h>
#include <asm/netlogic/xlp-hal/xlp.h>
#include <asm/netlogic/xlp-hal/bridge.h>
#include <asm/netlogic/xlp-hal/pic.h>
#include <asm/netlogic/xlp-hal/sys.h>

/* Main initialization */
void nlm_node_init(int node)
{
	struct nlm_soc_info *nodep;

	nodep = nlm_get_node(node);
	nodep->sysbase = nlm_get_sys_regbase(node);
	nodep->picbase = nlm_get_pic_regbase(node);
	nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
	if (cpu_is_xlp9xx())
		nodep->socbus = xlp9xx_get_socbus(node);
	else
		nodep->socbus = 0;
	spin_lock_init(&nodep->piclock);
}

int nlm_irq_to_irt(int irq)
{
	uint64_t pcibase;
	int devoff, irt;

	/* bypass for 9xx */
	if (cpu_is_xlp9xx()) {
		switch (irq) {
		case PIC_UART_0_IRQ:
			return 133;
		case PIC_UART_1_IRQ:
			return 134;
		}
		return -1;
	}

	devoff = 0;
	switch (irq) {
	case PIC_UART_0_IRQ:
		devoff = XLP_IO_UART0_OFFSET(0);
		break;
	case PIC_UART_1_IRQ:
		devoff = XLP_IO_UART1_OFFSET(0);
		break;
	case PIC_MMC_IRQ:
		devoff = XLP_IO_SD_OFFSET(0);
		break;
	case PIC_I2C_0_IRQ:	/* I2C will be fixed up */
	case PIC_I2C_1_IRQ:
	case PIC_I2C_2_IRQ:
	case PIC_I2C_3_IRQ:
		if (cpu_is_xlpii())
			devoff = XLP2XX_IO_I2C_OFFSET(0);
		else
			devoff = XLP_IO_I2C0_OFFSET(0);
		break;
	default:
		if (cpu_is_xlpii()) {
			switch (irq) {
				/* XLP2XX has three XHCI USB controller */
			case PIC_2XX_XHCI_0_IRQ:
				devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
				break;
			case PIC_2XX_XHCI_1_IRQ:
				devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
				break;
			case PIC_2XX_XHCI_2_IRQ:
				devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
				break;
			}
		} else {
			switch (irq) {
			case PIC_EHCI_0_IRQ:
				devoff = XLP_IO_USB_EHCI0_OFFSET(0);
				break;
			case PIC_EHCI_1_IRQ:
				devoff = XLP_IO_USB_EHCI1_OFFSET(0);
				break;
			case PIC_OHCI_0_IRQ:
				devoff = XLP_IO_USB_OHCI0_OFFSET(0);
				break;
			case PIC_OHCI_1_IRQ:
				devoff = XLP_IO_USB_OHCI1_OFFSET(0);
				break;
			case PIC_OHCI_2_IRQ:
				devoff = XLP_IO_USB_OHCI2_OFFSET(0);
				break;
			case PIC_OHCI_3_IRQ:
				devoff = XLP_IO_USB_OHCI3_OFFSET(0);
				break;
			}
		}
	}

	if (devoff != 0) {
		pcibase = nlm_pcicfg_base(devoff);
		irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
		/* HW weirdness, I2C IRT entry has to be fixed up */
		switch (irq) {
		case PIC_I2C_1_IRQ:
			irt = irt + 1; break;
		case PIC_I2C_2_IRQ:
			irt = irt + 2; break;
		case PIC_I2C_3_IRQ:
			irt = irt + 3; break;
		}
	} else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
			irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
		/* HW bug, PCI IRT entries are bad on early silicon, fix */
		irt = PIC_IRT_PCIE_LINK_INDEX(irq -
					PIC_PCIE_LINK_LEGACY_IRQ_BASE);
	} else if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) &&
			irq <= PIC_PCIE_LINK_MSI_IRQ(3)) {
		irt = -2;
	} else if (irq >= PIC_PCIE_MSIX_IRQ(0) &&
			irq <= PIC_PCIE_MSIX_IRQ(3)) {
		irt = -2;
	} else {
		irt = -1;
	}
	return irt;
}

unsigned int nlm_get_core_frequency(int node, int core)
{
	unsigned int pll_divf, pll_divr, dfs_div, ext_div;
	unsigned int rstval, dfsval, denom;
	uint64_t num, sysbase;

	sysbase = nlm_get_node(node)->sysbase;
	if (cpu_is_xlp9xx())
		rstval = nlm_read_sys_reg(sysbase, SYS_9XX_POWER_ON_RESET_CFG);
	else
		rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
	if (cpu_is_xlpii()) {
		num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
		denom = 3;
	} else {
		dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
		pll_divf = ((rstval >> 10) & 0x7f) + 1;
		pll_divr = ((rstval >> 8)  & 0x3) + 1;
		ext_div  = ((rstval >> 30) & 0x3) + 1;
		dfs_div  = ((dfsval >> (core * 4)) & 0xf) + 1;

		num = 800000000ULL * pll_divf;
		denom = 3 * pll_divr * ext_div * dfs_div;
	}
	do_div(num, denom);
	return (unsigned int)num;
}

/* Calculate Frequency to the PIC from PLL.
 * freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) /
 * ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
 */
static unsigned int nlm_2xx_get_pic_frequency(int node)
{
	u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div;
	u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
	u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select;

	sysbase = nlm_get_node(node)->sysbase;

	/* Find ref_clk_base */
	ref_clk_select =
		(nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
	switch (ref_clk_select) {
	case 0:
		ref_clk = 200000000ULL;
		ref_div = 3;
		break;
	case 1:
		ref_clk = 100000000ULL;
		ref_div = 1;
		break;
	case 2:
		ref_clk = 125000000ULL;
		ref_div = 1;
		break;
	case 3:
		ref_clk = 400000000ULL;
		ref_div = 3;
		break;
	}

	/* Find the clock source PLL device for PIC */
	reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3;
	switch (reg_select) {
	case 0:
		ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0);
		ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2);
		break;
	case 1:
		ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0));
		ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0));
		break;
	case 2:
		ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1));
		ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1));
		break;
	case 3:
		ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2));
		ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2));
		break;
	}

	vco_post_div = (ctrl_val0 >> 5) & 0x7;
	pll_post_div = (ctrl_val0 >> 24) & 0x7;
	mdiv = ctrl_val2 & 0xff;
	fdiv = (ctrl_val2 >> 8) & 0xfff;

	/* Find PLL post divider value */
	switch (pll_post_div) {
	case 1:
		pll_post_div = 2;
		break;
	case 3:
		pll_post_div = 4;
		break;
	case 7:
		pll_post_div = 8;
		break;
	case 6:
		pll_post_div = 16;
		break;
	case 0:
	default:
		pll_post_div = 1;
		break;
	}

	fdiv = fdiv/(1 << 13);
	pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
	pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;

	if (pll_out_freq_den > 0)
		do_div(pll_out_freq_num, pll_out_freq_den);

	/* PIC post divider, which happens after PLL */
	pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3;
	do_div(pll_out_freq_num, 1 << pic_div);

	return pll_out_freq_num;
}

unsigned int nlm_get_pic_frequency(int node)
{
	/* TODO Has to calculate freq as like 2xx */
	if (cpu_is_xlp9xx())
		return 250000000;

	if (cpu_is_xlpii())
		return nlm_2xx_get_pic_frequency(node);
	else
		return 133333333;
}

unsigned int nlm_get_cpu_frequency(void)
{
	return nlm_get_core_frequency(0, 0);
}

/*
 * Fills upto 8 pairs of entries containing the DRAM map of a node
 * if n < 0, get dram map for all nodes
 */
int xlp_get_dram_map(int n, uint64_t *dram_map)
{
	uint64_t bridgebase, base, lim;
	uint32_t val;
	int i, node, rv;

	/* Look only at mapping on Node 0, we don't handle crazy configs */
	bridgebase = nlm_get_bridge_regbase(0);
	rv = 0;
	for (i = 0; i < 8; i++) {
		val = nlm_read_bridge_reg(bridgebase,
					BRIDGE_DRAM_NODE_TRANSLN(i));
		node = (val >> 1) & 0x3;
		if (n >= 0 && n != node)
			continue;
		val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
		val = (val >>  12) & 0xfffff;
		base = (uint64_t) val << 20;
		val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
		val = (val >>  12) & 0xfffff;
		if (val == 0)   /* BAR not used */
			continue;
		lim = ((uint64_t)val + 1) << 20;
		dram_map[rv] = base;
		dram_map[rv + 1] = lim;
		rv += 2;
	}
	return rv;
}
Commit	Line	Data
65040e22 J	1	/*
	2	* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
	3	* reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the NetLogic
	9	* license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or without
	12	* modification, are permitted provided that the following conditions
	13	* are met:
	14	*
	15	* 1. Redistributions of source code must retain the above copyright
	16	* notice, this list of conditions and the following disclaimer.
	17	* 2. Redistributions in binary form must reproduce the above copyright
	18	* notice, this list of conditions and the following disclaimer in
	19	* the documentation and/or other materials provided with the
	20	* distribution.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
	23	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	24	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	25	* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	27	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	28	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
	29	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
	30	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
	31	* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
	32	* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	#include <linux/types.h>
	36	#include <linux/kernel.h>
	37	#include <linux/mm.h>
	38	#include <linux/delay.h>
	39
	40	#include <asm/mipsregs.h>
	41	#include <asm/time.h>
	42
77ae798f	43	#include <asm/netlogic/common.h>
65040e22 J	44	#include <asm/netlogic/haldefs.h>
	45	#include <asm/netlogic/xlp-hal/iomap.h>
	46	#include <asm/netlogic/xlp-hal/xlp.h>
a2ba6cd6	47	#include <asm/netlogic/xlp-hal/bridge.h>
65040e22 J	48	#include <asm/netlogic/xlp-hal/pic.h>
	49	#include <asm/netlogic/xlp-hal/sys.h>
	50
65040e22	51	/* Main initialization */
77ae798f	52	void nlm_node_init(int node)
65040e22	53	{
77ae798f J	54	struct nlm_soc_info *nodep;
	55
	56	nodep = nlm_get_node(node);
	57	nodep->sysbase = nlm_get_sys_regbase(node);
	58	nodep->picbase = nlm_get_pic_regbase(node);
	59	nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
5513c760 J	60	if (cpu_is_xlp9xx())
	61	nodep->socbus = xlp9xx_get_socbus(node);
	62	else
	63	nodep->socbus = 0;
77ae798f	64	spin_lock_init(&nodep->piclock);
65040e22 J	65	}
	66
	67	int nlm_irq_to_irt(int irq)
	68	{
3c0553e7 J	69	uint64_t pcibase;
3c0553e7 J	70	int devoff, irt;
65040e22	71
d150cef4 J	72	/* bypass for 9xx */
	73	if (cpu_is_xlp9xx()) {
	74	switch (irq) {
	75	case PIC_UART_0_IRQ:
	76	return 133;
	77	case PIC_UART_1_IRQ:
	78	return 134;
	79	}
	80	return -1;
	81	}
	82
9eac3591	83	devoff = 0;
65040e22 J	84	switch (irq) {
65040e22 J	85	case PIC_UART_0_IRQ:
3c0553e7 J	86	devoff = XLP_IO_UART0_OFFSET(0);
3c0553e7 J	87	break;
65040e22	88	case PIC_UART_1_IRQ:
3c0553e7 J	89	devoff = XLP_IO_UART1_OFFSET(0);
3c0553e7 J	90	break;
57d7cdb6	91	case PIC_MMC_IRQ:
3c0553e7 J	92	devoff = XLP_IO_SD_OFFSET(0);
3c0553e7 J	93	break;
e5be1fd0	94	case PIC_I2C_0_IRQ: /* I2C will be fixed up */
57d7cdb6	95	case PIC_I2C_1_IRQ:
e5be1fd0 GR	96	case PIC_I2C_2_IRQ:
	97	case PIC_I2C_3_IRQ:
	98	if (cpu_is_xlpii())
	99	devoff = XLP2XX_IO_I2C_OFFSET(0);
	100	else
	101	devoff = XLP_IO_I2C0_OFFSET(0);
3c0553e7	102	break;
65040e22	103	default:
9eac3591 GR	104	if (cpu_is_xlpii()) {
	105	switch (irq) {
	106	/* XLP2XX has three XHCI USB controller */
	107	case PIC_2XX_XHCI_0_IRQ:
	108	devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
	109	break;
	110	case PIC_2XX_XHCI_1_IRQ:
	111	devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
	112	break;
	113	case PIC_2XX_XHCI_2_IRQ:
	114	devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
	115	break;
	116	}
	117	} else {
	118	switch (irq) {
	119	case PIC_EHCI_0_IRQ:
	120	devoff = XLP_IO_USB_EHCI0_OFFSET(0);
	121	break;
	122	case PIC_EHCI_1_IRQ:
	123	devoff = XLP_IO_USB_EHCI1_OFFSET(0);
	124	break;
	125	case PIC_OHCI_0_IRQ:
	126	devoff = XLP_IO_USB_OHCI0_OFFSET(0);
	127	break;
	128	case PIC_OHCI_1_IRQ:
	129	devoff = XLP_IO_USB_OHCI1_OFFSET(0);
	130	break;
	131	case PIC_OHCI_2_IRQ:
	132	devoff = XLP_IO_USB_OHCI2_OFFSET(0);
	133	break;
	134	case PIC_OHCI_3_IRQ:
	135	devoff = XLP_IO_USB_OHCI3_OFFSET(0);
	136	break;
	137	}
	138	}
65040e22	139	}
3c0553e7 J	140
	141	if (devoff != 0) {
	142	pcibase = nlm_pcicfg_base(devoff);
	143	irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
e5be1fd0 GR	144	/* HW weirdness, I2C IRT entry has to be fixed up */
	145	switch (irq) {
	146	case PIC_I2C_1_IRQ:
	147	irt = irt + 1; break;
	148	case PIC_I2C_2_IRQ:
	149	irt = irt + 2; break;
	150	case PIC_I2C_3_IRQ:
	151	irt = irt + 3; break;
	152	}
c24a8a7a J	153	} else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
c24a8a7a J	154	irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
3c0553e7	155	/* HW bug, PCI IRT entries are bad on early silicon, fix */
c24a8a7a J	156	irt = PIC_IRT_PCIE_LINK_INDEX(irq -
	157	PIC_PCIE_LINK_LEGACY_IRQ_BASE);
	158	} else if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) &&
	159	irq <= PIC_PCIE_LINK_MSI_IRQ(3)) {
	160	irt = -2;
	161	} else if (irq >= PIC_PCIE_MSIX_IRQ(0) &&
	162	irq <= PIC_PCIE_MSIX_IRQ(3)) {
	163	irt = -2;
3c0553e7 J	164	} else {
	165	irt = -1;
	166	}
	167	return irt;
65040e22 J	168	}
65040e22 J	169
77ae798f	170	unsigned int nlm_get_core_frequency(int node, int core)
65040e22	171	{
2aa54b20 J	172	unsigned int pll_divf, pll_divr, dfs_div, ext_div;
2aa54b20 J	173	unsigned int rstval, dfsval, denom;
77ae798f	174	uint64_t num, sysbase;
65040e22	175
77ae798f	176	sysbase = nlm_get_node(node)->sysbase;
861c0569 J	177	if (cpu_is_xlp9xx())
	178	rstval = nlm_read_sys_reg(sysbase, SYS_9XX_POWER_ON_RESET_CFG);
	179	else
	180	rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
57ceb4b0 GR	181	if (cpu_is_xlpii()) {
	182	num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
	183	denom = 3;
	184	} else {
	185	dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
	186	pll_divf = ((rstval >> 10) & 0x7f) + 1;
	187	pll_divr = ((rstval >> 8) & 0x3) + 1;
	188	ext_div = ((rstval >> 30) & 0x3) + 1;
	189	dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
	190
	191	num = 800000000ULL * pll_divf;
	192	denom = 3 * pll_divr * ext_div * dfs_div;
	193	}
65040e22 J	194	do_div(num, denom);
	195	return (unsigned int)num;
	196	}
2aa54b20	197
57ceb4b0 GR	198	/* Calculate Frequency to the PIC from PLL.
	199	* freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) /
	200	* ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
	201	*/
	202	static unsigned int nlm_2xx_get_pic_frequency(int node)
	203	{
	204	u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div;
	205	u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
	206	u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select;
	207
	208	sysbase = nlm_get_node(node)->sysbase;
	209
	210	/* Find ref_clk_base */
	211	ref_clk_select =
	212	(nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
	213	switch (ref_clk_select) {
	214	case 0:
	215	ref_clk = 200000000ULL;
	216	ref_div = 3;
	217	break;
	218	case 1:
	219	ref_clk = 100000000ULL;
	220	ref_div = 1;
	221	break;
	222	case 2:
	223	ref_clk = 125000000ULL;
	224	ref_div = 1;
	225	break;
	226	case 3:
	227	ref_clk = 400000000ULL;
	228	ref_div = 3;
	229	break;
	230	}
	231
	232	/* Find the clock source PLL device for PIC */
	233	reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3;
	234	switch (reg_select) {
	235	case 0:
	236	ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0);
	237	ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2);
	238	break;
	239	case 1:
	240	ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0));
	241	ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0));
	242	break;
	243	case 2:
	244	ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1));
	245	ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1));
	246	break;
	247	case 3:
	248	ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2));
	249	ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2));
	250	break;
	251	}
	252
	253	vco_post_div = (ctrl_val0 >> 5) & 0x7;
	254	pll_post_div = (ctrl_val0 >> 24) & 0x7;
	255	mdiv = ctrl_val2 & 0xff;
	256	fdiv = (ctrl_val2 >> 8) & 0xfff;
	257
	258	/* Find PLL post divider value */
	259	switch (pll_post_div) {
	260	case 1:
	261	pll_post_div = 2;
262	break;
263	case 3:
264	pll_post_div = 4;
265	break;
266	case 7:
267	pll_post_div = 8;
268	break;
269	case 6:
270	pll_post_div = 16;
271	break;
272	case 0:
273	default:
274	pll_post_div = 1;
275	break;
276	}
277
278	fdiv = fdiv/(1 << 13);
279	pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
280	pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;
281
282	if (pll_out_freq_den > 0)
283	do_div(pll_out_freq_num, pll_out_freq_den);
284
285	/* PIC post divider, which happens after PLL */
286	pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3;
287	do_div(pll_out_freq_num, 1 << pic_div);
288
289	return pll_out_freq_num;
290	}
291
292	unsigned int nlm_get_pic_frequency(int node)
293	{
d150cef4 J	294	/* TODO Has to calculate freq as like 2xx */
	295	if (cpu_is_xlp9xx())
	296	return 250000000;
	297
57ceb4b0 GR	298	if (cpu_is_xlpii())
	299	return nlm_2xx_get_pic_frequency(node);
	300	else
	301	return 133333333;
	302	}
	303
2aa54b20 J	304	unsigned int nlm_get_cpu_frequency(void)
2aa54b20 J	305	{
77ae798f	306	return nlm_get_core_frequency(0, 0);
2aa54b20	307	}
a2ba6cd6 J	308
	309	/*
	310	* Fills upto 8 pairs of entries containing the DRAM map of a node
	311	* if n < 0, get dram map for all nodes
	312	*/
	313	int xlp_get_dram_map(int n, uint64_t *dram_map)
	314	{
	315	uint64_t bridgebase, base, lim;
	316	uint32_t val;
	317	int i, node, rv;
	318
	319	/* Look only at mapping on Node 0, we don't handle crazy configs */
	320	bridgebase = nlm_get_bridge_regbase(0);
	321	rv = 0;
	322	for (i = 0; i < 8; i++) {
	323	val = nlm_read_bridge_reg(bridgebase,
	324	BRIDGE_DRAM_NODE_TRANSLN(i));
	325	node = (val >> 1) & 0x3;
	326	if (n >= 0 && n != node)
	327	continue;
	328	val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
	329	val = (val >> 12) & 0xfffff;
	330	base = (uint64_t) val << 20;
	331	val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
	332	val = (val >> 12) & 0xfffff;
	333	if (val == 0) /* BAR not used */
	334	continue;
	335	lim = ((uint64_t)val + 1) << 20;
	336	dram_map[rv] = base;
	337	dram_map[rv + 1] = lim;
	338	rv += 2;
	339	}
	340	return rv;
	341	}