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3a2f9b99 GR |
1 | /* |
2 | * Copyright 2011, Netlogic Microsystems. | |
3 | * Copyright 2004, Matt Porter <mporter@kernel.crashing.org> | |
4 | * | |
5 | * This file is licensed under the terms of the GNU General Public | |
6 | * License version 2. This program is licensed "as is" without any | |
7 | * warranty of any kind, whether express or implied. | |
8 | */ | |
9 | ||
10 | #include <linux/device.h> | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/ioport.h> | |
17 | #include <linux/resource.h> | |
18 | #include <linux/spi/flash.h> | |
19 | ||
20 | #include <linux/mtd/mtd.h> | |
21 | #include <linux/mtd/physmap.h> | |
22 | #include <linux/mtd/nand.h> | |
23 | #include <linux/mtd/partitions.h> | |
24 | ||
25 | #include <asm/netlogic/haldefs.h> | |
26 | #include <asm/netlogic/xlr/iomap.h> | |
27 | #include <asm/netlogic/xlr/flash.h> | |
28 | #include <asm/netlogic/xlr/bridge.h> | |
29 | #include <asm/netlogic/xlr/gpio.h> | |
30 | #include <asm/netlogic/xlr/xlr.h> | |
31 | ||
32 | /* | |
33 | * Default NOR partition layout | |
34 | */ | |
35 | static struct mtd_partition xlr_nor_parts[] = { | |
36 | { | |
37 | .name = "User FS", | |
38 | .offset = 0x800000, | |
70342287 | 39 | .size = MTDPART_SIZ_FULL, |
3a2f9b99 GR |
40 | } |
41 | }; | |
42 | ||
43 | /* | |
44 | * Default NAND partition layout | |
45 | */ | |
46 | static struct mtd_partition xlr_nand_parts[] = { | |
47 | { | |
48 | .name = "Root Filesystem", | |
70342287 | 49 | .offset = 64 * 64 * 2048, |
3a2f9b99 GR |
50 | .size = 432 * 64 * 2048, |
51 | }, | |
52 | { | |
53 | .name = "Home Filesystem", | |
70342287 RB |
54 | .offset = MTDPART_OFS_APPEND, |
55 | .size = MTDPART_SIZ_FULL, | |
3a2f9b99 GR |
56 | }, |
57 | }; | |
58 | ||
59 | /* Use PHYSMAP flash for NOR */ | |
60 | struct physmap_flash_data xlr_nor_data = { | |
61 | .width = 2, | |
62 | .parts = xlr_nor_parts, | |
63 | .nr_parts = ARRAY_SIZE(xlr_nor_parts), | |
64 | }; | |
65 | ||
66 | static struct resource xlr_nor_res[] = { | |
67 | { | |
68 | .flags = IORESOURCE_MEM, | |
69 | }, | |
70 | }; | |
71 | ||
72 | static struct platform_device xlr_nor_dev = { | |
73 | .name = "physmap-flash", | |
74 | .dev = { | |
75 | .platform_data = &xlr_nor_data, | |
76 | }, | |
70342287 RB |
77 | .num_resources = ARRAY_SIZE(xlr_nor_res), |
78 | .resource = xlr_nor_res, | |
3a2f9b99 GR |
79 | }; |
80 | ||
81 | const char *xlr_part_probes[] = { "cmdlinepart", NULL }; | |
82 | ||
83 | /* | |
84 | * Use "gen_nand" driver for NAND flash | |
85 | * | |
86 | * There seems to be no way to store a private pointer containing | |
87 | * platform specific info in gen_nand drivier. We will use a global | |
88 | * struct for now, since we currently have only one NAND chip per board. | |
89 | */ | |
90 | struct xlr_nand_flash_priv { | |
91 | int cs; | |
92 | uint64_t flash_mmio; | |
93 | }; | |
94 | ||
95 | static struct xlr_nand_flash_priv nand_priv; | |
96 | ||
97 | static void xlr_nand_ctrl(struct mtd_info *mtd, int cmd, | |
98 | unsigned int ctrl) | |
99 | { | |
100 | if (ctrl & NAND_CLE) | |
101 | nlm_write_reg(nand_priv.flash_mmio, | |
102 | FLASH_NAND_CLE(nand_priv.cs), cmd); | |
103 | else if (ctrl & NAND_ALE) | |
104 | nlm_write_reg(nand_priv.flash_mmio, | |
105 | FLASH_NAND_ALE(nand_priv.cs), cmd); | |
106 | } | |
107 | ||
108 | struct platform_nand_data xlr_nand_data = { | |
109 | .chip = { | |
110 | .nr_chips = 1, | |
111 | .nr_partitions = ARRAY_SIZE(xlr_nand_parts), | |
112 | .chip_delay = 50, | |
113 | .partitions = xlr_nand_parts, | |
114 | .part_probe_types = xlr_part_probes, | |
115 | }, | |
116 | .ctrl = { | |
117 | .cmd_ctrl = xlr_nand_ctrl, | |
118 | }, | |
119 | }; | |
120 | ||
121 | static struct resource xlr_nand_res[] = { | |
122 | { | |
123 | .flags = IORESOURCE_MEM, | |
124 | }, | |
125 | }; | |
126 | ||
127 | static struct platform_device xlr_nand_dev = { | |
128 | .name = "gen_nand", | |
129 | .id = -1, | |
130 | .num_resources = ARRAY_SIZE(xlr_nand_res), | |
131 | .resource = xlr_nand_res, | |
132 | .dev = { | |
133 | .platform_data = &xlr_nand_data, | |
134 | } | |
135 | }; | |
136 | ||
137 | /* | |
138 | * XLR/XLS supports upto 8 devices on its FLASH interface. The value in | |
139 | * FLASH_BAR (on the MEM/IO bridge) gives the base for mapping all the | |
140 | * flash devices. | |
141 | * Under this, each flash device has an offset and size given by the | |
142 | * CSBASE_ADDR and CSBASE_MASK registers for the device. | |
143 | * | |
144 | * The CSBASE_ registers are expected to be setup by the bootloader. | |
145 | */ | |
146 | static void setup_flash_resource(uint64_t flash_mmio, | |
147 | uint64_t flash_map_base, int cs, struct resource *res) | |
148 | { | |
149 | u32 base, mask; | |
150 | ||
151 | base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs)); | |
152 | mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs)); | |
153 | ||
154 | res->start = flash_map_base + ((unsigned long)base << 16); | |
155 | res->end = res->start + (mask + 1) * 64 * 1024; | |
156 | } | |
157 | ||
158 | static int __init xlr_flash_init(void) | |
159 | { | |
160 | uint64_t gpio_mmio, flash_mmio, flash_map_base; | |
161 | u32 gpio_resetcfg, flash_bar; | |
162 | int cs, boot_nand, boot_nor; | |
163 | ||
164 | /* Flash address bits 39:24 is in bridge flash BAR */ | |
165 | flash_bar = nlm_read_reg(nlm_io_base, BRIDGE_FLASH_BAR); | |
166 | flash_map_base = (flash_bar & 0xffff0000) << 8; | |
167 | ||
168 | gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET); | |
169 | flash_mmio = nlm_mmio_base(NETLOGIC_IO_FLASH_OFFSET); | |
170 | ||
171 | /* Get the chip reset config */ | |
172 | gpio_resetcfg = nlm_read_reg(gpio_mmio, GPIO_PWRON_RESET_CFG_REG); | |
173 | ||
174 | /* Check for boot flash type */ | |
175 | boot_nor = boot_nand = 0; | |
176 | if (nlm_chip_is_xls()) { | |
177 | /* On XLS, check boot from NAND bit (GPIO reset reg bit 16) */ | |
178 | if (gpio_resetcfg & (1 << 16)) | |
179 | boot_nand = 1; | |
180 | ||
181 | /* check boot from PCMCIA, (GPIO reset reg bit 15 */ | |
182 | if ((gpio_resetcfg & (1 << 15)) == 0) | |
183 | boot_nor = 1; /* not set, booted from NOR */ | |
184 | } else { /* XLR */ | |
185 | /* check boot from PCMCIA (bit 16 in GPIO reset on XLR) */ | |
186 | if ((gpio_resetcfg & (1 << 16)) == 0) | |
187 | boot_nor = 1; /* not set, booted from NOR */ | |
188 | } | |
189 | ||
190 | /* boot flash at chip select 0 */ | |
191 | cs = 0; | |
192 | ||
193 | if (boot_nand) { | |
194 | nand_priv.cs = cs; | |
195 | nand_priv.flash_mmio = flash_mmio; | |
196 | setup_flash_resource(flash_mmio, flash_map_base, cs, | |
197 | xlr_nand_res); | |
198 | ||
199 | /* Initialize NAND flash at CS 0 */ | |
200 | nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs), | |
201 | FLASH_NAND_CSDEV_PARAM); | |
202 | nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs), | |
203 | FLASH_NAND_CSTIME_PARAMA); | |
204 | nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs), | |
205 | FLASH_NAND_CSTIME_PARAMB); | |
206 | ||
207 | pr_info("ChipSelect %d: NAND Flash %pR\n", cs, xlr_nand_res); | |
208 | return platform_device_register(&xlr_nand_dev); | |
209 | } | |
210 | ||
211 | if (boot_nor) { | |
212 | setup_flash_resource(flash_mmio, flash_map_base, cs, | |
213 | xlr_nor_res); | |
214 | pr_info("ChipSelect %d: NOR Flash %pR\n", cs, xlr_nor_res); | |
215 | return platform_device_register(&xlr_nor_dev); | |
216 | } | |
217 | return 0; | |
218 | } | |
219 | ||
220 | arch_initcall(xlr_flash_init); |