[mirror_ubuntu-bionic-kernel.git] / arch / mips / oprofile / op_model_mipsxx.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2004, 05, 06 by Ralf Baechle
 * Copyright (C) 2005 by MIPS Technologies, Inc.
 */
#include <linux/cpumask.h>
#include <linux/oprofile.h>
#include <linux/interrupt.h>
#include <linux/smp.h>
#include <asm/irq_regs.h>

#include "op_impl.h"

#define M_PERFCTL_EXL			(1UL      <<  0)
#define M_PERFCTL_KERNEL		(1UL      <<  1)
#define M_PERFCTL_SUPERVISOR		(1UL      <<  2)
#define M_PERFCTL_USER			(1UL      <<  3)
#define M_PERFCTL_INTERRUPT_ENABLE	(1UL      <<  4)
#define M_PERFCTL_EVENT(event)		(((event) & 0x3ff)  << 5)
#define M_PERFCTL_VPEID(vpe)		((vpe)    << 16)
#define M_PERFCTL_MT_EN(filter)		((filter) << 20)
#define    M_TC_EN_ALL			M_PERFCTL_MT_EN(0)
#define    M_TC_EN_VPE			M_PERFCTL_MT_EN(1)
#define    M_TC_EN_TC			M_PERFCTL_MT_EN(2)
#define M_PERFCTL_TCID(tcid)		((tcid)   << 22)
#define M_PERFCTL_WIDE			(1UL      << 30)
#define M_PERFCTL_MORE			(1UL      << 31)

#define M_COUNTER_OVERFLOW		(1UL      << 31)

#ifdef CONFIG_MIPS_MT_SMP
#define WHAT		(M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id()))
#define vpe_id()	smp_processor_id()

/*
 * The number of bits to shift to convert between counters per core and
 * counters per VPE.  There is no reasonable interface atm to obtain the
 * number of VPEs used by Linux and in the 34K this number is fixed to two
 * anyways so we hardcore a few things here for the moment.  The way it's
 * done here will ensure that oprofile VSMP kernel will run right on a lesser
 * core like a 24K also or with maxcpus=1.
 */
static inline unsigned int vpe_shift(void)
{
	if (num_possible_cpus() > 1)
		return 1;

	return 0;
}

#else

#define WHAT		0
#define vpe_id()	0

static inline unsigned int vpe_shift(void)
{
	return 0;
}

#endif

static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
{
	return counters >> vpe_shift();
}

static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
{
	return counters << vpe_shift();
}

#define __define_perf_accessors(r, n, np)				\
									\
static inline unsigned int r_c0_ ## r ## n(void)			\
{									\
	unsigned int cpu = vpe_id();					\
									\
	switch (cpu) {							\
	case 0:								\
		return read_c0_ ## r ## n();				\
	case 1:								\
		return read_c0_ ## r ## np();				\
	default:							\
		BUG();							\
	}								\
	return 0;							\
}									\
									\
static inline void w_c0_ ## r ## n(unsigned int value)			\
{									\
	unsigned int cpu = vpe_id();					\
									\
	switch (cpu) {							\
	case 0:								\
		write_c0_ ## r ## n(value);				\
		return;							\
	case 1:								\
		write_c0_ ## r ## np(value);				\
		return;							\
	default:							\
		BUG();							\
	}								\
	return;								\
}									\

__define_perf_accessors(perfcntr, 0, 2)
__define_perf_accessors(perfcntr, 1, 3)
__define_perf_accessors(perfcntr, 2, 0)
__define_perf_accessors(perfcntr, 3, 1)

__define_perf_accessors(perfctrl, 0, 2)
__define_perf_accessors(perfctrl, 1, 3)
__define_perf_accessors(perfctrl, 2, 0)
__define_perf_accessors(perfctrl, 3, 1)

struct op_mips_model op_model_mipsxx_ops;

static struct mipsxx_register_config {
	unsigned int control[4];
	unsigned int counter[4];
} reg;

/* Compute all of the registers in preparation for enabling profiling.  */

static void mipsxx_reg_setup(struct op_counter_config *ctr)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;
	int i;

	/* Compute the performance counter control word.  */
	for (i = 0; i < counters; i++) {
		reg.control[i] = 0;
		reg.counter[i] = 0;

		if (!ctr[i].enabled)
			continue;

		reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
		                 M_PERFCTL_INTERRUPT_ENABLE;
		if (ctr[i].kernel)
			reg.control[i] |= M_PERFCTL_KERNEL;
		if (ctr[i].user)
			reg.control[i] |= M_PERFCTL_USER;
		if (ctr[i].exl)
			reg.control[i] |= M_PERFCTL_EXL;
		reg.counter[i] = 0x80000000 - ctr[i].count;
	}
}

/* Program all of the registers in preparation for enabling profiling.  */

static void mipsxx_cpu_setup(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
		w_c0_perfcntr3(reg.counter[3]);
	case 3:
		w_c0_perfctrl2(0);
		w_c0_perfcntr2(reg.counter[2]);
	case 2:
		w_c0_perfctrl1(0);
		w_c0_perfcntr1(reg.counter[1]);
	case 1:
		w_c0_perfctrl0(0);
		w_c0_perfcntr0(reg.counter[0]);
	}
}

/* Start all counters on current CPU */
static void mipsxx_cpu_start(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(WHAT | reg.control[3]);
	case 3:
		w_c0_perfctrl2(WHAT | reg.control[2]);
	case 2:
		w_c0_perfctrl1(WHAT | reg.control[1]);
	case 1:
		w_c0_perfctrl0(WHAT | reg.control[0]);
	}
}

/* Stop all counters on current CPU */
static void mipsxx_cpu_stop(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
	case 3:
		w_c0_perfctrl2(0);
	case 2:
		w_c0_perfctrl1(0);
	case 1:
		w_c0_perfctrl0(0);
	}
}

static int mipsxx_perfcount_handler(void)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;
	unsigned int control;
	unsigned int counter;
	int handled = IRQ_NONE;

	if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
		return handled;

	switch (counters) {
#define HANDLE_COUNTER(n)						\
	case n + 1:							\
		control = r_c0_perfctrl ## n();				\
		counter = r_c0_perfcntr ## n();				\
		if ((control & M_PERFCTL_INTERRUPT_ENABLE) &&		\
		    (counter & M_COUNTER_OVERFLOW)) {			\
			oprofile_add_sample(get_irq_regs(), n);		\
			w_c0_perfcntr ## n(reg.counter[n]);		\
			handled = IRQ_HANDLED;				\
		}
	HANDLE_COUNTER(3)
	HANDLE_COUNTER(2)
	HANDLE_COUNTER(1)
	HANDLE_COUNTER(0)
	}

	return handled;
}

#define M_CONFIG1_PC	(1 << 4)

static inline int __n_counters(void)
{
	if (!(read_c0_config1() & M_CONFIG1_PC))
		return 0;
	if (!(r_c0_perfctrl0() & M_PERFCTL_MORE))
		return 1;
	if (!(r_c0_perfctrl1() & M_PERFCTL_MORE))
		return 2;
	if (!(r_c0_perfctrl2() & M_PERFCTL_MORE))
		return 3;

	return 4;
}

static inline int n_counters(void)
{
	int counters;

	switch (current_cpu_type()) {
	case CPU_R10000:
		counters = 2;
		break;

	case CPU_R12000:
	case CPU_R14000:
		counters = 4;
		break;

	default:
		counters = __n_counters();
	}

	return counters;
}

static inline void reset_counters(int counters)
{
	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
		w_c0_perfcntr3(0);
	case 3:
		w_c0_perfctrl2(0);
		w_c0_perfcntr2(0);
	case 2:
		w_c0_perfctrl1(0);
		w_c0_perfcntr1(0);
	case 1:
		w_c0_perfctrl0(0);
		w_c0_perfcntr0(0);
	}
}

static int __init mipsxx_init(void)
{
	int counters;

	counters = n_counters();
	if (counters == 0) {
		printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
		return -ENODEV;
	}

	reset_counters(counters);

	counters = counters_total_to_per_cpu(counters);

	op_model_mipsxx_ops.num_counters = counters;
	switch (current_cpu_type()) {
	case CPU_20KC:
		op_model_mipsxx_ops.cpu_type = "mips/20K";
		break;

	case CPU_24K:
		op_model_mipsxx_ops.cpu_type = "mips/24K";
		break;

	case CPU_25KF:
		op_model_mipsxx_ops.cpu_type = "mips/25K";
		break;

	case CPU_34K:
		op_model_mipsxx_ops.cpu_type = "mips/34K";
		break;

	case CPU_74K:
		op_model_mipsxx_ops.cpu_type = "mips/74K";
		break;

	case CPU_5KC:
		op_model_mipsxx_ops.cpu_type = "mips/5K";
		break;

	case CPU_R10000:
		if ((current_cpu_data.processor_id & 0xff) == 0x20)
			op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
		else
			op_model_mipsxx_ops.cpu_type = "mips/r10000";
		break;

	case CPU_R12000:
	case CPU_R14000:
		op_model_mipsxx_ops.cpu_type = "mips/r12000";
		break;

	case CPU_SB1:
	case CPU_SB1A:
		op_model_mipsxx_ops.cpu_type = "mips/sb1";
		break;

	default:
		printk(KERN_ERR "Profiling unsupported for this CPU\n");

		return -ENODEV;
	}

	perf_irq = mipsxx_perfcount_handler;

	return 0;
}

static void mipsxx_exit(void)
{
	int counters = op_model_mipsxx_ops.num_counters;

	counters = counters_per_cpu_to_total(counters);
	reset_counters(counters);

	perf_irq = null_perf_irq;
}

struct op_mips_model op_model_mipsxx_ops = {
	.reg_setup	= mipsxx_reg_setup,
	.cpu_setup	= mipsxx_cpu_setup,
	.init		= mipsxx_init,
	.exit		= mipsxx_exit,
	.cpu_start	= mipsxx_cpu_start,
	.cpu_stop	= mipsxx_cpu_stop,
};
Commit	Line	Data
54176736 RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
937a8015	6	* Copyright (C) 2004, 05, 06 by Ralf Baechle
54176736 RB	7	* Copyright (C) 2005 by MIPS Technologies, Inc.
54176736 RB	8	*/
5e2862eb	9	#include <linux/cpumask.h>
54176736 RB	10	#include <linux/oprofile.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/smp.h>
937a8015	13	#include <asm/irq_regs.h>
54176736 RB	14
	15	#include "op_impl.h"
	16
92c7b62f RB	17	#define M_PERFCTL_EXL (1UL << 0)
	18	#define M_PERFCTL_KERNEL (1UL << 1)
	19	#define M_PERFCTL_SUPERVISOR (1UL << 2)
	20	#define M_PERFCTL_USER (1UL << 3)
	21	#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
39a51109	22	#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
92c7b62f RB	23	#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
	24	#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
	25	#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
	26	#define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
	27	#define M_TC_EN_TC M_PERFCTL_MT_EN(2)
	28	#define M_PERFCTL_TCID(tcid) ((tcid) << 22)
	29	#define M_PERFCTL_WIDE (1UL << 30)
	30	#define M_PERFCTL_MORE (1UL << 31)
	31
	32	#define M_COUNTER_OVERFLOW (1UL << 31)
	33
	34	#ifdef CONFIG_MIPS_MT_SMP
be609f35 RB	35	#define WHAT (M_TC_EN_VPE \| M_PERFCTL_VPEID(smp_processor_id()))
be609f35 RB	36	#define vpe_id() smp_processor_id()
5e2862eb RB	37
	38	/*
	39	* The number of bits to shift to convert between counters per core and
	40	* counters per VPE. There is no reasonable interface atm to obtain the
	41	* number of VPEs used by Linux and in the 34K this number is fixed to two
	42	* anyways so we hardcore a few things here for the moment. The way it's
	43	* done here will ensure that oprofile VSMP kernel will run right on a lesser
	44	* core like a 24K also or with maxcpus=1.
	45	*/
	46	static inline unsigned int vpe_shift(void)
	47	{
	48	if (num_possible_cpus() > 1)
	49	return 1;
	50
	51	return 0;
	52	}
	53
92c7b62f	54	#else
5e2862eb	55
be609f35	56	#define WHAT 0
6f4c5bde	57	#define vpe_id() 0
5e2862eb RB	58
	59	static inline unsigned int vpe_shift(void)
	60	{
	61	return 0;
	62	}
	63
92c7b62f	64	#endif
54176736	65
5e2862eb RB	66	static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
	67	{
	68	return counters >> vpe_shift();
	69	}
	70
	71	static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
	72	{
	73	return counters << vpe_shift();
	74	}
	75
92c7b62f RB	76	#define __define_perf_accessors(r, n, np) \
	77	\
	78	static inline unsigned int r_c0_ ## r ## n(void) \
	79	{ \
be609f35	80	unsigned int cpu = vpe_id(); \
92c7b62f RB	81	\
	82	switch (cpu) { \
	83	case 0: \
	84	return read_c0_ ## r ## n(); \
	85	case 1: \
	86	return read_c0_ ## r ## np(); \
	87	default: \
	88	BUG(); \
	89	} \
30f244ae	90	return 0; \
92c7b62f RB	91	} \
	92	\
	93	static inline void w_c0_ ## r ## n(unsigned int value) \
	94	{ \
be609f35	95	unsigned int cpu = vpe_id(); \
92c7b62f RB	96	\
	97	switch (cpu) { \
	98	case 0: \
	99	write_c0_ ## r ## n(value); \
	100	return; \
	101	case 1: \
	102	write_c0_ ## r ## np(value); \
	103	return; \
	104	default: \
	105	BUG(); \
	106	} \
30f244ae	107	return; \
92c7b62f RB	108	} \
	109
	110	__define_perf_accessors(perfcntr, 0, 2)
	111	__define_perf_accessors(perfcntr, 1, 3)
795a2258 CD	112	__define_perf_accessors(perfcntr, 2, 0)
795a2258 CD	113	__define_perf_accessors(perfcntr, 3, 1)
92c7b62f RB	114
	115	__define_perf_accessors(perfctrl, 0, 2)
	116	__define_perf_accessors(perfctrl, 1, 3)
795a2258 CD	117	__define_perf_accessors(perfctrl, 2, 0)
795a2258 CD	118	__define_perf_accessors(perfctrl, 3, 1)
54176736	119
1acf1ca7	120	struct op_mips_model op_model_mipsxx_ops;
54176736 RB	121
	122	static struct mipsxx_register_config {
	123	unsigned int control[4];
	124	unsigned int counter[4];
	125	} reg;
	126
	127	/* Compute all of the registers in preparation for enabling profiling. */
	128
	129	static void mipsxx_reg_setup(struct op_counter_config *ctr)
	130	{
1acf1ca7	131	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	132	int i;
	133
	134	/* Compute the performance counter control word. */
54176736 RB	135	for (i = 0; i < counters; i++) {
	136	reg.control[i] = 0;
	137	reg.counter[i] = 0;
	138
	139	if (!ctr[i].enabled)
	140	continue;
	141
	142	reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) \|
	143	M_PERFCTL_INTERRUPT_ENABLE;
	144	if (ctr[i].kernel)
	145	reg.control[i] \|= M_PERFCTL_KERNEL;
	146	if (ctr[i].user)
	147	reg.control[i] \|= M_PERFCTL_USER;
	148	if (ctr[i].exl)
	149	reg.control[i] \|= M_PERFCTL_EXL;
	150	reg.counter[i] = 0x80000000 - ctr[i].count;
	151	}
	152	}
	153
	154	/* Program all of the registers in preparation for enabling profiling. */
	155
49a89efb	156	static void mipsxx_cpu_setup(void *args)
54176736	157	{
1acf1ca7	158	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	159
	160	switch (counters) {
	161	case 4:
92c7b62f RB	162	w_c0_perfctrl3(0);
92c7b62f RB	163	w_c0_perfcntr3(reg.counter[3]);
54176736	164	case 3:
92c7b62f RB	165	w_c0_perfctrl2(0);
92c7b62f RB	166	w_c0_perfcntr2(reg.counter[2]);
54176736	167	case 2:
92c7b62f RB	168	w_c0_perfctrl1(0);
92c7b62f RB	169	w_c0_perfcntr1(reg.counter[1]);
54176736	170	case 1:
92c7b62f RB	171	w_c0_perfctrl0(0);
92c7b62f RB	172	w_c0_perfcntr0(reg.counter[0]);
54176736 RB	173	}
	174	}
	175
	176	/* Start all counters on current CPU */
	177	static void mipsxx_cpu_start(void *args)
	178	{
1acf1ca7	179	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	180
	181	switch (counters) {
	182	case 4:
92c7b62f	183	w_c0_perfctrl3(WHAT \| reg.control[3]);
54176736	184	case 3:
92c7b62f	185	w_c0_perfctrl2(WHAT \| reg.control[2]);
54176736	186	case 2:
92c7b62f	187	w_c0_perfctrl1(WHAT \| reg.control[1]);
54176736	188	case 1:
92c7b62f	189	w_c0_perfctrl0(WHAT \| reg.control[0]);
54176736 RB	190	}
	191	}
	192
	193	/* Stop all counters on current CPU */
	194	static void mipsxx_cpu_stop(void *args)
	195	{
1acf1ca7	196	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	197
	198	switch (counters) {
	199	case 4:
92c7b62f	200	w_c0_perfctrl3(0);
54176736	201	case 3:
92c7b62f	202	w_c0_perfctrl2(0);
54176736	203	case 2:
92c7b62f	204	w_c0_perfctrl1(0);
54176736	205	case 1:
92c7b62f	206	w_c0_perfctrl0(0);
54176736 RB	207	}
	208	}
	209
937a8015	210	static int mipsxx_perfcount_handler(void)
54176736	211	{
1acf1ca7	212	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	213	unsigned int control;
54176736 RB	214	unsigned int counter;
ffe9ee47 CD	215	int handled = IRQ_NONE;
	216
	217	if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
	218	return handled;
54176736 RB	219
	220	switch (counters) {
	221	#define HANDLE_COUNTER(n) \
	222	case n + 1: \
92c7b62f RB	223	control = r_c0_perfctrl ## n(); \
92c7b62f RB	224	counter = r_c0_perfcntr ## n(); \
54176736 RB	225	if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \
54176736 RB	226	(counter & M_COUNTER_OVERFLOW)) { \
937a8015	227	oprofile_add_sample(get_irq_regs(), n); \
92c7b62f	228	w_c0_perfcntr ## n(reg.counter[n]); \
ffe9ee47	229	handled = IRQ_HANDLED; \
54176736 RB	230	}
	231	HANDLE_COUNTER(3)
	232	HANDLE_COUNTER(2)
	233	HANDLE_COUNTER(1)
	234	HANDLE_COUNTER(0)
	235	}
ba339c03 RB	236
ba339c03 RB	237	return handled;
54176736 RB	238	}
	239
	240	#define M_CONFIG1_PC (1 << 4)
	241
92c7b62f	242	static inline int __n_counters(void)
54176736 RB	243	{
	244	if (!(read_c0_config1() & M_CONFIG1_PC))
	245	return 0;
92c7b62f	246	if (!(r_c0_perfctrl0() & M_PERFCTL_MORE))
54176736	247	return 1;
92c7b62f	248	if (!(r_c0_perfctrl1() & M_PERFCTL_MORE))
54176736	249	return 2;
92c7b62f	250	if (!(r_c0_perfctrl2() & M_PERFCTL_MORE))
54176736 RB	251	return 3;
	252
	253	return 4;
	254	}
	255
92c7b62f RB	256	static inline int n_counters(void)
92c7b62f RB	257	{
714cfe78 RB	258	int counters;
714cfe78 RB	259
10cc3529	260	switch (current_cpu_type()) {
714cfe78 RB	261	case CPU_R10000:
714cfe78 RB	262	counters = 2;
148171b2	263	break;
714cfe78 RB	264
	265	case CPU_R12000:
	266	case CPU_R14000:
	267	counters = 4;
148171b2	268	break;
714cfe78 RB	269
	270	default:
	271	counters = __n_counters();
	272	}
92c7b62f	273
92c7b62f RB	274	return counters;
	275	}
	276
54176736 RB	277	static inline void reset_counters(int counters)
	278	{
	279	switch (counters) {
	280	case 4:
92c7b62f RB	281	w_c0_perfctrl3(0);
92c7b62f RB	282	w_c0_perfcntr3(0);
54176736	283	case 3:
92c7b62f RB	284	w_c0_perfctrl2(0);
92c7b62f RB	285	w_c0_perfcntr2(0);
54176736	286	case 2:
92c7b62f RB	287	w_c0_perfctrl1(0);
92c7b62f RB	288	w_c0_perfcntr1(0);
54176736	289	case 1:
92c7b62f RB	290	w_c0_perfctrl0(0);
92c7b62f RB	291	w_c0_perfcntr0(0);
54176736 RB	292	}
	293	}
	294
	295	static int __init mipsxx_init(void)
	296	{
	297	int counters;
	298
	299	counters = n_counters();
9efeae9a RB	300	if (counters == 0) {
9efeae9a RB	301	printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
54176736	302	return -ENODEV;
9efeae9a	303	}
54176736 RB	304
	305	reset_counters(counters);
	306
5e2862eb	307	counters = counters_total_to_per_cpu(counters);
795a2258	308
1acf1ca7	309	op_model_mipsxx_ops.num_counters = counters;
10cc3529	310	switch (current_cpu_type()) {
2065988e	311	case CPU_20KC:
1acf1ca7	312	op_model_mipsxx_ops.cpu_type = "mips/20K";
2065988e RB	313	break;
2065988e RB	314
54176736	315	case CPU_24K:
1acf1ca7	316	op_model_mipsxx_ops.cpu_type = "mips/24K";
54176736 RB	317	break;
54176736 RB	318
2065988e	319	case CPU_25KF:
1acf1ca7	320	op_model_mipsxx_ops.cpu_type = "mips/25K";
2065988e RB	321	break;
2065988e RB	322
fcfd980c	323	case CPU_34K:
1acf1ca7	324	op_model_mipsxx_ops.cpu_type = "mips/34K";
fcfd980c	325	break;
c620953c CD	326
c620953c CD	327	case CPU_74K:
1acf1ca7	328	op_model_mipsxx_ops.cpu_type = "mips/74K";
c620953c	329	break;
fcfd980c	330
2065988e	331	case CPU_5KC:
1acf1ca7	332	op_model_mipsxx_ops.cpu_type = "mips/5K";
2065988e RB	333	break;
2065988e RB	334
714cfe78 RB	335	case CPU_R10000:
	336	if ((current_cpu_data.processor_id & 0xff) == 0x20)
	337	op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
	338	else
	339	op_model_mipsxx_ops.cpu_type = "mips/r10000";
	340	break;
	341
	342	case CPU_R12000:
	343	case CPU_R14000:
	344	op_model_mipsxx_ops.cpu_type = "mips/r12000";
	345	break;
	346
c03bc121 MM	347	case CPU_SB1:
c03bc121 MM	348	case CPU_SB1A:
1acf1ca7	349	op_model_mipsxx_ops.cpu_type = "mips/sb1";
c03bc121 MM	350	break;
c03bc121 MM	351
54176736 RB	352	default:
	353	printk(KERN_ERR "Profiling unsupported for this CPU\n");
	354
	355	return -ENODEV;
	356	}
	357
	358	perf_irq = mipsxx_perfcount_handler;
	359
	360	return 0;
	361	}
	362
	363	static void mipsxx_exit(void)
	364	{
795a2258	365	int counters = op_model_mipsxx_ops.num_counters;
5e2862eb RB	366
5e2862eb RB	367	counters = counters_per_cpu_to_total(counters);
795a2258	368	reset_counters(counters);
54176736 RB	369
	370	perf_irq = null_perf_irq;
	371	}
	372
1acf1ca7	373	struct op_mips_model op_model_mipsxx_ops = {
54176736 RB	374	.reg_setup = mipsxx_reg_setup,
	375	.cpu_setup = mipsxx_cpu_setup,
	376	.init = mipsxx_init,
	377	.exit = mipsxx_exit,
	378	.cpu_start = mipsxx_cpu_start,
	379	.cpu_stop = mipsxx_cpu_stop,
	380	};