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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | #include <linux/init.h> |
3 | #include <linux/kernel.h> | |
4 | #include <linux/pci.h> | |
5 | #include <asm/ip32/ip32_ints.h> | |
6 | /* | |
7 | * O2 has up to 5 PCI devices connected into the MACE bridge. The device | |
8 | * map looks like this: | |
9 | * | |
10 | * 0 aic7xxx 0 | |
11 | * 1 aic7xxx 1 | |
12 | * 2 expansion slot | |
13 | * 3 N/C | |
14 | * 4 N/C | |
15 | */ | |
16 | ||
17 | #define SCSI0 MACEPCI_SCSI0_IRQ | |
18 | #define SCSI1 MACEPCI_SCSI1_IRQ | |
19 | #define INTA0 MACEPCI_SLOT0_IRQ | |
20 | #define INTA1 MACEPCI_SLOT1_IRQ | |
21 | #define INTA2 MACEPCI_SLOT2_IRQ | |
22 | #define INTB MACEPCI_SHARED0_IRQ | |
23 | #define INTC MACEPCI_SHARED1_IRQ | |
24 | #define INTD MACEPCI_SHARED2_IRQ | |
19a8d6b7 | 25 | static char irq_tab_mace[][5] = { |
70342287 RB |
26 | /* Dummy INT#A INT#B INT#C INT#D */ |
27 | {0, 0, 0, 0, 0}, /* This is placeholder row - never used */ | |
28 | {0, SCSI0, SCSI0, SCSI0, SCSI0}, | |
29 | {0, SCSI1, SCSI1, SCSI1, SCSI1}, | |
30 | {0, INTA0, INTB, INTC, INTD}, | |
31 | {0, INTA1, INTC, INTD, INTB}, | |
32 | {0, INTA2, INTD, INTB, INTC}, | |
1da177e4 LT |
33 | }; |
34 | ||
35 | ||
36 | /* | |
37 | * Given a PCI slot number (a la PCI_SLOT(...)) and the interrupt pin of | |
38 | * the device (1-4 => A-D), tell what irq to use. Note that we don't | |
39 | * in theory have slots 4 and 5, and we never normally use the shared | |
40 | * irqs. I suppose a device without a pin A will thank us for doing it | |
41 | * right if there exists such a broken piece of crap. | |
42 | */ | |
19a8d6b7 | 43 | int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
1da177e4 LT |
44 | { |
45 | return irq_tab_mace[slot][pin]; | |
46 | } | |
47 | ||
48 | /* Do platform specific device initialization at pci_enable_device() time */ | |
49 | int pcibios_plat_dev_init(struct pci_dev *dev) | |
50 | { | |
51 | return 0; | |
52 | } |